coreboot May 2003

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jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by Deepak Kotian 09 May '03

09 May '03

Hi, after putting some debug statements, it seems the LinuxBIOS resets after the jmp instruction is boot.c ( " jmp *%%eax\n\t" in jmp_to_elf_entry) fails. I am using ETHERBOOT payload with IDE support. Is it because the ram initialization is not proper or something, has anyone experienced this kind of problem. Any pointers, why it should fail over here. Here is the extract of the log ... ********* calling elf load... New segment addr 0x94000 size 0x8128 offset 0x60 filesize 0x38d4 (cleaned up) New segment addr 0x94000 size 0x8128 offset 0x60 filesize 0x38d4 Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000008128 filesz: 0x00 000000000038d4 Clearing Segment: addr: 0x00000000000978d4 memsz: 0x0000000000004854 Jumping to boot code at 0x94000 LinuxBIOS-1.0.0 Thu May 1 04:29:36 IST 2003 starting... Ram1 ********* Regards Deepak

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Re: jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by dkotian3＠vsnl.net 09 May '03

09 May '03

I have enabled RAMTEST(ramtest.inc) in the LinuxBIOS, it seems to be running at a very slow pace.Hope it finishes off by today. *****Extract***** dump northbridge: 00: 86 80 24 71 06 00 80 00 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 00 24 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 28 53 09 3c 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: c6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 eb fb 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 Done. Testing SDRAM : 80000a00-ffff0f30 SDRAM fill: 887e0000 *****Extract***** The number(887?????) increments at a very slow pace and has been more than an hour now. Moreover, I have 64MB ram, does the above range of test look OK. If has basically happened after changing some parameter in the North Bridge. I have run ramtest before as well without the changes. ****Extract Before ***** Testing SDRAM : 00000000-0009ffff SDRAM fill: 000000000001000000020000000300000004000000050000000600000007000000080000000900000009ffff SDRAM verify: 000000000001000000020000000300000004000000050000000600000007000000080000000900000009ffff Done. ****Extract Before ***** But in this case also, it used to reset... I hope, this what is expected in the Successful Output of Ramtest. Any pointers on this one. Regards Deepak

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Status freebios2...
by ebiederman＠lnxi.com 09 May '03

09 May '03

I am busily working on getting the switching from fallback to normal mode working in LinuxBIOS. To that end I have just implemented and committed structure and typedef support in LinuxBIOS. I realized the other day that to remove assembly code I would need to be able to call rdmsr && wrmsr from code compiled with romcc. rdmsr returns 2 values so I needed structure support. And typedef support was simple to implement and so I fixed it while I was in there. Hopefully I can now make some more progress. Eric

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Re: Flashing Bios Success...
by Nathanael Noblet 08 May '03

08 May '03

On Wednesday, May 7, 2003, at 03:06 PM, ron minnich wrote: > what is your southbridge part? can you look at the part directly? So I have the datasheet for the 5595 now (found using google so not sure whether I should send it to you) um either way to enable flash they talk about using the "address and data port, i.e. Port 70h and 71h, respectively. The access control with which the three portions of registers can be appropriately addressed are stored in PCI-ISA: 45h[3] (EXTEND_EN bit) and PCI-ISA: 45h[1](APCREG_EN bit)." but in the sis530 docs I get this for registers 70h: "Register 70h to register 76h define the attribute of the Shadow RAM from 640 KBytes to 1 MBytes. All of the registers 70h to 75h are defined as below, and each register defines the corresponding memory segment's attribute which are listed in the following table. REGISTER DEFINED RANGE REGISTER DEFINED RANGE Register 70h bits 7:5 0C0000h-0C3FFFh Register 73h bits 7:5 0D8000h-0DBFFFh" so I'm not sure how to set that in the 5595..? There must be some way through the pci bridge I think, but don't really know what I'm doing... so some pointers (or even pointers to some docs on how things work) would be great. Register 45h (on the 5595) controls the flash writability. But on the sis530 45h is "IDE Secondary Channel/Master Drive Data Active Time Control" so again it is a matter of knowing how to communicate with the 5595 instead of the main chipset. Now this is all great and what not, but I'm confused. We're having problems detecting the flash, not writing to it. So I'm not sure how this will help. As well in the flash_rom sources the enable_sis is never called. In going over the sources to devbios and the flash_rom, I realize that I don't know anything much about the pci/isa bridges and such... So basically I'm wondering what the next step is. 1) Does the write enable bit help with detecting? 2) Where do I get docs about how the pci & isa communication happens? 2a) do I need those docs? that's about it... -- Nathanael Noblet Gnat Solutions 4604 Monterey Ave NW Calgary, AB T3B 5K4 T/F 403.288.5360 C 403.809.5368 http://www.gnat.ca/

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Re: My Linux bios FAQ/HOWTO preAlpha
by Richard Smith 08 May '03

08 May '03

McMechan, James W CIV wrote: >>yes, somebody had it and was going to fill it out with more info >>but I have not heard from them. >> >>I'll try to get it to you today. > > That would be me. I was still going over the faq. > Alas I am slow... > The source to the FAQ appears to be the web page's html. Ok.. Well let me know when are ready to add in my stuff. I've added a few more items since my last post. On a sidenote... I've learned that OpenOffice 1.1beta can do DocBook stuff. I'd like to move my text document over to something like that so that you can autogenerate various formats. I pulled down OO1.1b but so far haven't been able to get the DocBook stuff enabled. (You have to go edit some XML config files and I don't seem to have done it correctly). As soon as I can get that setup I'll port my stuff over and attempt to do someting better with the format. And generate it into html,pdf,text, etc. Until then I'm not worrying about formatting. -- Richard A. Smith rsmith(a)bitworks.com

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Re: My Linux bios FAQ/HOWTO preAlpha
by McMechan, James W CIV 08 May '03

08 May '03

>> I also need to merge it with the current FAQ. Ron is that available in >> text form? > > yes, somebody had it and was going to fill it out with more info > but I have not heard from them. > > I'll try to get it to you today. That would be me. I was still going over the faq. Alas I am slow... The source to the FAQ appears to be the web page's html.

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Re: jmp INSTRUCTION IN boot.c fails and resets again , what couldbethe reason.
by Mark Wilkinson 08 May '03

08 May '03

Hi All, I think a bug has been introduced somewhere in the Via vt8601 ram initialisation which is causing this symptom. I have a VIA Epia 5000 mainboard with 128M ram, and using a fresh checkout from the CVS (when sourceforge finally let me :-) I built a fresh romimage. While this linuxbios image correctly reported 127M of ram (I assume that 1M grabbed by the vga chip) I kept seeing the fail, reset problem, where linuxbios would reset before getting a chance to jump to the loaded elf image. After commenting out the bit in the northbridge sizeram routine which sets the correct memory size, and just let it return the good old 64M, not only does the Image boot and load correctly, but memtest86 (v2.9) loaded and started running. Does this give anyone any ideas as to the problem ? Regards, Mark.

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Re: Flashing Bios Success...
by Nathanael Noblet 08 May '03

08 May '03

On Thursday, May 8, 2003, at 01:04 PM, ron minnich wrote: > On 8 May 2003, Nathanael D. Noblet wrote: > >> 00:01.0 ISA bridge: Silicon Integrated Systems [SiS] 85C503/5513 (rev >> b3) >> 00: 39 10 08 00 0f 00 00 02 b3 00 01 06 00 00 80 00 >> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 40: c8 80 80 80 80 60 00 02 ff ff 10 0f 11 20 04 01 >> 50: 11 28 02 01 62 00 66 00 9c 2e 12 00 0c e9 00 00 >> 60: 0c 80 7f 00 34 01 00 00 90 02 80 00 20 1d 00 00 >> 70: 1e 00 00 80 80 08 00 00 00 00 00 80 00 00 80 00 >> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 90: 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > this is the south bridge. This is the "function" (sub-device) of the > southbridge that controls flash write. > > reg 0x45 has a value of: > 0x60, binary 0110 0000 > to make eeprom flashable, bits 5,2 must == 01. see page 76 of the book. > > bit 5 is 1 and bit 2 is 0, which I think is 10. We need to flip them. > > 0100 0100 > > 4 4 > > Try this > setpci -s 0:1.0 45.b (read the value) > setpci -s 0:1.0 45.b=44 > setpci -s 0:1.0 45.b (read the value back and make sure it is 44) > > then run flash_rom and see what happens. EEPROM Found! nice! So now I'll try getting good old linuxbios on there... Seriously thanks alot... Is there anything I need to do to flash_rom.c to get that to work all the time? having someone explain what the -xxx output is sure helps understand what it is (besides knowing it is a hex dump)... -- Nathanael Noblet Gnat Solutions 4604 Monterey Ave NW Calgary, AB T3B 5K4 T/F 403.288.5360 C 403.809.5368 http://www.gnat.ca/

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Re: tusl2-c
by Yap Ee Huey 08 May '03

08 May '03

Hi ron, Do you think my memory initialization failed ? RAMTEST is reporting "too many errors" so I disabled it . But how does the PCI codes run if my memory is not brought up ? Or do you mean the MTRR part only ? thx, regards, eehuey >From: ron minnich <rminnich(a)lanl.gov> >To: Yap Ee Huey <yapeehuey(a)hotmail.com> >CC: linuxbios(a)clustermatic.org >Subject: Re: tusl2-c >Date: Wed, 7 May 2003 08:38:14 -0600 (MDT) > >It looks like a bad memory configuration to me. > >ron > _________________________________________________________________ Download ringtones, logos and picture messages from MSN Malaysia http://www.msn.com.my/mobile/ringtones/default.asp

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Re: jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by dkotian3＠vsnl.net 08 May '03

08 May '03

Thanks very much for sharing your experience. I have LinuxBIOS option with my etherboot payload. Actually, I see a similar issue with my ADLO payload as well. Must be something else. Regards Deepak stepan(a)suse.de wrote * Deepak Kotian <dkotian3(a)vsnl.net> [030507 20:55]: > after putting some debug statements, it seems the LinuxBIOS resets > after the jmp instruction is boot.c ( " jmp *%%eax\n\t" in jmp_to_elf_entry) > fails. > I am using ETHERBOOT payload with IDE support. Is it because the ram > initialization is not proper or something, has anyone experienced this kind > of problem. > > Any pointers, why it should fail over here. > > Clearing Segment: addr: 0x00000000000978d4 memsz: 0x0000000000004854 > Jumping to boot code at 0x94000 > > LinuxBIOS-1.0.0 Thu May 1 04:29:36 IST 2003 starting... > Ram1 I had the same thing after updating from etherbot 5.1.7 to 5.1.8 when I forgot to change the config file to build for LinuxBIOS instead of PC bios. I assume etherboot tries to call some intXX services early in that case which might cause the reboot. Did not investigate further after it worked though Best regards, Stefan Reinauer -- The use of COBOL cripples the mind; its teaching should, therefore, be regarded as a criminal offense. -- E. W. Dijkstra _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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coreboot May 2003