Hi everybody,
I prepared an initial set of patches to support the HP DL145 G3 server, which is a Broadcom HT-1000/HT-2100 based Socket F machine.
The current status of the port is:
* we have serial output (using the serverengines pilot chip on the board, see attached pilot_superio.patch) * CPU and memory gets initialized * on-board eth0 is working * SATA is working * the on-board graphic was not tested (not important for a server and the graphics sucks anyway...) * USB and PS2 work * no ACPI * I remember that I could also use a PCIe card, see attached bcm21000.patch * HTX card does work. * Earlier problems we had in respect to timer interrupt are not there anymore. * the hp_dl145_g3.patch includes the mainboard and the target dirs
BUT: * if I coldboot, the CPUs are only running at 1 GHz and not with 2.6 GHz as they should... * if we boot the factory BIOS and then perform a warm-reset into Coreboot, the CPUs run with 2.6 GHz.
I hope someone on the list can help.
* There are also some more problems with the HT-1000 (aka bcm5785) southbridge: - if I activate IDE in bcm5785_early_setup.c, the machine will freeze shortly after being completely booted - if I activate the second IOAPIC (line 179 in bcm5785_early_setup.c), my linux boot hangs when starting udevd... - with both features disabled (see attached bcm5785_noide.patch), the machine boots and does not crash, of course PATA drives are not available.
To boot the machine, I tested FILO. The on-board SATA adapter uses a class id of 0x104 in sata mode (which we use). FILO does not accept this class ID; I prepared a patch that adds this class ID to the respective if statement in driver/ide.c. FILO does then boot from SATA without any problems (see attached filo_dl145_sata.patch).
I hope this gets you started Samuel, and I hope the list can provide some insight regarding the CPU frequency problem.
Regards, Mondrian
I just tried building this :)
But I didn't succeed. What I did: 1. checkout payload filo, apply filo_dl_145_sata.patch and build it. svn co svn://coreboot.org/filo cd filo/trunk/filo patch -p 0 << ~/coreboot/filo_dl_145_sata.patch sh build.sh cp build/filo.elf ~/coreboot/
2. checkout coreboot-v2, apply remaining patches and build it: svn co svn://coreboot.org/repos/trunk/coreboot-v2 cd coreboot-v2 patch -p 0 << ~/coreboot/bcm2100.patch patch -p 0 << ~/coreboot/pilot_superio.patch patch -p 0 << ~/coreboot/hp_dl145_g3.patch patch -p 0 << ~/bcm5785_noide.patch cd targets buildtarget hp/dl145_g3 /home/samuel/coreboot/coreboot_v2 cd hp/dl145_g3 sed -e s@/home/mondrian/filo.elf@/home/samuel/coreboot/filo.elf@g Config.lb cd dl145_g3 make
and then i get the error: http://merlin.ugent.be/~samuel/dl145g3/builds/firmware_build_20090331_1708.t...
Any suggesions? Did I do something wrong?
2009/3/31 Mondrian Nuessle nuessle@uni-hd.de:
Hi everybody,
I prepared an initial set of patches to support the HP DL145 G3 server, which is a Broadcom HT-1000/HT-2100 based Socket F machine.
The current status of the port is:
- we have serial output (using the serverengines pilot chip on the board, see attached pilot_superio.patch)
- CPU and memory gets initialized
- on-board eth0 is working
- SATA is working
- the on-board graphic was not tested (not important for
a server and the graphics sucks anyway...)
- USB and PS2 work
- no ACPI
- I remember that I could also use a PCIe card, see attached bcm21000.patch
- HTX card does work.
- Earlier problems we had in respect to timer interrupt are not there anymore.
- the hp_dl145_g3.patch includes the mainboard and the target dirs
BUT:
- if I coldboot, the CPUs are only running at 1 GHz and not with 2.6 GHz as they should...
- if we boot the factory BIOS and then perform a warm-reset into Coreboot, the CPUs run with 2.6 GHz.
I hope someone on the list can help.
- There are also some more problems with the HT-1000 (aka bcm5785) southbridge:
- if I activate IDE in bcm5785_early_setup.c, the machine will freeze shortly after being completely booted - if I activate the second IOAPIC (line 179 in bcm5785_early_setup.c), my linux boot hangs when starting udevd... - with both features disabled (see attached bcm5785_noide.patch), the machine boots and does not crash, of course PATA drives are not available.
To boot the machine, I tested FILO. The on-board SATA adapter uses a class id of 0x104 in sata mode (which we use). FILO does not accept this class ID; I prepared a patch that adds this class ID to the respective if statement in driver/ide.c. FILO does then boot from SATA without any problems (see attached filo_dl145_sata.patch).
I hope this gets you started Samuel, and I hope the list can provide some insight regarding the CPU frequency problem.
Regards, Mondrian
-- Dr. Mondrian Nuessle Phone: +49 621 181 2717 University of Heidelberg Fax: +49 621 181 2713 Computer Architecture Group mailto:nuessle@uni-hd.de http://ra.ziti.uni-heidelberg.de
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On Tue, Mar 31, 2009 at 10:40 AM, samuel samuel.verstraete@gmail.com wrote:
I just tried building this :)
But I didn't succeed. What I did:
- checkout payload filo, apply filo_dl_145_sata.patch and build it.
svn co svn://coreboot.org/filo cd filo/trunk/filo patch -p 0 << ~/coreboot/filo_dl_145_sata.patch sh build.sh cp build/filo.elf ~/coreboot/
- checkout coreboot-v2, apply remaining patches and build it:
svn co svn://coreboot.org/repos/trunk/coreboot-v2 cd coreboot-v2 patch -p 0 << ~/coreboot/bcm2100.patch patch -p 0 << ~/coreboot/pilot_superio.patch patch -p 0 << ~/coreboot/hp_dl145_g3.patch patch -p 0 << ~/bcm5785_noide.patch cd targets buildtarget hp/dl145_g3 /home/samuel/coreboot/coreboot_v2 cd hp/dl145_g3 sed -e s@/home/mondrian/filo.elf@/home/samuel/coreboot/filo.elf@g Config.lb cd dl145_g3 make
and then i get the error:
cp coreboot_ram.nrv2b coreboot_ram.rom echo '/*ldoptions*/' > ldscript.ld; cat ldoptions >> ldscript.ld ; for file in /home/samuel/coreboot/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb /home/samuel/coreboot/coreboot-v2/src//cpu/x86/16bit/entry16.lds /home/samuel/coreboot/coreboot-v2/src//cpu/x86/16bit/reset16.lds /home/samuel/coreboot/coreboot-v2/src//arch/i386/lib/id.lds /home/samuel/coreboot/coreboot-v2/src//arch/i386/lib/failover.lds ; do echo /* $file */ >> ldscript.ld; cat $file >> ldscript.ld ; done gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld crt0.o /usr/bin/ld: coreboot: section `.id' can't be allocated in segment 2 /usr/bin/ld: final link failed: Bad value collect2: ld returned 1 exit status
Any suggesions? Did I do something wrong?
Try a different version of binutils and/or gcc. I used to get this error on Fedora Core 8.
Thanks, Myles
On Tue, Mar 31, 2009 at 6:56 PM, Myles Watson mylesgw@gmail.com wrote:
On Tue, Mar 31, 2009 at 10:40 AM, samuel samuel.verstraete@gmail.com wrote:
I just tried building this :)
But I didn't succeed. What I did:
- checkout payload filo, apply filo_dl_145_sata.patch and build it.
svn co svn://coreboot.org/filo cd filo/trunk/filo patch -p 0 << ~/coreboot/filo_dl_145_sata.patch sh build.sh cp build/filo.elf ~/coreboot/
- checkout coreboot-v2, apply remaining patches and build it:
svn co svn://coreboot.org/repos/trunk/coreboot-v2 cd coreboot-v2 patch -p 0 << ~/coreboot/bcm2100.patch patch -p 0 << ~/coreboot/pilot_superio.patch patch -p 0 << ~/coreboot/hp_dl145_g3.patch patch -p 0 << ~/bcm5785_noide.patch cd targets buildtarget hp/dl145_g3 /home/samuel/coreboot/coreboot_v2 cd hp/dl145_g3 sed -e s@/home/mondrian/filo.elf@/home/samuel/coreboot/filo.elf@g Config.lb cd dl145_g3 make
and then i get the error:
cp coreboot_ram.nrv2b coreboot_ram.rom echo '/*ldoptions*/' > ldscript.ld; cat ldoptions >> ldscript.ld ; for file in /home/samuel/coreboot/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb /home/samuel/coreboot/coreboot-v2/src//cpu/x86/16bit/entry16.lds /home/samuel/coreboot/coreboot-v2/src//cpu/x86/16bit/reset16.lds /home/samuel/coreboot/coreboot-v2/src//arch/i386/lib/id.lds /home/samuel/coreboot/coreboot-v2/src//arch/i386/lib/failover.lds ; do echo /* $file */ >> ldscript.ld; cat $file >> ldscript.ld ; done gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld crt0.o /usr/bin/ld: coreboot: section `.id' can't be allocated in segment 2 /usr/bin/ld: final link failed: Bad value collect2: ld returned 1 exit status
Any suggesions? Did I do something wrong?
Try a different version of binutils and/or gcc. I used to get this error on Fedora Core 8.
samuel@camelot ~ $ lvu version binutils 2.18 samuel@camelot ~ $ lvu version gcc 4.2.4
You suggest downgrading or upgrading? :)
Thanks, Myles
On Tue, Mar 31, 2009 at 10:59 AM, samuel samuel.verstraete@gmail.com wrote:
On Tue, Mar 31, 2009 at 6:56 PM, Myles Watson mylesgw@gmail.com wrote:
On Tue, Mar 31, 2009 at 10:40 AM, samuel samuel.verstraete@gmail.com wrote:
I just tried building this :)
But I didn't succeed. What I did:
- checkout payload filo, apply filo_dl_145_sata.patch and build it.
svn co svn://coreboot.org/filo cd filo/trunk/filo patch -p 0 << ~/coreboot/filo_dl_145_sata.patch sh build.sh cp build/filo.elf ~/coreboot/
- checkout coreboot-v2, apply remaining patches and build it:
svn co svn://coreboot.org/repos/trunk/coreboot-v2 cd coreboot-v2 patch -p 0 << ~/coreboot/bcm2100.patch patch -p 0 << ~/coreboot/pilot_superio.patch patch -p 0 << ~/coreboot/hp_dl145_g3.patch patch -p 0 << ~/bcm5785_noide.patch cd targets buildtarget hp/dl145_g3 /home/samuel/coreboot/coreboot_v2 cd hp/dl145_g3 sed -e s@/home/mondrian/filo.elf@/home/samuel/coreboot/filo.elf@g Config.lb cd dl145_g3 make
and then i get the error:
cp coreboot_ram.nrv2b coreboot_ram.rom echo '/*ldoptions*/' > ldscript.ld; cat ldoptions >> ldscript.ld ; for file in /home/samuel/coreboot/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb /home/samuel/coreboot/coreboot-v2/src//cpu/x86/16bit/entry16.lds /home/samuel/coreboot/coreboot-v2/src//cpu/x86/16bit/reset16.lds /home/samuel/coreboot/coreboot-v2/src//arch/i386/lib/id.lds /home/samuel/coreboot/coreboot-v2/src//arch/i386/lib/failover.lds ; do echo /* $file */ >> ldscript.ld; cat $file >> ldscript.ld ; done gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld crt0.o /usr/bin/ld: coreboot: section `.id' can't be allocated in segment 2 /usr/bin/ld: final link failed: Bad value collect2: ld returned 1 exit status
Any suggesions? Did I do something wrong?
Try a different version of binutils and/or gcc. I used to get this error on Fedora Core 8.
samuel@camelot ~ $ lvu version binutils 2.18 samuel@camelot ~ $ lvu version gcc 4.2.4
You suggest downgrading or upgrading? :)
I wish I knew. With Fedora I couldn't do either. I just had to switch distros. Interestingly, it only affected my 32-bit machine; 64-bit was fine.
Now I use:
gcc (Ubuntu 4.3.2-1ubuntu12) 4.3.2 GNU assembler (GNU Binutils for Ubuntu) 2.18.93.20081009
I know there are others that work too.
Thanks, Myles
On 31.03.2009 16:01 Uhr, Mondrian Nuessle wrote:
I prepared an initial set of patches to support the HP DL145 G3 server, which is a Broadcom HT-1000/HT-2100 based Socket F machine.
- I remember that I could also use a PCIe card, see attached bcm21000.patch
Hi Mondrian,
thank you very much for your patch. Do you happen to know if the component's name is HT2100 or HT21000? Just to make sure we have it in the repository correctly.
Stefan
On Tue, Mar 31, 2009 at 12:56 PM, Stefan Reinauer stepan@coresystems.de wrote:
thank you very much for your patch. Do you happen to know if the component's name is HT2100 or HT21000? Just to make sure we have it in the repository correctly.
The naming in the patch looks right. Broadcom refers to it as HT-2100 on their website:
http://www.broadcom.com/products/Small-Medium-Business/SystemI-O-Products/HT...
and as both HT-2100 and BCM21000 in the datasheet (often as "BCM21000 (HT-2100)" ).
thank you very much for your patch. Do you happen to know if the component's name is HT2100 or HT21000? Just to make sure we have it in the repository correctly.
The naming in the patch looks right. Broadcom refers to it as HT-2100 and as both HT-2100 and BCM21000 in the datasheet (often as "BCM21000 (HT-2100)" ).
that's my understanding, too.
OK,
I managed booting the firmware... I never worked with serial ports and stuff so this took me a while to grab the idea...
Anyway, you can find the boot.log on http://merlin.ugent.be/~samuel/dl145g3/boot.log
Obviously that boot line is wrong. http://merlin.ugent.be/~samuel/dl145g3/filo_config obviously CONFIG_MENULST_FILE="hda3:/boot/filo/menu.lst" is wrong. My kernel I'd like to boot is hda1:/2.6.28.8_x86-64
Trying to boot this as follows:
kernel hda1:/2.6.28.8_x86_64
results in:
Drive 0 does not exist Error 15: File not found.
I'm a bit stuck I'm afraid, afaik i did patch filo with the patch from mondrian so prolly me config of filo is wrong?
Kind regards,
Samuel
ok... Fixed that too :)
used the following bootline: kernel hda1:/2.6.28.8-x86_64 root=/dev/md1 console=tty0 console=ttyS0,115200
and that worked like a charm... Logged in with ssh and it works :D Even kvm was just working: from dmesg: loaded kvm module (kvm-84)
just wonderfull
So now on to the "issue list" 1. Cpu's are indeed running at 1Ghz. Running cpufreq-info says: no or unknown cpufreq driver is active on this CPU
2. not all that important but some vga output would be convenient.. .right now it's doing nothing...
Anyway i need to thank everyone already for helping me gettng this far :) I hope to get the procs running at full speed and then we can start virtualzing machine :D
Kind regards,
Samuel
So now on to the "issue list"
- Cpu's are indeed running at 1Ghz. Running cpufreq-info says: no or
unknown cpufreq driver is active on this CPU
#define K8_SET_FIDVID 0 needs to be a 1 for full speed but there might need to be some tweaking in cache_as_ram.c where it is used. Compare it with a known working mainboard.
Marc
On Thu, Apr 2, 2009 at 8:54 PM, Marc Jones marcj303@gmail.com wrote:
So now on to the "issue list"
- Cpu's are indeed running at 1Ghz. Running cpufreq-info says: no or
unknown cpufreq driver is active on this CPU
#define K8_SET_FIDVID 0 needs to be a 1 for full speed but there might need to be some tweaking in cache_as_ram.c where it is used. Compare it with a known working mainboard.
That indeed did the trick. It's running at 2.6Ghz now :)
Marc
Anyone has any hints on how to get the vga port going?
and another thing... I'm trying to get filo/grub to autoload my config file i made... i stored it on /dev/sda1 (together with the kernel) but it is not loading that file... it simply goes straight to the prompt. No error nothing...
the config i made looks like this: # timeout 10 default 0 fallback 1
title 2.6.28.8-x86_64 kernel /dev/sda1/2.6.28.8-x86_64 root=/dev/md1 console=tty0 console=ttyS0,115200 #
any ideas?
On Thu, Apr 2, 2009 at 2:45 PM, samuel samuel.verstraete@gmail.com wrote:
Anyone has any hints on how to get the vga port going?
I don't see it getting initialized. I don't see a line where the ROM is being run in your log.
Have you tried extracting the VGA BIOS?
Do you have a vga card to try?
and another thing... I'm trying to get filo/grub to autoload my config file i made... i stored it on /dev/sda1 (together with the kernel) but it is not loading that file... it simply goes straight to the prompt. No error nothing...
the config i made looks like this: # timeout 10 default 0 fallback 1
title 2.6.28.8-x86_64 kernel /dev/sda1/2.6.28.8-x86_64 root=/dev/md1 console=tty0 console=ttyS0,115200
/dev/sda1 looks wrong here. Have you tried hda1 (like your working boot line)?
Myles
On Thu, Apr 2, 2009 at 11:00 PM, Myles Watson mylesgw@gmail.com wrote:
On Thu, Apr 2, 2009 at 2:45 PM, samuel samuel.verstraete@gmail.com wrote:
Anyone has any hints on how to get the vga port going?
I don't see it getting initialized. I don't see a line where the ROM is being run in your log.
Have you tried extracting the VGA BIOS?
Do you have a vga card to try?
I will try that
and another thing... I'm trying to get filo/grub to autoload my config file i made... i stored it on /dev/sda1 (together with the kernel) but it is not loading that file... it simply goes straight to the prompt. No error nothing...
the config i made looks like this: # timeout 10 default 0 fallback 1
title 2.6.28.8-x86_64 kernel /dev/sda1/2.6.28.8-x86_64 root=/dev/md1 console=tty0 console=ttyS0,115200
/dev/sda1 looks wrong here. Have you tried hda1 (like your working boot line)?
But shouldn't it at least show the menu? Even if the entry is completely wrong?
Myles
Hi,
Status of dl145g3: * 2 Opteron 2218HE's working in the machine. No problem * both cpu's got 4GB of ram, NUMA is working :) * booting with filo works * converted the patches of Mondrian to the last revision of coreboot. (original patches are on trac, issue 127) * src/mainboard/hp/dl145g3/Config.lb: http://merlin.ugent.be/~samuel/dl145g3/config/srcConfig.lb * src/mainboard/hp/dl145g3/Options.lb: http://merlin.ugent.be/~samuel/dl145g3/config/srcOptions.lb * targets/hp/dl145g3/Config.lb: http://merlin.ugent.be/~samuel/dl145g3/config/Config.lb * Contacted Anton Borisov to extract the VGA rom of the orginal HP bios: http://merlin.ugent.be/~samuel/dl145g3/OPROM.00.rom
2 concerns: 1. CPU0 gets very hot during idling. Not really sure what is going on there. Does the code take into account that this is actually a HE (low power opteron)? or is that ignored? How can i check that the voltage applied by coreboot is correct? Maybe it's ok.. I just want a confirmation on this. 2. VGA output is still not working. I have tried both YABEL and X86BIOS to load the vga rom but i get errors... X86BIOS: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootx86bios.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes entering emulator int1a vector at 274af
YABEL: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootYABEL.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes pci_cfg_read(): Config read access invalid device! bus: 00 (00), devfn: 00 (20), offs: 00
I've also tried with a seperate VGA card on the pci-e slot on the machine but that doesn't seem to work either.
As no one on IRC seems to be able to help out with this I'd like to hear from you :)
Cheers,
Samuel
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of samuel Sent: Wednesday, April 22, 2009 6:00 AM To: coreboot@coreboot.org Cc: Anton Borisov; Mondrian Nuessle Subject: Re: [coreboot] [PATCH] First support for HP DL145 G3
Hi,
Status of dl145g3:
- 2 Opteron 2218HE's working in the machine. No problem
- both cpu's got 4GB of ram, NUMA is working :)
- booting with filo works
- converted the patches of Mondrian to the last revision of coreboot.
(original patches are on trac, issue 127)
- src/mainboard/hp/dl145g3/Config.lb:
http://merlin.ugent.be/~samuel/dl145g3/config/srcConfig.lb
- src/mainboard/hp/dl145g3/Options.lb:
http://merlin.ugent.be/~samuel/dl145g3/config/srcOptions.lb
- targets/hp/dl145g3/Config.lb:
http://merlin.ugent.be/~samuel/dl145g3/config/Config.lb
- Contacted Anton Borisov to extract the VGA rom of the orginal HP
bios: http://merlin.ugent.be/~samuel/dl145g3/OPROM.00.rom
2 concerns:
- CPU0 gets very hot during idling. Not really sure what is going on
there. Does the code take into account that this is actually a HE (low power opteron)? or is that ignored? How can i check that the voltage applied by coreboot is correct? Maybe it's ok.. I just want a confirmation on this. 2. VGA output is still not working. I have tried both YABEL and X86BIOS to load the vga rom but i get errors... X86BIOS: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootx86bios.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes entering emulator int1a vector at 274af
YABEL: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootYABEL.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes pci_cfg_read(): Config read access invalid device! bus: 00 (00), devfn: 00 (20), offs: 00
I've also tried with a seperate VGA card on the pci-e slot on the machine but that doesn't seem to work either.
Have you tried SeaBIOS for your payload? It runs the option ROMS directly instead of emulating them. As an added bonus it will use your original grub installation.
If SeaBIOS doesn't work for the onboard graphics or the VGA card, send the logs.
Thanks, Myles
Have you tried SeaBIOS for your payload? It runs the option ROMS directly instead of emulating them. As an added bonus it will use your original grub installation.
I have considered this but didn't test it yet as filo also had a patch to support the dl145g3, and i'm unsure if i need to port that patch to seabios as well: http://www.coreboot.org/pipermail/coreboot/attachments/20090331/9e221f84/att...
If SeaBIOS doesn't work for the onboard graphics or the VGA card, send the logs.
Thanks, Myles
On Wed, Apr 22, 2009 at 6:00 AM, samuel samuel.verstraete@gmail.com wrote:
Hi,
Status of dl145g3:
- 2 Opteron 2218HE's working in the machine. No problem
- both cpu's got 4GB of ram, NUMA is working :)
- booting with filo works
- converted the patches of Mondrian to the last revision of coreboot.
(original patches are on trac, issue 127) * src/mainboard/hp/dl145g3/Config.lb: http://merlin.ugent.be/~samuel/dl145g3/config/srcConfig.lb * src/mainboard/hp/dl145g3/Options.lb: http://merlin.ugent.be/~samuel/dl145g3/config/srcOptions.lb * targets/hp/dl145g3/Config.lb: http://merlin.ugent.be/~samuel/dl145g3/config/Config.lb
- Contacted Anton Borisov to extract the VGA rom of the orginal HP
bios: http://merlin.ugent.be/~samuel/dl145g3/OPROM.00.rom
2 concerns:
- CPU0 gets very hot during idling. Not really sure what is going on
there. Does the code take into account that this is actually a HE (low power opteron)? or is that ignored? How can i check that the voltage applied by coreboot is correct? Maybe it's ok.. I just want a confirmation on this. 2. VGA output is still not working. I have tried both YABEL and X86BIOS to load the vga rom but i get errors... X86BIOS: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootx86bios.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes entering emulator int1a vector at 274af
YABEL: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootYABEL.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes pci_cfg_read(): Config read access invalid device! bus: 00 (00), devfn: 00 (20), offs: 00
device pci 2.2 on end # USB # when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,), device pci 4.0 on end # VGA /* REMOVE THIS ONE */
chip drivers/pci/onboard # it is in bcm5785_0 bus, but the device id can # not be changed even unitid is changed, fake one # to get the rom_address # if HT_CHAIN_END_UNITID_BASE=0, it is 4, # if HT_CHAIN_END_UNITID_BASE=1, it is 3 device pci 4.0 on end register "rom_address" = "0xfff00000" end
This is probably not _the_ problem, but it is a problem. Could you remove the first reference to the VGA. I think the correct one is getting disabled.
Thanks, Myles
devfn: 00 (20), offs: 00
device pci 2.2 on end # USB # when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,), device pci 4.0 on end # VGA /* REMOVE THIS ONE */
chip drivers/pci/onboard # it is in bcm5785_0 bus, but the device id can # not be changed even unitid is changed, fake one # to get the rom_address # if HT_CHAIN_END_UNITID_BASE=0, it is 4, # if HT_CHAIN_END_UNITID_BASE=1, it is 3 device pci 4.0 on end register "rom_address" = "0xfff00000" end
This is probably not _the_ problem, but it is a problem. Could you remove the first reference to the VGA. I think the correct one is getting disabled.
removed it and it didn't make a difference :) so at least it was not needed The error remains the same though
On Wed, Apr 22, 2009 at 8:00 AM, samuel samuel.verstraete@gmail.com wrote:
- VGA output is still not working. I have tried both YABEL and
X86BIOS to load the vga rom but i get errors... X86BIOS: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootx86bios.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes entering emulator int1a vector at 274af
YABEL: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootYABEL.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes pci_cfg_read(): Config read access invalid device! bus: 00 (00), devfn: 00 (20), offs: 00
I only see two "int 1a"s in the ROM binary:
seg000:77DC B8 02 B1 mov ax, 0B102h seg000:77DF B9 41 15 mov cx, 1541h seg000:77E2 BA B9 10 mov dx, 10B9h seg000:77E5 BE 00 00 mov si, 0 seg000:77E8 CD 1A int 1Ah ... seg000:7801 B8 02 B1 mov ax, 0B102h seg000:7804 B9 43 52 mov cx, 5243h seg000:7807 BA B9 10 mov dx, 10B9h seg000:780A BE 00 00 mov si, 0 seg000:780D CD 1A int 1Ah
so it is searching for the 0th instance of ven/dev 10b9:1541 or 10b9:5243: http://www.ctyme.com/intr/rb-2372.htm
Those are: 10b9 ALi Corporation 1541 M1541 10b9 1541 ALI M1541 Aladdin V/V+ AGP System Controller 5243 M1541 PCI to AGP Controller
which seems kind of weird. Maybe it does some workaround when on a platform with those devices.
Also, is there any tracing you can enable (or just add) in the emulators? (to see more closely where it is failing, there is probably more execution after the int 1a and the config read of 0) I don't know if YABEL's and X86BIOS's messages are warnings or errors.
On Wed, Apr 22, 2009 at 9:29 AM, Tom Sylla tsylla@gmail.com wrote:
On Wed, Apr 22, 2009 at 8:00 AM, samuel samuel.verstraete@gmail.com wrote:
- VGA output is still not working. I have tried both YABEL and
X86BIOS to load the vga rom but i get errors... X86BIOS: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootx86bios.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes entering emulator int1a vector at 274af
YABEL: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootYABEL.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes pci_cfg_read(): Config read access invalid device! bus: 00 (00), devfn: 00 (20), offs: 00
I only see two "int 1a"s in the ROM binary:
seg000:77DC B8 02 B1 mov ax, 0B102h seg000:77DF B9 41 15 mov cx, 1541h seg000:77E2 BA B9 10 mov dx, 10B9h seg000:77E5 BE 00 00 mov si, 0 seg000:77E8 CD 1A int 1Ah ... seg000:7801 B8 02 B1 mov ax, 0B102h seg000:7804 B9 43 52 mov cx, 5243h seg000:7807 BA B9 10 mov dx, 10B9h seg000:780A BE 00 00 mov si, 0 seg000:780D CD 1A int 1Ah
so it is searching for the 0th instance of ven/dev 10b9:1541 or 10b9:5243: http://www.ctyme.com/intr/rb-2372.htm
Those are: 10b9 ALi Corporation 1541 M1541 10b9 1541 ALI M1541 Aladdin V/V+ AGP System Controller 5243 M1541 PCI to AGP Controller
which seems kind of weird. Maybe it does some workaround when on a platform with those devices.
Also, is there any tracing you can enable (or just add) in the emulators? (to see more closely where it is failing, there is probably more execution after the int 1a and the config read of 0) I don't know if YABEL's and X86BIOS's messages are warnings or errors.
It turns out that this was caused by an extra VGA entry in the Config.lb
# when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,), device pci 4.0 on end # VGA /* REMOVE THIS ONE */
chip drivers/pci/onboard # it is in bcm5785_0 bus, but the device id can # not be changed even unitid is changed, fake one # to get the rom_address # if HT_CHAIN_END_UNITID_BASE=0, it is 4, # if HT_CHAIN_END_UNITID_BASE=1, it is 3 device pci 4.0 on end register "rom_address" = "0xfff00000" end
It was trying to initialize the device, but it wasn't correctly connected to the bus. Here's the new failure. Now it looks like it's not finding the ROM anymore.
new log: http://merlin.ugent.be/~samuel/dl145g3/vgarom/coreboot-3.log
Thanks, Myles
On Wed, Apr 22, 2009 at 10:59 AM, Myles Watson mylesgw@gmail.com wrote:
On Wed, Apr 22, 2009 at 9:29 AM, Tom Sylla tsylla@gmail.com wrote:
On Wed, Apr 22, 2009 at 8:00 AM, samuel samuel.verstraete@gmail.com wrote:
- VGA output is still not working. I have tried both YABEL and
X86BIOS to load the vga rom but i get errors... X86BIOS: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootx86bios.log relevant part: On mainboard, rom address for PCI: 00:04.0 = fff00000 copying VGA ROM Image from fff00000 to 0xc0000, 0x8000 bytes entering emulator int1a vector at 274af
from the latest log:
PCI: 00:04.0 init On card, rom address for PCI: 00:04.0 = fda00000 Incorrect Expansion ROM Header Signature 0000
Samuel,
It should still say On mainboard. Could you send the snippet from the Config.lb that you're using?
Thanks, Myles
Am Donnerstag, den 02.04.2009, 19:12 +0200 schrieb samuel:
OK,
I managed booting the firmware... I never worked with serial ports and stuff so this took me a while to grab the idea...
Anyway, you can find the boot.log on http://merlin.ugent.be/~samuel/dl145g3/boot.log
Obviously that boot line is wrong. http://merlin.ugent.be/~samuel/dl145g3/filo_config obviously CONFIG_MENULST_FILE="hda3:/boot/filo/menu.lst" is wrong. My kernel I'd like to boot is hda1:/2.6.28.8_x86-64
Trying to boot this as follows:
kernel hda1:/2.6.28.8_x86_64
results in:
Drive 0 does not exist Error 15: File not found.
I'm a bit stuck I'm afraid, afaik i did patch filo with the patch from mondrian so prolly me config of filo is wrong?
I have never tried it myself. But as far as I know FILO handles config files from GRUB, where is written what options are available for boot. So if you have used GRUB before, you have to point the config to this file.
Thanks,
Paul
2009/3/31 Mondrian Nuessle nuessle@uni-hd.de:
Hi everybody,
I prepared an initial set of patches to support the HP DL145 G3 server, which is a Broadcom HT-1000/HT-2100 based Socket F machine.
Thanks for the patches! Could you add a Signed-off-by: line so I can ack and commit it?
Thanks, Myles
Acked-by: Samuel Verstraete <samuel.verstraete at gmail.com>
2009/3/31 Mondrian Nuessle nuessle@uni-hd.de:
Hi everybody,
I prepared an initial set of patches to support the HP DL145 G3 server, which is a Broadcom HT-1000/HT-2100 based Socket F machine.
The current status of the port is:
- we have serial output (using the serverengines pilot chip on the board, see attached pilot_superio.patch)
- CPU and memory gets initialized
- on-board eth0 is working
- SATA is working
- the on-board graphic was not tested (not important for
a server and the graphics sucks anyway...)
- USB and PS2 work
- no ACPI
- I remember that I could also use a PCIe card, see attached bcm21000.patch
- HTX card does work.
- Earlier problems we had in respect to timer interrupt are not there anymore.
- the hp_dl145_g3.patch includes the mainboard and the target dirs
BUT:
- if I coldboot, the CPUs are only running at 1 GHz and not with 2.6 GHz as they should...
- if we boot the factory BIOS and then perform a warm-reset into Coreboot, the CPUs run with 2.6 GHz.
I hope someone on the list can help.
- There are also some more problems with the HT-1000 (aka bcm5785) southbridge:
- if I activate IDE in bcm5785_early_setup.c, the machine will freeze shortly after being completely booted - if I activate the second IOAPIC (line 179 in bcm5785_early_setup.c), my linux boot hangs when starting udevd... - with both features disabled (see attached bcm5785_noide.patch), the machine boots and does not crash, of course PATA drives are not available.
To boot the machine, I tested FILO. The on-board SATA adapter uses a class id of 0x104 in sata mode (which we use). FILO does not accept this class ID; I prepared a patch that adds this class ID to the respective if statement in driver/ide.c. FILO does then boot from SATA without any problems (see attached filo_dl145_sata.patch).
I hope this gets you started Samuel, and I hope the list can provide some insight regarding the CPU frequency problem.
Regards, Mondrian
-- Dr. Mondrian Nuessle Phone: +49 621 181 2717 University of Heidelberg Fax: +49 621 181 2713 Computer Architecture Group mailto:nuessle@uni-hd.de http://ra.ziti.uni-heidelberg.de
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On Wed, Apr 22, 2009 at 2:22 PM, samuel samuel.verstraete@gmail.com wrote:
Acked-by: Samuel Verstraete <samuel.verstraete at gmail.com>
Rev 4182, 4183, 4184.
I didn't commit the patch that disables IDE since it would affect other boards. It will need to be reworked so that it is board-specific.
Thanks, Myles