This patch adds the target hp/dl145_g3 together with
the appropriate mainboard sources.

Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>

Index: src/mainboard/hp/dl145_g3/Config.lb
===================================================================
--- src/mainboard/hp/dl145_g3/Config.lb	(revision 0)
+++ src/mainboard/hp/dl145_g3/Config.lb	(revision 0)
@@ -0,0 +1,307 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 AMD
+## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
+##
+## Copyright (C) 2007 University of Mannheim
+## Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
+##
+## Copyright (C) 2009 University of Heidelberg
+## Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+       default ROM_SECTION_SIZE   = FALLBACK_SIZE
+       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+       default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+#dir /drivers/si/3114
+
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
+if HAVE_MP_TABLE
+       object mptable.o
+end
+
+if HAVE_PIRQ_TABLE
+       object irq_tables.o
+end
+
+if USE_DCACHE_RAM
+
+       if CONFIG_USE_INIT
+               # compile cache_as_ram.c to auto.o
+               makerule ./cache_as_ram_auto.o
+                       depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+               end
+
+       else
+               #compile cache_as_ram.c to auto.inc
+               makerule ./cache_as_ram_auto.inc
+                       depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+                       action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+                       action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+               end
+
+       end
+end
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+
+if USE_FALLBACK_IMAGE
+       mainboardinit cpu/x86/16bit/entry16.inc
+       ldscript /cpu/x86/16bit/entry16.lds
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+       mainboardinit cpu/x86/16bit/reset16.inc
+       ldscript /cpu/x86/16bit/reset16.lds
+else
+       mainboardinit cpu/x86/32bit/reset32.inc
+       ldscript /cpu/x86/32bit/reset32.lds
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+if USE_DCACHE_RAM
+       ##
+       ## Setup Cache-As-Ram
+       ##
+       mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+       if USE_DCACHE_RAM
+               ldscript /arch/i386/lib/failover.lds
+       end
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+       if CONFIG_USE_INIT
+               initobject cache_as_ram_auto.o
+       else
+               mainboardinit ./cache_as_ram_auto.inc
+       end
+
+end
+
+##
+## Include the secondary Configuration files
+##
+if CONFIG_CHIP_NAME
+       config chip.h
+end
+
+# config for hp/dl145_g3
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8  # northbridge
+			device pci 18.0 on  # devices on link 0
+				chip southbridge/broadcom/bcm21000 # HT2100
+					device pci 0.0 on 
+					end   # bridge to slot PCI-E 4x ??
+					device pci 1.0 on	
+					end
+					device pci 2.0 on 
+					end  # unused
+					device pci 3.0 on  	# bridge to slot PCI-E 16x ??
+					end
+					device pci 4.0 on
+					end  # unused
+					device pci 5.0 on
+						device pci 4.0 on end # BCM5715 NIC
+						device pci 4.1 on end # BCM5715 NIC
+					end
+				end
+                                chip southbridge/broadcom/bcm5785 # HT1000
+					device pci 0.0 on  # HT PXB  0x0036
+						device pci d.0 on end # PCI/PCI-X bridge 0x0104
+						device pci e.0 on end # SATA 0x024a
+					end
+					device pci 1.0 on end # Legacy  pci main  0x0205
+					device pci 1.1 on end # IDE        0x0214
+					device pci 1.2 on     # LPC        0x0234
+						chip superio/nsc/pc87417
+							device  pnp 4e.0 off  # Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 4e.1 off  # Parallel Port
+									io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 4e.2 off # Com 2
+									io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 4e.3 off  # Com 1
+									io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 4e.4 off end # SWC
+							device pnp 4e.5 off end # Mouse
+							device pnp 4e.6 off  # Keyboard
+									io 0x60 = 0x60
+									io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 4e.7 off end # GPIO
+							device pnp 4e.f off end # XBUS
+							device pnp 4e.10 on #RTC
+								io 0x60 = 0x70
+								io 0x62 = 0x72
+							end
+						end # end superio
+					end # end pci 1.2
+					device pci 1.3 off end # WDTimer    0x0238 
+					device pci 1.4 on end # XIOAPIC0   0x0235 
+					device pci 1.5 on end # XIOAPIC1          
+					device pci 1.6 on end # XIOAPIC2          
+					device pci 2.0 on end # USB        0x0223
+					device pci 2.1 on end # USB
+					device pci 2.2 on end # USB
+					# when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,),
+					device pci 3.0 on end # VGA
+
+# 					chip drivers/pci/onboard
+						# it is in bcm5785_0 bus, but the device id can
+						# not be changed even unitid is changed, fake one
+						# to get the rom_address
+						# if HT_CHAIN_END_UNITID_BASE=0, it is 4,
+						# if HT_CHAIN_END_UNITID_BASE=1, it is 3
+# 						device pci 3.0 on end
+# 						register "rom_address" = "0xfff80000"
+# 					end
+					#bx_a013+ start
+					#chip drivers/pci/onboard    #SATA2
+					#       device pci 5.0 on end
+					#       device pci 5.1 on end
+					#       device pci 5.2 on end
+					#       device pci 5.3 on end
+					#end
+					#bx_a013+ end
+				end
+			end
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+      end # amdk8
+
+#  chip northbridge/amd/amdk8  # northbridge
+#		 device pci 19.0 on end	
+#		 device pci 19.0 on end
+#     device pci 19.0 on end
+#		 device pci 19.1 on end
+#		 device pci 19.2 on end
+#		 device pci 19.3 on end
+#	 end # amdk8
+
+   end #pci_domain
+#        chip drivers/generic/debug
+#              device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#       end
+end
+
+
Index: src/mainboard/hp/dl145_g3/mptable.c
===================================================================
--- src/mainboard/hp/dl145_g3/mptable.c	(revision 0)
+++ src/mainboard/hp/dl145_g3/mptable.c	(revision 0)
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
+ *
+ * Copyright (C) 2007 University of Mannheim
+ * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+extern void get_bus_conf(void);
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "HP      ";
+        static const char productid[12] = "TREX        ";
+        struct mp_config_table *mc;
+
+        unsigned char bus_num;
+        int i;
+        struct mb_sysconf_t *m;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+        get_bus_conf();
+        m = sysconf.mb;
+
+/*Bus:         Bus ID  Type*/
+       /* define bus and isa numbers */
+/*        for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
+                smp_write_bus(mc, bus_num, "PCI   ");
+		printk_debug("writing bus %d as PCI...\n",bus_num);
+         }
+	 */
+	         smp_write_bus(mc, 0, "PCI   ");
+         smp_write_bus(mc, 1, "PCI   ");
+         smp_write_bus(mc, 7, "PCI   ");
+         smp_write_bus(mc, 8, "PCI   ");
+							    
+        smp_write_bus(mc,m->bus_isa, "ISA   ");
+	printk_debug("writing %d as ISA...\n",m->bus_isa);
+
+/*I/O APICs:   APIC ID Version State           Address*/
+        { 
+               device_t dev = 0;
+               int i;
+               struct resource *res;
+                for(i=0; i<3; i++) {
+                       dev = dev_find_device(0x1166, 0x0235, dev);
+                        if (dev) {
+                               res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                               if (res) {
+				       printk_debug("APIC %d base address: %x\n",m->apicid_bcm5785[i],  res->base);
+                                       smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
+                                }
+                       }
+               }
+
+       }
+
+	/* IRQ routing as factory BIOS */
+	outb(0x01, 0xc00); outb(0x0A, 0xc01);
+	outb(0x17, 0xc00); outb(0x05, 0xc01);
+/* 	outb(0x2E, 0xc00); outb(0x0B, 0xc01); */
+/* 	outb(0x07, 0xc00); outb(0x07, 0xc01); */
+	outb(0x07, 0xc00); outb(0x0b, 0xc01);
+
+	outb(0x24, 0xc00); outb(0x05, 0xc01);
+	//outb(0x00, 0xc00); outb(0x09, 0xc01);
+	outb(0x02, 0xc00); outb(0x0E, 0xc01);
+
+	// 8259 registers...
+	outb(0xa0, 0x4d0);
+	outb(0x0e, 0x4d1);
+
+        {
+                device_t dev;
+                dev = dev_find_device(0x1166, 0x0205, 0);
+                if(dev) {
+                        uint32_t dword;
+                        dword = pci_read_config32(dev, 0x64);
+                        dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
+                        pci_write_config32(dev, 0x64, dword);
+                }
+		// set GEVENT pins to NO OP
+		outb(0x33, 0xcd6); outb(0x00, 0xcd7);
+		outb(0x34, 0xcd6); outb(0x00, 0xcd7);
+		outb(0x35, 0xcd6); outb(0x00, 0xcd7);
+        }
+
+	// hide XIOAPIC PCI configuration space
+	{
+		device_t dev;
+		dev = dev_find_device(0x1166, 0x205, 0);
+		if (dev) {
+                       uint32_t dword;
+                       dword = pci_read_config32(dev, 0x64);
+                       dword |= (1<<26);
+                       pci_write_config32(dev, 0x64, dword);
+		}
+	}
+
+/*I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_bcm5785[0], 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_bcm5785[0], 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_bcm5785[0], 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_bcm5785[0], 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_bcm5785[0], 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x5, m->apicid_bcm5785[0], 0x5);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_bcm5785[0], 0x6);
+	//SATA
+/* 	printk_debug("MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
+/*         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
+	printk_debug("MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_bcm5785[0], 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x9, m->apicid_bcm5785[0], 0x9);
+	//USB
+	printk_debug("sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
+	
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xb, m->apicid_bcm5785[0], 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_bcm5785[0], 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_bcm5785[0], 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_bcm5785[0], 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_bcm5785[0], 0xf);
+
+	//VGA
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7);
+	
+	//PCIE
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe);
+	
+	//IDE
+//     	outb(0x02, 0xc00); outb(0x0e, 0xc01);
+//	printk_debug("MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
+//      	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
+
+	//onboard Broadcom GbE
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4);
+
+
+ 
+        /* enable int */
+        /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
+        {
+                device_t dev;
+                dev = dev_find_device(0x1166, 0x0205, 0);
+                if(dev) {
+                        uint32_t dword;
+                        dword = pci_read_config32(dev, 0x6c);
+                        dword |= (1<<4); // enable interrupts
+			printk_debug("6ch: %x\n",dword);
+                        pci_write_config32(dev, 0x6c, dword);
+                }
+        }
+
+/*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
+      	printk_debug("m->bus_isa is: %x\n",m->bus_isa);
+      	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
+      	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1);
+      
+	//extended table entries
+	smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
+	smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
+	smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
+	smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
+	smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
+	smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
+      	smp_write_bus_hierarchy(mc, 9, 0x01, 0);
+      	smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
+      	smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
+
+
+       /* Compute the checksums */
+       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+       printk_debug("Wrote the mp table end at: %p - %p\n",
+               mc, smp_next_mpe_entry(mc));
+       return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+       void *v;
+       v = smp_write_floating_table(addr);
+       return (unsigned long)smp_write_config_table(v);
+}
Index: src/mainboard/hp/dl145_g3/irq_tables.c
===================================================================
--- src/mainboard/hp/dl145_g3/irq_tables.c	(revision 0)
+++ src/mainboard/hp/dl145_g3/irq_tables.c	(revision 0)
@@ -0,0 +1,59 @@
+/* This file was generated by getpir.c, do not modify!
+ * (but if you do, please run checkpir on it to verify)
+ *
+ * Contains the IRQ Routing Table dumped directly from your
+ * memory, which BIOS sets up.
+ *
+ * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
+ */
+
+#ifdef GETPIR
+#include "pirq_routing.h"
+#else
+#include <arch/pirq_routing.h>
+#endif
+
+const struct irq_routing_table intel_irq_routing_table = {
+        PIRQ_SIGNATURE,  /* u32 signature */
+        PIRQ_VERSION,    /* u16 version   */
+        32+16*15,        /* There can be total 19 devices on the bus */
+        0x0,            /* Where the interrupt router lies (bus) */
+	(0x2<<3)|0x4,	
+        0,               /* IRQs devoted exclusively to PCI usage */
+        0,               /* Vendor */
+        0,               /* Device */
+        0,               /* Crap (miniport) */
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+        0x2a,            /* u8 checksum. This has to be set to some
+                            value that would give 0 after the sum of all
+                            bytes for this structure (including checksum) */
+        {
+                /* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+                {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Host Bridge
+                {0x00,(0x02<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Broadcom ht1000 legacy southbridge
+                {0x00,(0x03<<3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Broadcom ht1000 usb
+                {0x00,(0x04<<3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// VGA Contr
+                {0x00,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Broadcom ht1000 pci/pci-x bridge
+                {0x01,(0x0e<<3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Broadcom BCM5785 [HT1000] SATA
+                {0x01,(0x0d<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// BCM5785 [HT1000] PCI/PCI-X Bridge
+                //{0x02,(0x01<<3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, 
+                {0x00,(0x06<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Broadcom HT2100 PCI-Express Bridge
+                //{0x03,(0x00<<3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, 
+                {0x00,(0x07<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Broadcom HT2100 PCI-Express Bridge
+                {0x00,(0x08<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Broadcom HT2100 PCI-Express Bridge
+                {0x00,(0x09<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	//	Broadcom HT2100 PCI-Express Bridge
+                //{0x06,(0x00<<3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0},
+                {0x00,(0x0a<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	//	Broadcom HT2100 PCI-Express Bridge
+                //{0x07,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+                {0x08,(0x04<<3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// BCM5715 Gigabit Ethernet 
+                {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},	// Host Bridge
+                //{0x10,(0x01<<3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0},
+		{0x40,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},     // HTX slot
+        }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+        return copy_pirq_routing_table(addr);
+}
+
Index: src/mainboard/hp/dl145_g3/Options.lb
===================================================================
--- src/mainboard/hp/dl145_g3/Options.lb	(revision 0)
+++ src/mainboard/hp/dl145_g3/Options.lb	(revision 0)
@@ -0,0 +1,339 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 AMD
+## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
+##
+## Copyright (C) 2007 University of Mannheim
+## Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for Uni Mannheim
+## Copyright (C) 2009 University of Heidelberg
+## Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_ACPI_TABLES
+uses ACPI_SSDTX_NUM
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses COREBOOT_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses HW_MEM_HOLE_SIZEK
+uses HW_MEM_HOLE_SIZE_AUTO_INC
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses SERIAL_CPU_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses CONFIG_PCI_64BIT_PREF_MEM
+
+uses CONFIG_LB_MEM_TOPK
+
+uses CONFIG_USE_PRINTK_IN_CAR
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=524288
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
+
+#more 1M for pgtbl
+default CONFIG_LB_MEM_TOPK=2048
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=15
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## ACPI tables will be included
+#default HAVE_ACPI_TABLES=1
+## extra SSDT num
+#default ACPI_SSDTX_NUM=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+
+default SERIAL_CPU_INIT=0
+
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x8
+default LIFT_BSP_APIC_ID=1
+
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
+#2G
+#default HW_MEM_HOLE_SIZEK=0x200000
+#1G
+default HW_MEM_HOLE_SIZEK=0x100000
+#512M
+#default HW_MEM_HOLE_SIZEK=0x80000
+
+#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
+#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+#HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x06
+
+#real SB Unit ID, default is 0x20, mean dont touch it at last
+default HT_CHAIN_END_UNITID_BASE=0x01
+
+#make the SB HT chain on bus 0, default is not (0)
+default SB_HT_CHAIN_ON_BUS0=2
+
+#only offset for SB chain?, default is yes(1)
+#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#allow capable device use that above 4G
+#default CONFIG_PCI_64BIT_PREF_MEM=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcc000
+default DCACHE_RAM_SIZE=0x04000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="DL145 G3"
+default MAINBOARD_VENDOR="HP"
+#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default HEAP_SIZE=0x8000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+#enabel printk in CAR by default
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end
Index: src/mainboard/hp/dl145_g3/mb_sysconf.h
===================================================================
--- src/mainboard/hp/dl145_g3/mb_sysconf.h	(revision 0)
+++ src/mainboard/hp/dl145_g3/mb_sysconf.h	(revision 0)
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
+ *
+ * Copyright (C) 2007 University of Mannheim
+ * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+       unsigned char bus_isa;
+       unsigned char bus_bcm5780[7];
+       unsigned char bus_bcm5785_0;
+       unsigned char bus_bcm5785_1;
+       unsigned char bus_bcm5785_1_1;
+       unsigned apicid_bcm5785[3];
+
+       unsigned sbdn2;
+};
+
+#endif
+
Index: src/mainboard/hp/dl145_g3/chip.h
===================================================================
--- src/mainboard/hp/dl145_g3/chip.h	(revision 0)
+++ src/mainboard/hp/dl145_g3/chip.h	(revision 0)
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 University of Mannheim
+ * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+//     int fixup_scsi;
+//     int fixup_vga;
+};
+
Index: src/mainboard/hp/dl145_g3/cmos.layout
===================================================================
--- src/mainboard/hp/dl145_g3/cmos.layout	(revision 0)
+++ src/mainboard/hp/dl145_g3/cmos.layout	(revision 0)
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399         1       e       2        dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432         8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
Index: src/mainboard/hp/dl145_g3/mainboard.c
===================================================================
--- src/mainboard/hp/dl145_g3/mainboard.c	(revision 0)
+++ src/mainboard/hp/dl145_g3/mainboard.c	(revision 0)
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 University of Mannheim
+ * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for Uni of Mannheim.
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_ops = {
+       CHIP_NAME("HP DL145 G3 Mainboard")
+};
+#endif
Index: src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
===================================================================
--- src/mainboard/hp/dl145_g3/cache_as_ram_auto.c	(revision 0)
+++ src/mainboard/hp/dl145_g3/cache_as_ram_auto.c	(revision 0)
@@ -0,0 +1,378 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Tyan
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
+ *
+ * Copyright (C) 2007 University of Mannheim 
+ * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+
+#define K8_ALLOCATE_IO_RANGE 1
+//#define K8_SCAN_PCI_BUS 1
+
+#define QRANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 0
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#define DBGP_DEFAULT 7
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+
+#if USE_FAILOVER_IMAGE==0
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+
+#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#include "superio/serverengines/pilot/pilot_early_serial.c"
+#include "superio/serverengines/pilot/pilot_early_init.c"
+#include "superio/nsc/pc87417/pc87417_early_serial.c"
+
+
+#if USE_FAILOVER_IMAGE==0
+
+#include "cpu/x86/bist.h"
+
+#if CONFIG_USE_INIT == 0
+       #include "lib/memcpy.c"
+#endif
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
+#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
+
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+#define SMBUS_SWITCH1 0x70
+#define SMBUS_SWITCH2 0x72
+        unsigned device = (ctrl->channel0[0]) >> 8;
+        smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
+        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+        return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit_f.c"
+
+#include "sdram/generic_sdram.c"
+
+//#include "resourcemap.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+//first node
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
+//second node
+#define DIMM4 0x54
+#define DIMM5 0x55
+#define DIMM6 0x56
+#define DIMM7 0x57
+
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+
+#include "northbridge/amd/amdk8/early_ht.c"
+
+//#include "ipmi.c"
+
+// static void setup_early_ipmi_serial()
+// { 
+//   unsigned char result;
+//   char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
+//   char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
+//   char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
+//   char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
+//   char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
+// 
+// //  earlydbg(0x0d); 
+//   //set channel access system only
+//  ipmi_request(5,channel_access);
+// //  earlydbg(result); 
+// /*  
+//   //Set serial/modem config
+//   result=ipmi_request(6,serialmodem_conf);
+//   earlydbg(result); 
+//         
+//   //Set serial mux 1
+//   result=ipmi_request(4,serial_mux1);
+//   earlydbg(result); 
+//               
+//   //Set serial mux 2
+//   result=ipmi_request(4,serial_mux2);
+//   earlydbg(result); 
+//                   
+//   //Set serial mux 3
+//   result=ipmi_request(4,serial_mux3);
+//   earlydbg(result);
+// */
+// //  earlydbg(0x0e); 
+// 
+// } 
+
+
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        /* Is this a cpu only reset? Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal()) { // RTC already inited
+                        goto normal_image; //normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+        bcm5785_enable_rom();
+        bcm5785_enable_lpc();
+        //enable RTC
+       pc87417_enable_dev(RTC_DEV);
+
+        /* Is this a deliberate reset by the bios */
+
+        if (bios_reset_detected() && last_boot_normal()) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+#if HAVE_FAILOVER_BOOT==1
+	__asm__ volatile ("jmp __fallback_image"
+		: /* outputs */
+		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+		)
+#endif
+        ;
+
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if HAVE_FAILOVER_BOOT==1
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);
+    #endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+       static const uint16_t spd_addr[] = {
+                       //first node
+                        DIMM0, DIMM2, 0, 0,
+                        DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+                       //second node
+                       DIMM4, DIMM6, 0, 0,
+                       DIMM5, DIMM7, 0, 0,
+#endif
+
+       };
+
+       struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset;
+        unsigned bsp_apicid = 0;
+
+	
+        if (bist == 0) {
+               bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+	
+	pilot_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	
+	//setup_mp_resource_map();
+
+	uart_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+
+	console_init();
+//	setup_early_ipmi_serial();
+	pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
+	print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
+#if MEM_TRAIN_SEQ == 1
+	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+	setup_coherent_ht_domain();
+
+	wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+	// It is said that we should start core1 after all core0 launched
+	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+	 * So here need to make sure last core0 is started, esp for two way system,
+	 * (there may be apic id conflicts in that case)
+	*/
+	start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	/* it will set up chains and store link pair for optimization later */
+	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+	bcm5785_early_setup();
+
+#if K8_SET_FIDVID == 1
+	{
+		msr_t msr;
+		msr=rdmsr(0xc0010042);
+		print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+	}
+	enable_fid_change();
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+	init_fidvid_bsp(bsp_apicid);
+	// show final fid and vid
+	{
+		msr_t msr;
+		msr=rdmsr(0xc0010042);
+		print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+	}
+#endif
+
+	needs_reset = optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+
+	// fidvid change will issue one LDTSTOP and the HT change will be effective too
+	if (needs_reset) {
+		print_info("ht reset -\r\n");
+		soft_reset();
+	}
+
+	allow_all_aps_stop(bsp_apicid);
+
+	//It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	enable_smbus();
+
+	memreset_setup();
+	//do we need apci timer, tsc...., only debug need it for better output
+	/* all ap stopped? */
+//	init_timer(); // Need to use TMICT to synconize FID/VID
+
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+	post_cache_as_ram();
+
+}
+
+#endif
\ No newline at end of file
Index: src/mainboard/hp/dl145_g3/get_bus_conf.c
===================================================================
--- src/mainboard/hp/dl145_g3/get_bus_conf.c	(revision 0)
+++ src/mainboard/hp/dl145_g3/get_bus_conf.c	(revision 0)
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by bxshi <bingxunshi@gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+struct mb_sysconf_t mb_sysconf;
+
+static unsigned pci1234x[] =
+{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+         //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+        0x0000ff0,
+        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0
+};
+static unsigned hcdnx[] =
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+        0x20202020,
+        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+};
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+
+       unsigned apicid_base;
+
+        device_t dev;
+        int i;
+       struct mb_sysconf_t *m;
+
+        if(get_bus_conf_done==1) return; //do it only once
+
+        get_bus_conf_done = 1;
+
+       sysconf.mb = &mb_sysconf;
+
+       m = sysconf.mb;
+
+        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+
+        for(i=0;i<sysconf.hc_possible_num; i++) {
+                sysconf.pci1234[i] = pci1234x[i];
+                sysconf.hcdn[i] = hcdnx[i];
+        }
+
+        get_sblk_pci1234();
+
+        sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
+        m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
+
+       m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff;
+       m->bus_bcm5780[0] = m->bus_bcm5785_0;
+
+                /* bcm5785 */
+        printk_debug("search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0);
+        dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0));	
+        if (dev) {
+		printk_debug("found dev %s...\n",dev_path(dev));
+                m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		printk_debug("secondary is %d...\n",m->bus_bcm5785_1);
+               dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0));
+	       printk_debug("now found %s...\n",dev_path(dev));
+               if(dev) {
+                       m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
+                       m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                       m->bus_isa++;
+                       printk_debug("bus_isa 1=%d\n",m->bus_isa);
+#endif
+               }
+        }
+       else {
+                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
+        }
+
+               /* bcm5780 */
+       for(i = 1; i < 6; i++) {
+               dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
+               if(dev) {
+                       m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+                        m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        m->bus_isa++;
+                      printk_debug("bus_isa 2=%d\n",m->bus_isa);
+#endif
+
+               }
+               else {
+                       printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
+               }
+       }
+
+
+/*I/O APICs:   APIC ID Version State           Address*/
+#if CONFIG_LOGICAL_CPUS==1
+       apicid_base = get_apicid_base(3);
+#else
+       apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+       for(i=0;i<3;i++)
+               m->apicid_bcm5785[i] = apicid_base+i;
+}
Index: targets/hp/dl145_g3/Config.lb
===================================================================
--- targets/hp/dl145_g3/Config.lb	(revision 0)
+++ targets/hp/dl145_g3/Config.lb	(revision 0)
@@ -0,0 +1,60 @@
+##
+## This file is part of the Coreboot project.
+##
+## Copyright (C) 2007 University of Mannheim
+## Written by Philipp Degler <pdegler@rumms.uni-mannheim.de>
+## Copyright (C) 2009 University of Heidelberg
+## Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target dl145_g3
+mainboard hp/dl145_g3
+
+option ROM_SIZE=(1024*1024)
+
+# newisys RAPTOR
+romimage "normal"
+        #option USE_FAILOVER_IMAGE=0
+        option USE_FALLBACK_IMAGE=0
+        option ROM_IMAGE_SIZE=0x20000
+        option XIP_ROM_SIZE=0x20000
+        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+		    payload /home/mondrian/filo.elf
+
+end
+
+romimage "fallback"
+        #option USE_FAILOVER_IMAGE=0
+        option USE_FALLBACK_IMAGE=1
+        option ROM_IMAGE_SIZE=0x20000
+        option XIP_ROM_SIZE=0x20000
+        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+		    payload /home/mondrian/filo.elf
+
+
+end
+
+#romimage "failover"
+#        option USE_FAILOVER_IMAGE=1
+#        option USE_FALLBACK_IMAGE=0
+#        option ROM_IMAGE_SIZE=FAILOVER_SIZE
+#        option XIP_ROM_SIZE=FAILOVER_SIZE
+#        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+#end
+
+#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
