Hi,
as a noob I am trying to make a port based on the mahagony fam10, as the abit is also an AMD RS780/SB700 board. I have a Phenom II X4 840 installed, so I guess selecting fam10 is correct? I also adjusted the sources to use the correct superio (Winbond W83627DHG). Unfortunately the motherboard doesn't have serial ports, so I am debugging using a port80 diagnostics card... (Should I actually enable the com ports in devicetree.cb?)
So, I cannot make coreboot boot. On cold start it seems to hang in
src/southbridge/amd/sb700/reset.c
in soft_reset. set_bios_reset seems sucessful, but I get no post code after outb(0x06, 0x0cf9). Any idea, what I can try?
If I do a warm start (ie: booting with factory bios, flashing coreboot image and then reset) I get further, but it hangs somewhere in dev_enable. Probably my set_pcie_dereset and/or my devicetree.cb is wrong? How to find out the correct GPIOs for the former?
But before attacking these problems, I'd like to solve the early problem on cold start. Any hints?
(More infos, which are probably irrelevant at this point: I have seabios as payload, included the vga bios, which I extracted from factory bios and set coreboot rom execution off.)
Regards,
Prakash
On Monday 23 January 2012 20:12:33 Prakash Punnoor wrote:
Hi,
as a noob I am trying to make a port based on the mahagony fam10, as the abit is also an AMD RS780/SB700 board. I have a Phenom II X4 840 installed, so I guess selecting fam10 is correct? I also adjusted the sources to use the correct superio (Winbond W83627DHG). Unfortunately the motherboard doesn't have serial ports, so I am debugging using a port80 diagnostics card... (Should I actually enable the com ports in devicetree.cb?)
So, I cannot make coreboot boot. On cold start it seems to hang in
src/southbridge/amd/sb700/reset.c
in soft_reset. set_bios_reset seems sucessful, but I get no post code after outb(0x06, 0x0cf9). Any idea, what I can try?
If I do a warm start (ie: booting with factory bios, flashing coreboot image and then reset) I get further, but it hangs somewhere in dev_enable. Probably my set_pcie_dereset and/or my devicetree.cb is wrong? How to find out the correct GPIOs for the former?
Well, I came a bit further I found out the hang here was because of missing "device id" of my cpu. This solves that problem:
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index cf11135..24da249 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -153,6 +153,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ + { X86_VENDOR_AMD, 0x100F53 }, /* BL-C3 */ { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
Ignoring the soft_reset problem, now coreboot seems to successfully finish. The last post code is F8, so it seesm SeaBios should have been started. Unfortunately I the internal gfx doesn't seem to get propery initialized, as I cannot see anything. Then I changed to config to coreboot running vga option ROM and using grub2 as payload. On "warm start" coreboot now resets itself indefinitely. On cold start, coreboot want to do a soft reset - which still hangs. I think the soft reset here gets triggered by init_cpus. (I haven't verified this, yet.)
I am still not sure about the GPIO/GPM to use for dereset. At least GPM 8 and 9 and GPIO 73 look "fishy", ie the registers contain non default values, so I tried using them for dereset:
void set_pci_de_reset(int enable) { u8 byte; u16 word; device_t sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); byte &= ~((1 << 1) | (1 << 2)); pm_iowrite(0x8d, byte);
/* set the GPM8 and GPM9 output enable and the value to 1 */ byte = pm_ioread(0x94); byte &= ~((1 << 2) | (1 << 3)); if (enable) byte |= ((1 << 0) | (1 << 1)); else byte &= ~((1 << 0) | (1 << 1)); pm_iowrite(0x94, byte);
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = pci_read_config16(sm_dev, 0x5A); if (enable) word |= (1 << 3); /* GPIO 73 */ else word &= ~(1 << 3); word &= ~(1 << 7); word |= (1 << 15); pci_write_config16(sm_dev, 0x5A, word); }
void set_pcie_dereset() { set_pci_de_reset(1); }
void set_pcie_reset() { set_pci_de_reset(0); }
Attached is my devicetree.cb. The dual slot, gpp and gppsb config I read out from nbmisc registers.
Any help would be appreciated.
Regards,
Prakash
Prakash Punnoor wrote:
]...
]Well, I came a bit further I found out the hang here was because of missing
]"device id" of my cpu. This solves that problem:
Hello Prakash,
Great work finding this missing model problem.
]Ignoring the soft_reset problem, now coreboot seems to successfully finish.
]The last post code is F8, so it seesm SeaBios should have been started. ]Unfortunately I the internal gfx doesn't seem to get propery initialized, ]as I ]cannot see anything. Then I changed to config to coreboot running vga ]option ]ROM and using grub2 as payload. On "warm start" coreboot now resets itself ]indefinitely. On cold start, coreboot want to do a soft reset - which still
]hangs. I think the soft reset here gets triggered by init_cpus. (I haven't ]verified this, yet.)
It might be worth running your binary on simnow to debug. The public release of simnow includes a model (shiner_family10h.bsd) that is a close match to your hardware. The supplied shiner model uses cpuid 100F40 which should work fine, though cpuid 100F52 is available by switching to supplied model file Family10hBL-AM3_C2A.id. You would need to swap out the ITE SIO used by the Shiner mode to the Winbond 627. With simnow, you can route serial output to a named pipe and watch it with putty. Unfortunately simnow doesn't emulate the uma graphics portion of RS780. The shiner model includes a PCIe video card. You could switch that to a plain PCI video card connected to the SB700 and get that working. Then you could confirm it works on your board using a PCI video card. For the problem you are having with the RS780 video, did you confirm the video option rom is getting loaded to address C0000?
]...
]Regards, ] ]Prakash
On 29.01.2012 05:16, Scott Duplichan wrote:
Prakash Punnoor wrote: ]The last post code is F8, so it seesm SeaBios should have been started. ]Unfortunately I the internal gfx doesn't seem to get propery initialized, ]as I ]cannot see anything. Then I changed to config to coreboot running vga ]option ]ROM and using grub2 as payload. On "warm start" coreboot now resets itself ]indefinitely. On cold start, coreboot want to do a soft reset - which still
]hangs. I think the soft reset here gets triggered by init_cpus. (I haven't ]verified this, yet.)
It might be worth running your binary on simnow to debug.
Ok, I'll try setting it up. Hope it triggers the problems I am seeing.
For the problem you are having with the RS780 video, did you confirm the video option rom is getting loaded to address C0000?
Well, I don't know yet how to confirm it. I can see my post card showing 0x40 (IIRC, and previous code 0x36) for half a second or so. My guess is that video bios is running and thus causing the delay. I haven't searched the source code for these codes yet.
I am also considering porting my files to using agesa, as I can see that fam10h seems supported (though I have to add my cpu id here, as well). But I am not sure whether this is an easy task or not... some more .c files which seem to contain mainboard specific stuff. At least I found a supermicro board which is somewhat similar to my setup using agesa.
BTW, I am reading through the sources and found this in src/cpu/amd/car/cache_as_ram.inc:
134 bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
While I am not very experienced in assembler, esp AT&T syntax, I am wondering whether paranthesis are missing? Somewhat later I see this:
386 bt $(54 - 32), %edx
So I wonder is both correct or have I found a bug?
Cheers,
Prakash
-
Prakash Punnoor -
Scott Duplichan