Re: [coreboot] Trying to port abit A-S78H

[Prakash Punnoor]

On Monday 23 January 2012 20:12:33 Prakash Punnoor wrote:
> Hi,
>
> as a noob I am trying to make a port based on the mahagony fam10, as the
> abit is also an AMD RS780/SB700 board. I have a Phenom II X4 840 installed,
> so I guess selecting fam10 is correct? I also adjusted the sources to use
> the correct superio (Winbond W83627DHG). Unfortunately the motherboard
> doesn't have serial ports, so I am debugging using a port80 diagnostics
> card... (Should I actually enable the com ports in devicetree.cb?)
>
> So, I cannot make coreboot boot. On cold start it seems to hang in
>
> src/southbridge/amd/sb700/reset.c
>
> in soft_reset. set_bios_reset seems sucessful, but I get no post code after
> outb(0x06, 0x0cf9). Any idea, what I can try?
>
> If I do a warm start (ie: booting with factory bios, flashing coreboot image
> and then reset) I get further, but it hangs somewhere in dev_enable.
> Probably my set_pcie_dereset and/or my devicetree.cb is wrong? How to find
> out the correct GPIOs for the former?

Well, I came a bit further I found out the hang here was because of missing 
"device id" of my cpu. This solves that problem:

diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c 
b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index cf11135..24da249 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -153,6 +153,7 @@ static struct cpu_device_id cpu_table[] = {
        { X86_VENDOR_AMD, 0x100F42 },           /* RB-C2 */
        { X86_VENDOR_AMD, 0x100F43 },           /* RB-C3 */
        { X86_VENDOR_AMD, 0x100F52 },           /* BL-C2 */
+       { X86_VENDOR_AMD, 0x100F53 },           /* BL-C3 */
        { X86_VENDOR_AMD, 0x100F62 },           /* DA-C2 */
        { X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
        { X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */

Ignoring the soft_reset problem, now coreboot seems to successfully finish. 
The last post code is F8, so it seesm SeaBios should have been started. 
Unfortunately I the internal gfx doesn't seem to get propery initialized, as I 
cannot see anything. Then I changed to config to coreboot running vga option 
ROM and using grub2 as payload. On "warm start" coreboot now resets itself 
indefinitely. On cold start, coreboot want to do a soft reset - which still 
hangs. I think the soft reset here gets triggered by init_cpus. (I haven't 
verified this, yet.)

I am still not sure about the GPIO/GPM to use for dereset. At least GPM 8 and 
9 and GPIO 73 look "fishy", ie the registers contain non default values, so I 
tried using them for dereset:

void set_pci_de_reset(int enable)
{
    u8 byte;
    u16 word;
    device_t sm_dev;
    /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
    /* set 0 to bit2 :disable GPM8 as AZ_RST output */
    byte = pm_ioread(0x8d);
    byte &= ~((1 << 1) | (1 << 2));
    pm_iowrite(0x8d, byte);

/* set the GPM8 and GPM9 output enable and the value to 1 */
    byte = pm_ioread(0x94);
    byte &= ~((1 << 2) | (1 << 3));
    if (enable)
    	byte |=  ((1 << 0) | (1 << 1));
    else
    	byte &=  ~((1 << 0) | (1 << 1));
    
    pm_iowrite(0x94, byte);

sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));

word = pci_read_config16(sm_dev, 0x5A);
    if (enable)
    	word |= (1 << 3); /* GPIO 73 */
    else
    	word &= ~(1 << 3);
    
    word &= ~(1 << 7);
    word |= (1 << 15);
    pci_write_config16(sm_dev, 0x5A, word);
}

void set_pcie_dereset()
{
    set_pci_de_reset(1);
}

void set_pcie_reset()
{
    set_pci_de_reset(0);
}

Attached is my devicetree.cb. The dual slot, gpp and gppsb config I read out 
from nbmisc registers.

Any help would be appreciated.

Regards,

Prakash