#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. #Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_tmds, 0: didn't support TMDS, 1: support #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on chip cpu/amd/socket_AM2r2 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 device pci 6.0 off end # PCIE P2P bridge 0x9606 device pci 7.0 off end # PCIE P2P bridge 0x9607 device pci 8.0 off end # NB/SB Link P2P bridge device pci 9.0 on end # device pci a.0 on end # register "gppsb_configuration" = "4" # Configuration E default register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" register "gfx_lane_reversal" = "0" register "gfx_tmds" = "0" register "gfx_compliance" = "0" register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.1 on end # USB device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627dhg device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end #device pnp 2e.6 off # SPI #end device pnp 2e.307 off # GPIO6 end device pnp 2e.8 on # WDTO#, PLED end device pnp 2e.009 on # GPIO2 end device pnp 2e.109 on # GPIO3 end device pnp 2e.209 on # GPIO4 end device pnp 2e.309 off # GPIO5 end device pnp 2e.a off # ACPI end device pnp 2e.b on # HWM io 0x60 = 0x290 end device pnp 2e.c off # PECI, SST end end #superio/winbond/w83627dhg end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 off end # USB 2 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/sb700 end # device pci 18.0 device pci 18.0 on end device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end end #northbridge/amd/amdk8 end #pci_domain end #northbridge/amd/amdk8/root_complex