v3 updates

[ron minnich]

I just pushed a lot of bits across.

The problem with serengeti, if anybody wants to work on it, is that
the 8111 device is not scanning its subordinate busses. It would be
great if someone could take a look.

The dbm690t is almost ready for test, once the stage0 fits.It's 23k.
Help welcome.

ron

[Myles Watson]

Ron,

I'd like to help here more, but I don't understand the v3 architecture very
well.  I'm looking through the differences between the configuration spaces
of the factory BIOS, v2, and v3.

I also noticed that phase3_scan is null in 8111_ops.  Could that be the
problem?  Which function should be used to scan this bus?  I tried
pci_scan_bridge and pci_domain_scan_bus, but neither Just Worked for me.

Thanks,
Myles
> -----Original Message-----
> From: [e-mail] [mailto:[e-mail]]
> On Behalf Of ron minnich
> Sent: Monday, October 06, 2008 11:19 AM
> To: Coreboot
> Subject: [coreboot] v3 updates
>
> I just pushed a lot of bits across.
>
> The problem with serengeti, if anybody wants to work on it, is that
> the 8111 device is not scanning its subordinate busses. It would be
> great if someone could take a look.
>
> The dbm690t is almost ready for test, once the stage0 fits.It's 23k.
> Help welcome.
>
> ron

[Myles Watson]

Could you help me understand how we get from this picture from the 8111 data
sheet to the serengeti dts?  It looks like to me that the nic and ide
portions should be included in the amd8111 dts, not the board dts.  I'm also
confused why the ide and nic entries seem to be on the same bus.

Thanks,
Myles

On Mon, Oct 6, 2008 at 12:06 PM, Myles Watson  wrote:
> Ron,
>
> I'd like to help here more, but I don't understand the v3 architecture very
> well.  I'm looking through the differences between the configuration spaces
> of the factory BIOS, v2, and v3.
>
> I also noticed that phase3_scan is null in 8111_ops.  Could that be the
> problem?  Which function should be used to scan this bus?  I tried
> pci_scan_bridge and pci_domain_scan_bus, but neither Just Worked for me.
>
> Thanks,
> Myles
> > -----Original Message-----
> > From: [e-mail] [mailto:
>
> [e-mail]]
> > On Behalf Of ron minnich
> > Sent: Monday, October 06, 2008 11:19 AM
> > To: Coreboot
> > Subject: [coreboot] v3 updates
> >
> > I just pushed a lot of bits across.
> >
> > The problem with serengeti, if anybody wants to work on it, is that
> > the 8111 device is not scanning its subordinate busses. It would be
> > great if someone could take a look.
> >
> > The dbm690t is almost ready for test, once the stage0 fits.It's 23k.
> > Help welcome.
> >
> > ron

[ron minnich]

On Mon, Oct 6, 2008 at 11:59 AM, Myles Watson  wrote:
> Could you help me understand how we get from this picture from the 8111 data
> sheet to the serengeti dts?  It looks like to me that the nic and ide
> portions should be included in the amd8111 dts, not the board dts.  I'm also
> confused why the ide and nic entries seem to be on the same bus.

nic and ide are in mainboard dts so we can set control variables.

v3 is like v2 in that dts topology reflects mainboard topology but
does also show some detailsof chipset topology.

nic and ide on same bus? That's my mistake, pure and simple. The
mainboard dts is wrong.

We're in the learning phase here on dts for boards like this. We
understand simple boards like geode boards. This is our first complex
hierarchy board.

Welcome to Adventure!

ron

[Myles Watson]

All right.  I'd love to help fix it.  Here's the relevant snippet from
serengeti/dts

/* guesses; we need a real lspci */
        pci0@18,0 {
            /config/("northbridge/amd/k8/pci");
            pci@0,0 {
                /config/("southbridge/amd/amd8111/amd8111.dts");
            };
            pci@4,0 {
                /config/("southbridge/amd/amd8111/ide.dts");
            };
            pci@5,0 {
                /config/("southbridge/amd/amd8111/nic.dts");
            };
        };

from amd8111.dts:

{
    device_operations = "amd8111";
};

from amd8111/ide.dts:

{
    device_operations = "amd8111_ide";
    ide0_enable = "0";
    ide1_enable = "1";
};

from amd8111/nic.dts:

{
    device_operations = "amd8111_nic";
    phy_lowreset = "0";
};

I see that the device_operations structures get used, but I don't see how
there are parameters being passed here.  I'm sorry to be so clueless, I
don't understand the meaning of the dts yet.

Thanks,
Myles

On Mon, Oct 6, 2008 at 2:35 PM, ron minnich  wrote:
> On Mon, Oct 6, 2008 at 11:59 AM, Myles Watson  wrote:
> > Could you help me understand how we get from this picture from the 8111
>
> data
> > sheet to the serengeti dts?  It looks like to me that the nic and ide
> > portions should be included in the amd8111 dts, not the board dts.  I'm
>
> also
> > confused why the ide and nic entries seem to be on the same bus.
>
> nic and ide are in mainboard dts so we can set control variables.
>
> v3 is like v2 in that dts topology reflects mainboard topology but
> does also show some detailsof chipset topology.
>
> nic and ide on same bus? That's my mistake, pure and simple. The
> mainboard dts is wrong.
>
> We're in the learning phase here on dts for boards like this. We
> understand simple boards like geode boards. This is our first complex
> hierarchy board.
>
> Welcome to Adventure!
>
> ron

[ron minnich]

On Mon, Oct 6, 2008 at 2:14 PM, Myles Watson  wrote:
> All right.  I'd love to help fix it.  Here's the relevant snippet from
> serengeti/dts
>     /* guesses; we need a real lspci */
>     pci0@18,0 {
>         /config/("northbridge/amd/k8/pci");
>         pci@0,0 {
>             /config/("southbridge/amd/amd8111/amd8111.dts");
>         };
>         pci@4,0 {
>             /config/("southbridge/amd/amd8111/ide.dts");
>         };
>         pci@5,0 {
>             /config/("southbridge/amd/amd8111/nic.dts");
>         };
>     };
>
> from amd8111.dts:
>
> {
>     device_operations = "amd8111";
> };
>
> from amd8111/ide.dts:
>
> {
>     device_operations = "amd8111_ide";
>     ide0_enable = "0";
>     ide1_enable = "1";
> };
>
> from amd8111/nic.dts:
>
> {
>     device_operations = "amd8111_nic";
>     phy_lowreset = "0";
> };
>
> I see that the device_operations structures get used, but I don't see how
> there are parameters being passed here.  I'm sorry to be so clueless, I
> don't understand the meaning of the dts yet.

There are no parameters to pass on some things, so that is one issue.
You need these dts nodes in there to make the connection to the data
structure for the device_operations. This is a change in v3: no linker
sets, so arrays of structs that were created by the linker in v2 are
now created by the device tree compiler in v3 (which means you can
browse these structs with, e.g., kscope; the arrays of structs were
invisible in v2 as they were created by the linker).

Here is a proposed change to dts. I've forgotten all I ever knew about
the 8111 so I am pretty sure this is incomplete, but it's something
like what we want.

Index: mainboard/amd/serengeti/dts
===================================================================
--- mainboard/amd/serengeti/dts	(revision 904)
+++ mainboard/amd/serengeti/dts	(working copy)
@@ -28,18 +28,17 @@
    	/config/("northbridge/amd/k8/domain");
    	pci@1,0{
    	};
-		/* guesses; we need a real lspci */
    	pci0@18,0 {
    		/config/("northbridge/amd/k8/pci");
-			pci@0,0 {
+			pci@0,0 {
    			/config/("southbridge/amd/amd8111/amd8111.dts");
+				pci@1,0 {
+					/config/("southbridge/amd/amd8111/nic.dts");
+				};
    		};
    		pci@4,0 {
    			/config/("southbridge/amd/amd8111/ide.dts");
    		};
-			pci@5,0 {
-				/config/("southbridge/amd/amd8111/nic.dts");
-			};
    	};
    	pci1@18,0 {
    		/config/("northbridge/amd/k8/pci");

It still doesn't seem quite right. Segher?

ron

[Myles Watson]

> Here is a proposed change to dts. I've forgotten all I ever knew about
> the 8111 so I am pretty sure this is incomplete, but it's something
> like what we want.
> Index: mainboard/amd/serengeti/dts
>
> --- mainboard/amd/serengeti/dts	(revision 904)
> +++ mainboard/amd/serengeti/dts	(working copy)
> @@ -28,18 +28,17 @@
>    	/config/("northbridge/amd/k8/domain");
>    	pci@1,0{
>    	};
> /* guesses; we need a real lspci */
> pci0@18,0 {
> 	/config/("northbridge/amd/k8/pci");
> 	pci@0,0 {
> 	pci@0,0 {

/config/("southbridge/amd/amd8111/amd8111.dts");
> 		pci@1,0 {

/config/("southbridge/amd/amd8111/nic.dts");
> 		};
> };
> pci@4,0 {
> 	/config/("southbridge/amd/amd8111/ide.dts");
> };
> 	pci@5,0 {
> 		/config/("southbridge/amd/amd8111/nic.dts");
> 	};
> };
> pci1@18,0 {
> 	/config/("northbridge/amd/k8/pci");
>
> It still doesn't seem quite right. Segher?

I've played with it a little more, no luck yet.  Could you help me
understand the naming convention?

pci@5,0 = pci at device 5 function 0 ?

I don't see how we say there's a pci bridge at device 0 function 0 on this
bus, then specify the devices on the pci bus from there.

Should we be using the amd8111/pci.dts here too?  Maybe that's why you had
the phase3_scan = 0, since the pci bus should take care of its scan?

Thanks,
Myles

[ron minnich]

On Tue, Oct 7, 2008 at 9:44 AM, Myles Watson  wrote:
> > Here is a proposed change to dts. I've forgotten all I ever knew about
> > the 8111 so I am pretty sure this is incomplete, but it's something
> > like what we want.
> > Index: mainboard/amd/serengeti/dts
> >
> > --- mainboard/amd/serengeti/dts       (revision 904)
> > +++ mainboard/amd/serengeti/dts       (working copy)
> > @@ -28,18 +28,17 @@
> >               /config/("northbridge/amd/k8/domain");
> >               pci@1,0{
> >               };
> >         /* guesses; we need a real lspci */
> >         pci0@18,0 {
> >                 /config/("northbridge/amd/k8/pci");
> >                 pci@0,0 {
> >                 pci@0,0 {
>
> /config/("southbridge/amd/amd8111/amd8111.dts");
> >                         pci@1,0 {
>
> /config/("southbridge/amd/amd8111/nic.dts");
> >                         };
> >                 };
> >                 pci@4,0 {
> >                         /config/("southbridge/amd/amd8111/ide.dts");
> >                 };
> >                 pci@5,0 {
> >                         /config/("southbridge/amd/amd8111/nic.dts");
> >                 };
> >         };
> >         pci1@18,0 {
> >                 /config/("northbridge/amd/k8/pci");
> >
> > It still doesn't seem quite right. Segher?
>
> I've played with it a little more, no luck yet.  Could you help me
> understand the naming convention?
>
> pci@5,0 = pci at device 5 function 0 ?

yes
> I don't see how we say there's a pci bridge at device 0 function 0 on this
> bus, then specify the devices on the pci bus from there.

the bridge is actually implied by the fact that the node has child
nodes (as in v2). But yes, I see your point.
I don't have time to look today but there is some simple thing wrong.
The devices are straight from v2.
> Should we be using the amd8111/pci.dts here too?  Maybe that's why you had
> the phase3_scan = 0, since the pci bus should take care of its scan?

Hmm, not sure, ref. v2 again.

I think we should take a careful look at v2 again but I think this is
a  simple problem that just needs
close looking at ...

ron

[Marc Jones]

ron minnich wrote:
> On Mon, Oct 6, 2008 at 11:59 AM, Myles Watson  wrote:
> > Could you help me understand how we get from this picture from the 8111 data
> > sheet to the serengeti dts?  It looks like to me that the nic and ide
> > portions should be included in the amd8111 dts, not the board dts.  I'm also
> > confused why the ide and nic entries seem to be on the same bus.
>
> nic and ide are in mainboard dts so we can set control variables.
>
> v3 is like v2 in that dts topology reflects mainboard topology but
> does also show some detailsof chipset topology.
>
> nic and ide on same bus? That's my mistake, pure and simple. The
> mainboard dts is wrong.
>
> We're in the learning phase here on dts for boards like this. We
> understand simple boards like geode boards. This is our first complex
> hierarchy board.

Yes, the mainboard dts is where you want to control this. On many 
platforms the on silicon devices may not be used and disabled.

Marc

[ron minnich]

On Mon, Oct 6, 2008 at 11:06 AM, Myles Watson  wrote:
> I also noticed that phase3_scan is null in 8111_ops.  Could that be the
> problem?  Which function should be used to scan this bus?  I tried
> pci_scan_bridge and pci_domain_scan_bus, but neither Just Worked for me.

yes, missing phase3_scan is bad. I wonder how I missed that.

ron