Could you help me understand how we get from this picture from the 8111 data sheet to the serengeti dts?  It looks like to me that the nic and ide portions should be included in the amd8111 dts, not the board dts.  I'm also confused why the ide and nic entries seem to be on the same bus.

Thanks,
Myles

On Mon, Oct 6, 2008 at 12:06 PM, Myles Watson <mylesgw@gmail.com> wrote:
Ron,

I'd like to help here more, but I don't understand the v3 architecture very
well.  I'm looking through the differences between the configuration spaces
of the factory BIOS, v2, and v3.

I also noticed that phase3_scan is null in 8111_ops.  Could that be the
problem?  Which function should be used to scan this bus?  I tried
pci_scan_bridge and pci_domain_scan_bus, but neither Just Worked for me.

Thanks,
Myles

> -----Original Message-----
> From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org]
> On Behalf Of ron minnich
> Sent: Monday, October 06, 2008 11:19 AM
> To: Coreboot
> Subject: [coreboot] v3 updates
>
> I just pushed a lot of bits across.
>
> The problem with serengeti, if anybody wants to work on it, is that
> the 8111 device is not scanning its subordinate busses. It would be
> great if someone could take a look.
>
> The dbm690t is almost ready for test, once the stage0 fits.It's 23k.
> Help welcome.
>
> ron
>
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