Setup the MTRRs in stage1 so that memory and cache are available throughout stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF. It also sets all system memory to WriteBack cached and sets the ROM area to cached.
Signed-off-by: Marc Jones marcj303@gmail.com
On Fri, Feb 6, 2009 at 6:26 PM, Peter Stuge peter@stuge.se wrote:
+ /* System ROM (Assume 1MB) */
Can we do CONFIG_COREBOOT_ROM_SIZE_KB << 10 instead? Otherwise we'll have breakage with any rom >1MB.
Thanks, Corey
On 06.02.2009 23:37, Marc Jones wrote:
The code looks scary, especially the part where you disable cache although memory may not be set up completely yet. Can you explain why that is not a problem? Thanks.
My general principle is "don't fiddle with cache settings until you know RAM is fine".
Regards, Carl-Daniel
On Sat, Feb 7, 2009 at 4:05 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
I guess that comment could use more clarification. The RAM that is available will be cached but not all the memory in the system may be setup when set_mtrr_ram_access is called. It is the job of the memory/cpu init code to call it again as memory is added. Note the the cache is being set based on TOM and TOM2.
Marc
On Sat, Feb 7, 2009 at 10:28 AM, Marc Jones marcj303@gmail.com wrote:
Fixed the comment for clarity and the ROM size based on the config.
Marc
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Carl-Daniel Hailfinger -
Corey Osgood -
Marc Jones -
Peter Stuge