[v3][patch] Add early MTRR setup

[Marc Jones]

Setup the MTRRs in stage1 so that memory and cache are available throughout
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.

Signed-off-by: Marc Jones

[Peter Stuge]

Marc Jones wrote:
> Setup the MTRRs in stage1 so that memory and cache are available throughout
> stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
> It also sets all system memory to WriteBack cached and sets the ROM
> area to cached.
>
> Signed-off-by: Marc Jones

Acked-by: Peter Stuge

[Corey Osgood]

On Fri, Feb 6, 2009 at 6:26 PM, Peter Stuge  wrote:
> Marc Jones wrote:
> > Setup the MTRRs in stage1 so that memory and cache are available
>
> throughout
> > stage2. This fixes problems with VGA graphics ROMs access to
>
> 0xA0000-0xBFFFF.
> > It also sets all system memory to WriteBack cached and sets the ROM
> > area to cached.
> >
> > Signed-off-by: Marc Jones
>
> Acked-by: Peter Stuge

+    /* System ROM (Assume 1MB) */
> stage1_set_var_mtrr(1, 0xFFF00000, 0x00100000, MTRR_TYPE_WRTHROUGH);

Can we do CONFIG_COREBOOT_ROM_SIZE_KB << 10 instead? Otherwise we'll have
breakage with any rom >1MB.

Thanks,
Corey

[Carl-Daniel Hailfinger]

On 06.02.2009 23:37, Marc Jones wrote:
> Setup the MTRRs in stage1 so that memory and cache are available throughout
> stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
> It also sets all system memory to WriteBack cached and sets the ROM
> area to cached.
>
> Signed-off-by: Marc Jones

The code looks scary, especially the part where you disable cache
although memory may not be set up completely yet. Can you explain why
that is not a problem? Thanks.

My general principle is "don't fiddle with cache settings until you know
RAM is fine".

Regards,
Carl-Daniel

[Marc Jones]

On Fri, Feb 6, 2009 at 9:58 PM, Corey Osgood  wrote:
> On Fri, Feb 6, 2009 at 6:26 PM, Peter Stuge  wrote:
> > Marc Jones wrote:
> > > Setup the MTRRs in stage1 so that memory and cache are available
> > > throughout
> > > stage2. This fixes problems with VGA graphics ROMs access to
> > > 0xA0000-0xBFFFF.
> > > It also sets all system memory to WriteBack cached and sets the ROM
> > > area to cached.
> > >
> > > Signed-off-by: Marc Jones
> >
> > Acked-by: Peter Stuge
> > /* System ROM (Assume 1MB) */
> > stage1_set_var_mtrr(1, 0xFFF00000, 0x00100000, MTRR_TYPE_WRTHROUGH);
>
> Can we do CONFIG_COREBOOT_ROM_SIZE_KB << 10 instead? Otherwise we'll have
> breakage with any rom >1MB.
>
> Thanks,
> Corey

Sure, no problem.

Marc

[Marc Jones]

On Sat, Feb 7, 2009 at 4:05 AM, Carl-Daniel Hailfinger
 wrote:
> On 06.02.2009 23:37, Marc Jones wrote:
> > Setup the MTRRs in stage1 so that memory and cache are available throughout
> > stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
> > It also sets all system memory to WriteBack cached and sets the ROM
> > area to cached.
> >
> > Signed-off-by: Marc Jones
>
> The code looks scary, especially the part where you disable cache
> although memory may not be set up completely yet. Can you explain why
> that is not a problem? Thanks.
>
> My general principle is "don't fiddle with cache settings until you know
> RAM is fine".

I guess that comment could use more clarification. The RAM that is
available will be cached but not all the memory in the system may be
setup when set_mtrr_ram_access is called. It is the job of the
memory/cpu init code to call it again as memory is added. Note the the
cache is being set based on TOM and TOM2.

Marc

[Marc Jones]

On Sat, Feb 7, 2009 at 10:28 AM, Marc Jones  wrote:
> On Sat, Feb 7, 2009 at 4:05 AM, Carl-Daniel Hailfinger
>  wrote:
> > On 06.02.2009 23:37, Marc Jones wrote:
> > > Setup the MTRRs in stage1 so that memory and cache are available throughout
> > > stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
> > > It also sets all system memory to WriteBack cached and sets the ROM
> > > area to cached.
> > >
> > > Signed-off-by: Marc Jones

Fixed the comment for clarity and the ROM size based on the config.

Marc

[Marc Jones]

On Mon, Feb 9, 2009 at 1:18 PM, Marc Jones  wrote:
> On Sat, Feb 7, 2009 at 10:28 AM, Marc Jones  wrote:
> > On Sat, Feb 7, 2009 at 4:05 AM, Carl-Daniel Hailfinger
> >  wrote:
> > > On 06.02.2009 23:37, Marc Jones wrote:
> > > > Setup the MTRRs in stage1 so that memory and cache are available throughout
> > > > stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
> > > > It also sets all system memory to WriteBack cached and sets the ROM
> > > > area to cached.
> > > >
> > > > Signed-off-by: Marc Jones
>
> Fixed the comment for clarity and the ROM size based on the config.
>
> Marc

r1128