Acked-by: Peter Stuge <peter@stuge.se>Marc Jones wrote:
> Setup the MTRRs in stage1 so that memory and cache are available throughout
> stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
> It also sets all system memory to WriteBack cached and sets the ROM
> area to cached.
>
> Signed-off-by: Marc Jones <marcj303@gmail.com>
+ /* System ROM (Assume 1MB) */
+ stage1_set_var_mtrr(1, 0xFFF00000, 0x00100000, MTRR_TYPE_WRTHROUGH);