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39779 discussions

alternate startup idea.
by ron minnich 23 Jul '03

23 Jul '03

Well, my alternate startup idea works fine on the K8. Except ... looks like flash rom addressing is not enabled by default for anything but the 0xffff0000 segment, which means while my idea works, it's useless: if I jump to the 0xfffe0000 segment, I'll be reading air, not the flash part. Darn it. I kind of wish that we could get the chipmakers to default to full addressing in the high part of the address space, i.e. when it decodes for the flash, it decodes from 0xfff00000 up, not 0xffff0000 up. Someday ... Well, at least I have an interesting (I guess) proof-of-concept. Not sure where to take it, but I think I'll go ahead and put it aside. Sigh. ron

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NVidia NForce2
by Marco Hetzel 23 Jul '03

23 Jul '03

Hi! The help-fromular on your page isn't working, so I once again try to write here. Are there any Driver for the NForce2 - Chipset? THX, Marco

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K8 Progress
by ron minnich 22 Jul '03

22 Jul '03

it's getting easier and easier to resync the new config tool to the ongoing changes. Took a few minutes earlier today and I was back on the air. I have noticed that the testing of the first 16M of memory in auto.c is very slow, so I've turned it off on my version. My guess is for you guys it runs very fast. There must still be a difference somewhere. Can someone confirm that the K8 memory test in auto.c is fast? A note on the SST 49LF0[48]0 flash parts, since we've all had trouble with them. Here's what I have found. The first time I flash there is always trouble. However, if I 'eraseall /dev/mtd0' a few times, then do the 'dd trick': dd if=image of=/dev/mtd0 bs=65536 seek=$i skip=$i i.e. program individual blocks, it almost always works. >From that point on, programming is a matter of cat image > /dev/mtd0 So it seems there is something 'sticky' in these parts when new, cured by programming individual blocks. Flash is very odd ... ron

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second alternate startup idea
by ron minnich 22 Jul '03

22 Jul '03

Seems to me we could enable the full flash rom decoding, then put the c_payload at 0xfffx0000, then have really big linuxbios images. I'll take a look at this too, later. ron

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About my last post
by Gregg C Levine 22 Jul '03

22 Jul '03

Hello again from Gregg C Levine I dislike sending these. Along with the problems associated with this cloddish mailer. Sorry guys for sending that blasted thing out, twice. Ron, when you get the four of them, just discard one pair, or the other. ------------------- Gregg C Levine hansolofalcon(a)worldnet.att.net ------------------------------------------------------------ "The Force will be with you...Always." Obi-Wan Kenobi "Use the Force, Luke." Obi-Wan Kenobi (This company dedicates this E-Mail to General Obi-Wan Kenobi ) (This company dedicates this E-Mail to Master Yoda )

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K8 news
by ron minnich 22 Jul '03

22 Jul '03

For those just joining. Eric Biederman has a solid C compiler for x86 for no-memory situations. The amount of assembly code in LinuxBIOS shrinks day-by-day. Stefan Reinauer at Suse and Eric have been working on different parts of the K8 problem and have linuxbios up on K8 1, 2, and 4 CPU systems. YHLu of Tyan has linuxbios up on the new K8 motherboard. Linuxbios also works now on the Arima HDAMA. Greg Watson and I have been upgrading the config tool. It is a substantial improvement. I am now easily able to track the tree and build with the new config tool only. The new tool is faster and produces more comprehensible makefiles. Perl expressions in makefiles are a thing of the past. The new tool is also much better for non-PC systems, e.g. PPC. I am also booting Linux directly out of FLASH using the 49LF080 1 Mbyte parts. I will be starting work on the NewISYS board soon. AMD has provided support in many ways, including opening up the documents. AMD should be credited for their longstanding support of LinuxBIOS on the K8, going back to long before the K8 was officially released. I think vendors such as AMD, LNXI, Suse, Tyan, Arima, and Newisys (I hope I left no one else out) are to be commended for their support of LinuxBIOS on this new CPU. This work represents a substantial financial commitment on the part of these companies. Thanks to you all. ron

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fallbackimage, question
by Felix Kloeckner 22 Jul '03

22 Jul '03

hello, i successfully ported the fallbackimage-principle for the elitegroup p6stp-fl (sis630)but the problem is that it only works with 64KB fallback-image (i took the calculations from "supermicro/p4dpeg2/Config") because i need more space for the payload i need a bigger fallbackimage, but if i change the size of "FALLBACK_IMAGE_SIZE" only the fallbackimage will boot, not the normalimage (each time the normalimage should be jumped to the watchdogtimer expires and resets the board, after that the fallbackimage will boot again) does anybody see what i made wrong? (below is a part of my config - felix size related stuff from my config ---------------------------------------------- option USE_FALLBACK_IMAGE=0 expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE option ROM_SIZE=0x80000 #works only with exactly 0x10000, need more! <--------- option FALLBACK_IMAGE_SIZE=0x10000 option ROM_IMAGE_SIZE=43520 expr ROM_SECTION_SIZE=(USE_FALLBACK_IMAGE * FALLBACK_IMAGE_SIZE) + (USE_NORMAL_IMAGE * (ROM_SIZE - FALLBACK_IMAGE_SIZE) ) expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE * (ROM_SIZE - FALLBACK_IMAGE_SIZE)) + (USE_NORMAL_IMAGE * 0) expr ZKERNEL_START=(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) expr PAYLOAD_SIZE=ROM_SECTION_SIZE - ROM_IMAGE_SIZE expr _ROMBASE=ZKERNEL_START + PAYLOAD_SIZE #cache the upper 16M of the 4G address space #or else the decompression would be so slow that #the watchdogtimer resets the board even before #decompression is done option XIP_ROM_SIZE= 0x01000000 option XIP_ROM_BASE= 0xfe000000

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Re: K8 + 2.4.21 + Tyan S2880
by YhLu 22 Jul '03

22 Jul '03

Eric, It can be compiled with you new code. But it meet problems in Etherboot stage. In S2880 has two broadcom NIC port in 8131 bus B, and one amd 8111 built-in nic, and even if I hide it in amd8111 init and Etherboot can find it and try to enable it and can not find the PM cap so aborting, in the old linuxbios code (before yesterday) ( with mem hard code), it will go to tickle on Broadcom nic, but in the new code (yesterday check in) ( mem configurable), it will go to MB restarting.??? How about arima broadcom nic position? Regards Yinghai Lu -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年7月21日 18:33 收件人: YhLu 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: K8 + 2.4.21 + Tyan S2880 YhLu <YhLu(a)tyan.com> writes: > Eric, > > In the auto.c, if I enable : sdram_initialize(&cpu1), the linuxbios need > another 20k. What happened? Only add one line and the same function has been > called ??? All functions are inline and the set of functions called is large. At least I believe that is the issue. And good luck catching up.... While I am away you get a chance. My latest code has changed sdram_initialize one more time to take a cpu count parameter. And perversely this should help because if a function is called in a loop it will only be inlined once instead of multiple times. Eric

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Re: configurable onboard components
by ron minnich 22 Jul '03

22 Jul '03

On Tue, 22 Jul 2003, Stefan Reinauer wrote: > * you disabled onboard ethernet and ac97 in amd8111_lpc.c > can we make this somehow configurable? Is there a way to probe > whether these are actually wired through to some outputs? hmm, could I have a better example of why we need that static device tree :-) ron

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SPD reading with asus A7S333 - SiS745
by Rudolf Marek 22 Jul '03

22 Jul '03

Hello, Someone earlier got similar problem. Asus is muxing the devices on the SMBUS. I'm developing drivers for lm_sensors project. (W83785 driver) I got my smbus working (same as SiS645) There are some devices on the bus - ATXP2, W83785 and some Asus ASIC. But no SPD EEPROM, nor PLL. I'm curious about the content of my SPD. Someone here pointed out that it can be enabled by some of GPO bits. I got 2 problems. 1) I dont have a datasheet for SiS745 (I ot only for SiS630) 2) I dont know which GPO to enable. Please would someone be so king and give me some advice? I got disassembled BIOS for reference, but I even dont know in wich PCI dev should I look for GPO. You will need this information anyway if you plan tu support this motherboard :) (it will be very nice) Regards Rudolf Marek

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