coreboot September 2018

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160 discussions

Re: [coreboot] Kabylake unable to boot with post code 0x71
by Naresh G. Solanki 18 Sep '18

18 Sep '18

Hi Jose, Ideally, FSP silicon init returns if there is error & error code is displayed. Since return has not happended then it is most likely that input to FSPS UPD which comes from devicetree.cb might have gone wrong. In other word, can you match devicetree.cb setting with descriptor & board schematics. Especially check: domain_vr_config Additionally can you provide info like when the hang happens, what is state of SLP_S0/3/4/5. Also check voltage level for VCC_CORE/GT/SA Regards, Naresh G Solanki On Tue, Sep 18, 2018 at 3:01 PM Jose Trujillo via coreboot <coreboot(a)coreboot.org> wrote: > > Dear Naresh / All: > > I added their corresponding FSP headers but still the system never returns from the FSP function (fsp_silicon_init) post 0x71. > > My question is if somebody can tell me how to enable (if possible) FSP port 80 post codes and/or FSP serial debug from SIO (non SOC) UART. > > Thank you, > Jose Trujillo > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > On Monday, September 17, 2018 6:14 PM, Naresh G. Solanki <naresh.solanki.2011(a)gmail.com> wrote: > > > Location in coreboot folder: > > https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp… > > > > Header Files can be taken from location: > > https://github.com/IntelFsp/FSP/tree/master/KabylakeFspBinPkg/Include > > > > FSP binary can be taken from: > > https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Fsp.fd > > > > This file needs to be split into fspm.bin fsps.bin . For this refer: > > https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/UserManual… > > On Mon, Sep 17, 2018 at 7:51 PM Jose Trujillo ce.autom(a)protonmail.com wrote: > > > > > Thank you Naresh, > > > How to do the copy? > > > Could you give me some details? > > > You too have an excellent day. > > > Jose. > > > Sent with ProtonMail Secure Email. > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > On Monday, September 17, 2018 5:17 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > I guess the FSP version you have is 3.5.0 > > > You should have received fsp header along with fsp binary in single package. > > > However you can get FSP binaries and header from https://github.com/IntelFsp/FSP > > > Also make sure you copy FSP header version equal fsp binary version. > > > All the best! > > > On Mon 17 Sep, 2018, 3:34 PM Jose Trujillo via coreboot, coreboot(a)coreboot.org wrote: > > > > > > > Dear Naresh: > > > > You are right; it never returns from the FSP function (fsp_silicon_init). > > > > chip_fsp20.c Ln.169 > > > > void soc_init_pre_device(void chip_info) > > > > { > > > > printk(BIOS_INFO, "Entering: fsp_silicon_init"); // Added > > > > / Perform silicon specific init. / > > > > fsp_silicon_init(romstage_handoff_is_resume()); > > > > / swap enabled PCI ports in device tree if needed */printk(BIOS_INFO, "Entering: pcie_override_devicetree"); // Added > > > > pcie_override_devicetree_after_silicon_init(); > > > > printk(BIOS_INFO, "Exit: soc_init_pre_device"); // Added > > > > } > > > > Serial dump. > > > > .... > > > > Enabling SMIs. > > > > Locking SMM. > > > > VMX : param.enable = 0 > > > > VMX: pre-conditions not met > > > > VMX: pre-conditions not met > > > > VMX: pre-conditions not met > > > > SGX: pre-conditions not met > > > > VMX: pre-conditions not met > > > > SGX: pre-conditions not met > > > > POST: 0x71 > > > > SGX: pre-conditions not met > > > > SGX: pre-conditions not met > > > > Entering: fsp_silicon_init <------ never returns from FSP. > > > > .... > > > > About the FSP header version I am not sure how exactly to obtain it but getting the binary decription from BCT I got: > > > > Header Revision: 0x3 > > > > Image Revision: 0x3050000 > > > > 3.0.5 ???? > > > > See the attached file for more details about the FSP binary. > > > > Please advise. > > > > Thank you, > > > > Jose Trujillo. > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > On Friday, September 14, 2018 6:58 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > > > > > With available data. It is most likely that it might have stuck > > > > > somewhere in function > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/ch… > > > > > You can add printk in that function & other functions called by it to > > > > > bisect & confirm the exact position of hang.. > > > > > Also can you please check FSP binary version you are using versus FSP > > > > > header version checked-out in coreboot(which is currently 2.9.2). > > > > > They should be > > > > > On Fri, Sep 14, 2018 at 7:55 PM Jose Trujillo via coreboot > > > > > coreboot(a)coreboot.org wrote: > > > > > > > > > > > Here is Naresh.... > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > On Friday, September 14, 2018 4:49 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > > Can you also provide latest complete log. > > > > > > On Fri 14 Sep, 2018, 2:10 PM Jose Trujillo via coreboot, coreboot(a)coreboot.org wrote: > > > > > > > > > > > > > Thank you Naresh, > > > > > > > I added the missing PCH device id following your advise, also enabled DEBUG_BOOT_STATE but I am still not able to get more information via serial debug about the exact location of the problem (but now I am certain is in the coreboot code not in FSP). > > > > > > > I suspect the code involved aound this issue is hardwaremain.c and device.c.... > > > > > > > Only the first "boot" just after flash I notice that the ethernet and SATA LEDs blink for a fraction of a second then reboots. > > > > > > > After that, the following attempts to boot I don't see LED activity neither reboots, just halted in some kind of loop. > > > > > > > According to the serial dump the las printed text is "0x71" but my question is if the serial port gets broken still during "BS_DEV_INIT_CHIPS" or is already doing "BS_DEV_ENUMERATE". > > > > > > > As Naresh pointed my PCH H chipset "Kabylake-H HM175" was not added to the list; I added it but may be is needed to do something else to make it work. > > > > > > > Or istill is misconfigured (attached my .config file for your review)... I someone has a similar system working and want to share its configuration files to compare them myself I will be grateful. > > > > > > > Jose Trujillo. > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > On Wednesday, 12 September 2018 19:33, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > > > Hi > > > > > > > > > > > > > > > PCH: device id a152 (rev 31) is Unknown > > > > > > > > > > > > > > This indicates that LPCID 0xa152 is not added. > > > > > > > The #define should be added in source path: https://review.coreboot.org/cgit/coreboot.git/tree/src/include/device/pci_i… > > > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/blo… > > > > > > > & > > > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/bo… > > > > > > > as well. > > > > > > > Additionally you can enable config DEBUG_BOOT_STATE to understand where exactly its stuck. > > > > > > > Regards, > > > > > > > Naresh G. Solanki > > > > > > > On Wed, Sep 12, 2018 at 9:24 PM Jose Trujillo via coreboot coreboot(a)coreboot.org wrote: > > > > > > > > > > > > > > > Dear All, > > > > > > > > About the memory I just changed the dimm to address A0 and now coreboot is reporting correctly 1 dimm detected. > > > > > > > > But still no luck on the 0x71 post code loop (looks it is in some kind of loop because is still responsive to power and reset buttons). > > > > > > > > I don't know where this loop could be located (coreboot or FSP). > > > > > > > > The description on the post_codes.h file shows the following: > > > > > > > > .... > > > > > > > > /** > > > > > > > > > > > > > > > > - \brief Initializing Chips > > > > > > > > - > > > > > > > > - Boot State Machine: bs_dev_init_chips() > > > > > > > > */ > > > > > > > > #define POST_BS_DEV_INIT_CHIPS 0x71 > > > > > > > > .... > > > > > > > > > > > > > > > > > > > > > > > > Any advice on this issue? > > > > > > > > Attached is the serial dump with extra information. > > > > > > > > Thank you > > > > > > > > Jose Trujillo > > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > > On Wednesday, 12 September 2018 16:12, Jose Trujillo ce.autom(a)protonmail.com wrote: > > > > > > > > To begin with the system didn't find memory attached... > > > > > > > > but there is memory attached, SPD address mismatch? I will check. > > > > > > > > .... > > > > > > > > .......Timeout while sending command 0x0d to EC! > > > > > > > > recv_ec_data: 0xff > > > > > > > > recv_ec_data: 0xff > > > > > > > > SPD index 7 > > > > > > > > No memory dimm at address A0 > > > > > > > > No memory dimm at address A2 > > > > > > > > No memory dimm at address A6 > > > > > > > > .... > > > > > > > > 0 DIMMs found > > > > > > > > .... > > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > > On Wednesday, 12 September 2018 13:29, Jose Trujillo via coreboot coreboot(a)coreboot.org wrote: > > > > > > > > Dear coreboot engineers: > > > > > > > > Right now I am stuck with a Kabylake system with the following message: > > > > > > > > .... > > > > > > > > CPU #1 initialized > > > > > > > > apic_id: 0x06 done. > > > > > > > > microcode: updated to revision 0x8d date=2018-01-21 > > > > > > > > CPU #3 initialized > > > > > > > > bsp_do_flight_plan done after 220 msecs. > > > > > > > > CPU: frequency set to 3600 MHz > > > > > > > > Enabling SMIs. > > > > > > > > Locking SMM. > > > > > > > > VMX : param.enable = 0 > > > > > > > > VMX: pre-conditions not met > > > > > > > > SGX: pre-conditions not met > > > > > > > > VMX: pre-conditions not met > > > > > > > > VMX: pre-conditions not met > > > > > > > > SGX: pre-conditions not met > > > > > > > > SGX: pre-conditions not met > > > > > > > > VMX: pre-conditions not met > > > > > > > > SGX: pre-conditions not met > > > > > > > > POST: 0x71 > > > > > > > > .... > > > > > > > > May be some configuration is missing and I am trying to find this out myself but if someone of you can give a hint on how to resolve it I will be grateful. > > > > > > > > Attached is the full serial dump. > > > > > > > > Thank you, > > > > > > > > Jose Trujillo > > > > > > > > > > > > > > > > ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- > > > > > > > > > > > > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > > > > > > > -- > > > > > > > Best regards, > > > > > > > Naresh G. Solanki > > > > > > > > > > > > > > ----------------------------------- > > > > > > > > > > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > > > > > -- > > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > > > -- > > > > > Best regards, > > > > > Naresh G. Solanki > > > > > > > > -- > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > -- > > > > Best regards, > > Naresh G. Solanki > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- Best regards, Naresh G. Solanki

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 18 Sep '18

18 Sep '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1395725: Control flow issues (DEADCODE) /src/mainboard/intel/coffeelake_rvp/romstage.c: 23 in mainboard_memory_init_params() ________________________________________________________________________________________________________ *** CID 1395725: Control flow issues (DEADCODE) /src/mainboard/intel/coffeelake_rvp/romstage.c: 23 in mainboard_memory_init_params() 17 #include <baseboard/variants.h> 18 #include <soc/cnl_memcfg_init.h> 19 #include <soc/romstage.h> 20 21 void mainboard_memory_init_params(FSPM_UPD *memupd) 22 { >>> CID 1395725: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "spd.spd_smbus_address[spd@d...". 23 const struct spd_info spd = { 24 .spd_smbus_address[0] = 0xA0, 25 .spd_smbus_address[1] = 0xA2, 26 .spd_smbus_address[2] = 0xA4, 27 .spd_smbus_address[3] = 0xA6, 28 }; 29 30 cannonlake_memcfg_init(&memupd->FspmConfig, 31 variant_memcfg_config(), &spd); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Re: [coreboot] UEFI Payload update
by Patrick Georgi 18 Sep '18

18 Sep '18

Regarding the (off-topic) discussion of slimboot's merits: I share some of the sentiment, but it's certainly possible to phrase it a less confrontational way. We can moderate individuals on this list, so if you can't watch your words, I will. Regards, Patrick Am Di., 18. Sep. 2018 um 11:56 Uhr schrieb Ivan Ivanov <qmastery16(a)gmail.com >: > Slim Bootloader? Thanks, but > " We wanted the open source Intel ME / FSP firmwares, and all we got > is this lousy byproduct of Not-Invented-Here syndrome " > /thread > вт, 18 сент. 2018 г. в 5:18, You, Benjamin <benjamin.you(a)intel.com>: > > > > Hi, > > > > A staging project "UEFIPayload" has been started to upgrade the > Coreboot*Pkgs in EDK II repository. > > > > The new features are: > > - Supporting Slim Bootloader (https://github.com/slimbootloader) in > addition to Coreboot > > - Source file configuration using .ini format > > - User extension using simple "C" libs > > - Platform supporting lib > > > > The link of this project is: > https://github.com/tianocore/edk2-staging/tree/UEFIPayload > > > > Thanks, > > > > - ben > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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Re: [coreboot] UEFI Payload update
by Alberto Bursi 18 Sep '18

18 Sep '18

Slim-bootloader is BSD-license. Not just NIH, it "fixes" one of the last big Coreboot "isses", the license. Gotta protect your IP man, think of the children. -Alberto On 9/18/2018 11:54 AM, Ivan Ivanov wrote: > Slim Bootloader? Thanks, but > " We wanted the open source Intel ME / FSP firmwares, and all we got > is this lousy byproduct of Not-Invented-Here syndrome " > /thread > вт, 18 сент. 2018 г. в 5:18, You, Benjamin <benjamin.you(a)intel.com>: >> Hi, >> >> A staging project "UEFIPayload" has been started to upgrade the Coreboot*Pkgs in EDK II repository. >> >> The new features are: >> - Supporting Slim Bootloader (https://github.com/slimbootloader) in addition to Coreboot >> - Source file configuration using .ini format >> - User extension using simple "C" libs >> - Platform supporting lib >> >> The link of this project is: https://github.com/tianocore/edk2-staging/tree/UEFIPayload >> >> Thanks, >> >> - ben >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] UEFI Payload update
by Ivan Ivanov 18 Sep '18

18 Sep '18

Slim Bootloader? Thanks, but " We wanted the open source Intel ME / FSP firmwares, and all we got is this lousy byproduct of Not-Invented-Here syndrome " /thread вт, 18 сент. 2018 г. в 5:18, You, Benjamin <benjamin.you(a)intel.com>: > > Hi, > > A staging project "UEFIPayload" has been started to upgrade the Coreboot*Pkgs in EDK II repository. > > The new features are: > - Supporting Slim Bootloader (https://github.com/slimbootloader) in addition to Coreboot > - Source file configuration using .ini format > - User extension using simple "C" libs > - Platform supporting lib > > The link of this project is: https://github.com/tianocore/edk2-staging/tree/UEFIPayload > > Thanks, > > - ben > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Kabylake unable to boot with post code 0x71
by Jose Trujillo 18 Sep '18

18 Sep '18

Dear Naresh / All: I added their corresponding FSP headers but still the system never returns from the FSP function (fsp_silicon_init) post 0x71. My question is if somebody can tell me how to enable (if possible) FSP port 80 post codes and/or FSP serial debug from SIO (non SOC) UART. Thank you, Jose Trujillo ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Monday, September 17, 2018 6:14 PM, Naresh G. Solanki <naresh.solanki.2011(a)gmail.com> wrote: > Location in coreboot folder: > https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp… > > Header Files can be taken from location: > https://github.com/IntelFsp/FSP/tree/master/KabylakeFspBinPkg/Include > > FSP binary can be taken from: > https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Fsp.fd > > This file needs to be split into fspm.bin fsps.bin . For this refer: > https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/UserManual… > On Mon, Sep 17, 2018 at 7:51 PM Jose Trujillo ce.autom(a)protonmail.com wrote: > > > Thank you Naresh, > > How to do the copy? > > Could you give me some details? > > You too have an excellent day. > > Jose. > > Sent with ProtonMail Secure Email. > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > On Monday, September 17, 2018 5:17 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > I guess the FSP version you have is 3.5.0 > > You should have received fsp header along with fsp binary in single package. > > However you can get FSP binaries and header from https://github.com/IntelFsp/FSP > > Also make sure you copy FSP header version equal fsp binary version. > > All the best! > > On Mon 17 Sep, 2018, 3:34 PM Jose Trujillo via coreboot, coreboot(a)coreboot.org wrote: > > > > > Dear Naresh: > > > You are right; it never returns from the FSP function (fsp_silicon_init). > > > chip_fsp20.c Ln.169 > > > void soc_init_pre_device(void chip_info) > > > { > > > printk(BIOS_INFO, "Entering: fsp_silicon_init"); // Added > > > / Perform silicon specific init. / > > > fsp_silicon_init(romstage_handoff_is_resume()); > > > / swap enabled PCI ports in device tree if needed */printk(BIOS_INFO, "Entering: pcie_override_devicetree"); // Added > > > pcie_override_devicetree_after_silicon_init(); > > > printk(BIOS_INFO, "Exit: soc_init_pre_device"); // Added > > > } > > > Serial dump. > > > .... > > > Enabling SMIs. > > > Locking SMM. > > > VMX : param.enable = 0 > > > VMX: pre-conditions not met > > > VMX: pre-conditions not met > > > VMX: pre-conditions not met > > > SGX: pre-conditions not met > > > VMX: pre-conditions not met > > > SGX: pre-conditions not met > > > POST: 0x71 > > > SGX: pre-conditions not met > > > SGX: pre-conditions not met > > > Entering: fsp_silicon_init <------ never returns from FSP. > > > .... > > > About the FSP header version I am not sure how exactly to obtain it but getting the binary decription from BCT I got: > > > Header Revision: 0x3 > > > Image Revision: 0x3050000 > > > 3.0.5 ???? > > > See the attached file for more details about the FSP binary. > > > Please advise. > > > Thank you, > > > Jose Trujillo. > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > On Friday, September 14, 2018 6:58 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > > > With available data. It is most likely that it might have stuck > > > > somewhere in function > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/ch… > > > > You can add printk in that function & other functions called by it to > > > > bisect & confirm the exact position of hang.. > > > > Also can you please check FSP binary version you are using versus FSP > > > > header version checked-out in coreboot(which is currently 2.9.2). > > > > They should be > > > > On Fri, Sep 14, 2018 at 7:55 PM Jose Trujillo via coreboot > > > > coreboot(a)coreboot.org wrote: > > > > > > > > > Here is Naresh.... > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > On Friday, September 14, 2018 4:49 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > Can you also provide latest complete log. > > > > > On Fri 14 Sep, 2018, 2:10 PM Jose Trujillo via coreboot, coreboot(a)coreboot.org wrote: > > > > > > > > > > > Thank you Naresh, > > > > > > I added the missing PCH device id following your advise, also enabled DEBUG_BOOT_STATE but I am still not able to get more information via serial debug about the exact location of the problem (but now I am certain is in the coreboot code not in FSP). > > > > > > I suspect the code involved aound this issue is hardwaremain.c and device.c.... > > > > > > Only the first "boot" just after flash I notice that the ethernet and SATA LEDs blink for a fraction of a second then reboots. > > > > > > After that, the following attempts to boot I don't see LED activity neither reboots, just halted in some kind of loop. > > > > > > According to the serial dump the las printed text is "0x71" but my question is if the serial port gets broken still during "BS_DEV_INIT_CHIPS" or is already doing "BS_DEV_ENUMERATE". > > > > > > As Naresh pointed my PCH H chipset "Kabylake-H HM175" was not added to the list; I added it but may be is needed to do something else to make it work. > > > > > > Or istill is misconfigured (attached my .config file for your review)... I someone has a similar system working and want to share its configuration files to compare them myself I will be grateful. > > > > > > Jose Trujillo. > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > On Wednesday, 12 September 2018 19:33, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > > Hi > > > > > > > > > > > > > PCH: device id a152 (rev 31) is Unknown > > > > > > > > > > > > This indicates that LPCID 0xa152 is not added. > > > > > > The #define should be added in source path: https://review.coreboot.org/cgit/coreboot.git/tree/src/include/device/pci_i… > > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/blo… > > > > > > & > > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/bo… > > > > > > as well. > > > > > > Additionally you can enable config DEBUG_BOOT_STATE to understand where exactly its stuck. > > > > > > Regards, > > > > > > Naresh G. Solanki > > > > > > On Wed, Sep 12, 2018 at 9:24 PM Jose Trujillo via coreboot coreboot(a)coreboot.org wrote: > > > > > > > > > > > > > Dear All, > > > > > > > About the memory I just changed the dimm to address A0 and now coreboot is reporting correctly 1 dimm detected. > > > > > > > But still no luck on the 0x71 post code loop (looks it is in some kind of loop because is still responsive to power and reset buttons). > > > > > > > I don't know where this loop could be located (coreboot or FSP). > > > > > > > The description on the post_codes.h file shows the following: > > > > > > > .... > > > > > > > /** > > > > > > > > > > > > > > - \brief Initializing Chips > > > > > > > - > > > > > > > - Boot State Machine: bs_dev_init_chips() > > > > > > > */ > > > > > > > #define POST_BS_DEV_INIT_CHIPS 0x71 > > > > > > > .... > > > > > > > > > > > > > > > > > > > > > Any advice on this issue? > > > > > > > Attached is the serial dump with extra information. > > > > > > > Thank you > > > > > > > Jose Trujillo > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > On Wednesday, 12 September 2018 16:12, Jose Trujillo ce.autom(a)protonmail.com wrote: > > > > > > > To begin with the system didn't find memory attached... > > > > > > > but there is memory attached, SPD address mismatch? I will check. > > > > > > > .... > > > > > > > .......Timeout while sending command 0x0d to EC! > > > > > > > recv_ec_data: 0xff > > > > > > > recv_ec_data: 0xff > > > > > > > SPD index 7 > > > > > > > No memory dimm at address A0 > > > > > > > No memory dimm at address A2 > > > > > > > No memory dimm at address A6 > > > > > > > .... > > > > > > > 0 DIMMs found > > > > > > > .... > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > On Wednesday, 12 September 2018 13:29, Jose Trujillo via coreboot coreboot(a)coreboot.org wrote: > > > > > > > Dear coreboot engineers: > > > > > > > Right now I am stuck with a Kabylake system with the following message: > > > > > > > .... > > > > > > > CPU #1 initialized > > > > > > > apic_id: 0x06 done. > > > > > > > microcode: updated to revision 0x8d date=2018-01-21 > > > > > > > CPU #3 initialized > > > > > > > bsp_do_flight_plan done after 220 msecs. > > > > > > > CPU: frequency set to 3600 MHz > > > > > > > Enabling SMIs. > > > > > > > Locking SMM. > > > > > > > VMX : param.enable = 0 > > > > > > > VMX: pre-conditions not met > > > > > > > SGX: pre-conditions not met > > > > > > > VMX: pre-conditions not met > > > > > > > VMX: pre-conditions not met > > > > > > > SGX: pre-conditions not met > > > > > > > SGX: pre-conditions not met > > > > > > > VMX: pre-conditions not met > > > > > > > SGX: pre-conditions not met > > > > > > > POST: 0x71 > > > > > > > .... > > > > > > > May be some configuration is missing and I am trying to find this out myself but if someone of you can give a hint on how to resolve it I will be grateful. > > > > > > > Attached is the full serial dump. > > > > > > > Thank you, > > > > > > > Jose Trujillo > > > > > > > > > > > > > > ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- > > > > > > > > > > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > > > > > -- > > > > > > Best regards, > > > > > > Naresh G. Solanki > > > > > > > > > > > > ----------------------------------- > > > > > > > > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > > > -- > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > -- > > > > Best regards, > > > > Naresh G. Solanki > > > > > > -- > > > coreboot mailing list: coreboot(a)coreboot.org > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > -- > > Best regards, > Naresh G. Solanki

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UEFI Payload update
by You, Benjamin 18 Sep '18

18 Sep '18

Hi, A staging project "UEFIPayload" has been started to upgrade the Coreboot*Pkgs in EDK II repository. The new features are: - Supporting Slim Bootloader (https://github.com/slimbootloader) in addition to Coreboot - Source file configuration using .ini format - User extension using simple "C" libs - Platform supporting lib The link of this project is: https://github.com/tianocore/edk2-staging/tree/UEFIPayload Thanks, - ben

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Coreboot for Apollolake
by Antony AbeePrakash X V 17 Sep '18

17 Sep '18

Hi, We would like to build coreboot image for Apollo lake platform. We are using * Coreboot-4.8.1 * Apollo lake Intel FSP_2_0 We have built the coreboot source and created coreboot.rom image with the below warning message: ** WARNING ** coreboot will be built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region. Is the coreboot.rom image is enough to flash ? Could you please provide feedback on this ? Thanks & Regards, Antony L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] Kabylake unable to boot with post code 0x71
by Naresh G. Solanki 17 Sep '18

17 Sep '18

I guess the FSP version you have is 3.5.0 You should have received fsp header along with fsp binary in single package. However you can get FSP binaries and header from https://github.com/IntelFsp/FSP Also make sure you copy FSP header version equal fsp binary version. All the best! On Mon 17 Sep, 2018, 3:34 PM Jose Trujillo via coreboot, < coreboot(a)coreboot.org> wrote: > Dear Naresh: > > You are right; it never returns from the FSP function (fsp_silicon_init). > > chip_fsp20.c Ln.169 > > void soc_init_pre_device(void *chip_info) > { > printk(BIOS_INFO, "Entering: fsp_silicon_init"); // > Added > /* Perform silicon specific init. */ > fsp_silicon_init(romstage_handoff_is_resume()); > /* swap enabled PCI ports in device tree if needed */ > printk(BIOS_INFO, "Entering: pcie_override_devicetree"); // > Added > pcie_override_devicetree_after_silicon_init(); > printk(BIOS_INFO, "Exit: soc_init_pre_device"); // > Added > } > > Serial dump. > .... > Enabling SMIs. > Locking SMM. > VMX : param.enable = 0 > VMX: pre-conditions not met > VMX: pre-conditions not met > VMX: pre-conditions not met > SGX: pre-conditions not met > VMX: pre-conditions not met > SGX: pre-conditions not met > POST: 0x71 > SGX: pre-conditions not met > SGX: pre-conditions not met > Entering: fsp_silicon_init <------ never returns from FSP. > .... > > About the FSP header version I am not sure how exactly to obtain it but > getting the binary decription from BCT I got: > > Header Revision: 0x3 > Image Revision: 0x3050000 > > 3.0.5 ???? > > See the attached file for more details about the FSP binary. > > Please advise. > > Thank you, > Jose Trujillo. > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > On Friday, September 14, 2018 6:58 PM, Naresh G. Solanki < > naresh.solanki.2011(a)gmail.com> wrote: > > > With available data. It is most likely that it might have stuck > > somewhere in function > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/ch… > > You can add printk in that function & other functions called by it to > > bisect & confirm the exact position of hang.. > > Also can you please check FSP binary version you are using versus FSP > > header version checked-out in coreboot(which is currently 2.9.2). > > They should be > > > > On Fri, Sep 14, 2018 at 7:55 PM Jose Trujillo via coreboot > > coreboot(a)coreboot.org wrote: > > > > > Here is Naresh.... > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > On Friday, September 14, 2018 4:49 PM, Naresh G. Solanki > naresh.solanki.2011(a)gmail.com wrote: > > > Can you also provide latest complete log. > > > On Fri 14 Sep, 2018, 2:10 PM Jose Trujillo via coreboot, > coreboot(a)coreboot.org wrote: > > > > > > > Thank you Naresh, > > > > I added the missing PCH device id following your advise, also > enabled DEBUG_BOOT_STATE but I am still not able to get more information > via serial debug about the exact location of the problem (but now I am > certain is in the coreboot code not in FSP). > > > > I suspect the code involved aound this issue is hardwaremain.c and > device.c.... > > > > Only the first "boot" just after flash I notice that the ethernet > and SATA LEDs blink for a fraction of a second then reboots. > > > > After that, the following attempts to boot I don't see LED activity > neither reboots, just halted in some kind of loop. > > > > According to the serial dump the las printed text is "0x71" but my > question is if the serial port gets broken still during "BS_DEV_INIT_CHIPS" > or is already doing "BS_DEV_ENUMERATE". > > > > As Naresh pointed my PCH H chipset "Kabylake-H HM175" was not added > to the list; I added it but may be is needed to do something else to make > it work. > > > > Or istill is misconfigured (attached my .config file for your > review)... I someone has a similar system working and want to share its > configuration files to compare them myself I will be grateful. > > > > Jose Trujillo. > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > On Wednesday, 12 September 2018 19:33, Naresh G. Solanki > naresh.solanki.2011(a)gmail.com wrote: > > > > Hi > > > > > > > > > PCH: device id a152 (rev 31) is Unknown > > > > > > > > This indicates that LPCID 0xa152 is not added. > > > > The #define should be added in source path: > https://review.coreboot.org/cgit/coreboot.git/tree/src/include/device/pci_i… > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/blo… > > > > & > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/bo… > > > > as well. > > > > Additionally you can enable config DEBUG_BOOT_STATE to understand > where exactly its stuck. > > > > Regards, > > > > Naresh G. Solanki > > > > On Wed, Sep 12, 2018 at 9:24 PM Jose Trujillo via coreboot > coreboot(a)coreboot.org wrote: > > > > > > > > > Dear All, > > > > > About the memory I just changed the dimm to address A0 and now > coreboot is reporting correctly 1 dimm detected. > > > > > But still no luck on the 0x71 post code loop (looks it is in some > kind of loop because is still responsive to power and reset buttons). > > > > > I don't know where this loop could be located (coreboot or FSP). > > > > > The description on the post_codes.h file shows the following: > > > > > .... > > > > > /** > > > > > > > > > > - \brief Initializing Chips > > > > > - > > > > > - Boot State Machine: bs_dev_init_chips() > > > > > */ > > > > > #define POST_BS_DEV_INIT_CHIPS 0x71 > > > > > .... > > > > > > > > > > > > > > > Any advice on this issue? > > > > > Attached is the serial dump with extra information. > > > > > Thank you > > > > > Jose Trujillo > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > On Wednesday, 12 September 2018 16:12, Jose Trujillo > ce.autom(a)protonmail.com wrote: > > > > > To begin with the system didn't find memory attached... > > > > > but there is memory attached, SPD address mismatch? I will check. > > > > > .... > > > > > .......Timeout while sending command 0x0d to EC! > > > > > recv_ec_data: 0xff > > > > > recv_ec_data: 0xff > > > > > SPD index 7 > > > > > No memory dimm at address A0 > > > > > No memory dimm at address A2 > > > > > No memory dimm at address A6 > > > > > .... > > > > > 0 DIMMs found > > > > > .... > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > On Wednesday, 12 September 2018 13:29, Jose Trujillo via coreboot > coreboot(a)coreboot.org wrote: > > > > > Dear coreboot engineers: > > > > > Right now I am stuck with a Kabylake system with the following > message: > > > > > .... > > > > > CPU #1 initialized > > > > > apic_id: 0x06 done. > > > > > microcode: updated to revision 0x8d date=2018-01-21 > > > > > CPU #3 initialized > > > > > bsp_do_flight_plan done after 220 msecs. > > > > > CPU: frequency set to 3600 MHz > > > > > Enabling SMIs. > > > > > Locking SMM. > > > > > VMX : param.enable = 0 > > > > > VMX: pre-conditions not met > > > > > SGX: pre-conditions not met > > > > > VMX: pre-conditions not met > > > > > VMX: pre-conditions not met > > > > > SGX: pre-conditions not met > > > > > SGX: pre-conditions not met > > > > > VMX: pre-conditions not met > > > > > SGX: pre-conditions not met > > > > > POST: 0x71 > > > > > .... > > > > > May be some configuration is missing and I am trying to find this > out myself but if someone of you can give a hint on how to resolve it I > will be grateful. > > > > > Attached is the full serial dump. > > > > > Thank you, > > > > > Jose Trujillo > > > > > -- > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > -- > > > > Best regards, > > > > Naresh G. Solanki > > > > -- > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > -- > > > coreboot mailing list: coreboot(a)coreboot.org > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > -- > > > > Best regards, > > Naresh G. Solanki > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Divide Error in Tianocore payload
by Jorge Fernandez Monteagudo 17 Sep '18

17 Sep '18

Hi, Finally I've been able to make it works. Video modes not supported all returns the line VBE: resolution: 0x0@0 With the SeaBIOS I've seen some code to list all the supported modes (see src/bootsplash.c 'find_videomode' function) and the needed one is 0x122, 800x600x32 corresponding to an unmapped mode, then I've compiled coreboot with the entries: CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x122 Regards ________________________________ De: coreboot <coreboot-bounces(a)coreboot.org> en nombre de Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com> Enviado: jueves, 6 de septiembre de 2018 8:44:57 Para: coreboot(a)coreboot.org Asunto: Re: [coreboot] Divide Error in Tianocore payload More info from traces. In the correct mode I see VBE: Getting information about VESA mode 4114 VBE: resolution: 800x600@16 VBE: framebuffer: e0000000 VBE: Setting VESA mode 4114 VGA Option ROM was run and in the non working: VBE: Getting information about VESA mode 4115 VBE: resolution: 0x0@0 VBE: framebuffer: e0000000 VBE: Setting VESA mode 4115 VGA Option ROM was run ________________________________ De: coreboot <coreboot-bounces(a)coreboot.org> en nombre de Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com> Enviado: jueves, 6 de septiembre de 2018 8:02:15 Para: coreboot(a)coreboot.org Asunto: [coreboot] Divide Error in Tianocore payload Hi, I'm debugging an problem I have with coreboot & tianocore payload. I'm using ae05d095b36ac835a6b1a221e6858065e5486888 commit from Tue May 8 17:09:57 2018 My board is an AMD Bettong. The options enabled to set the video mode: CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_VBE_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y Configuring 800x600 64k-color (5:6:5) CONFIG_FRAMEBUFFER_VESA_MODE_114=y CONFIG_FRAMEBUFFER_VESA_MODE=0x114 the video mode is set ok but using 800x600 16.8M-color (8:8:8) CONFIG_FRAMEBUFFER_VESA_MODE_115=y CONFIG_FRAMEBUFFER_VESA_MODE=0x115 I get !!!! X64 Exception Type - 00(#DE - Divide Error) CPU Apic ID - 00000010 !!!! RIP - 000000008F5A2EC4, CS - 0000000000000038, RFLAGS - 0000000000010246 RAX - 0000000000000000, RCX - 000000008F58D618, RDX - 0000000000000000 RBX - 000000008F593A98, RSP - 000000008FDA7700, RBP - 0000000000000000 RSI - 000000008F58CF98, RDI - 0000000000000000 R8 - 0000000000000000, R9 - 000000008F5A3A3F, R10 - FFFFFFFF70A73180 R11 - 000000008FDC3F88, R12 - 0000000000000000, R13 - 000000008F58CF18 R14 - 000000008FA32EA0, R15 - 000000008F58D518 DS - 0000000000000030, ES - 0000000000000030, FS - 0000000000000030 GS - 0000000000000030, SS - 0000000000000030 CR0 - 0000000080000011, CR2 - 0000000000000000, CR3 - 000000008FB87000 CR4 - 0000000000000628, CR8 - 0000000000000000 DR0 - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000 DR3 - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400 GDTR - 000000008FB73F98 0000000000000047, LDTR - 0000000000000000 IDTR - 000000008F903018 0000000000000FFF, TR - 0000000000000000 FXSAVE_STATE - 000000008FDA7360 !!!! Find PE image /mnt/develop/bettong/coreboot/master/coreboot_tiano/payloads/external/tianocore/tianocore/Build/CorebootPayloadPkgX64/RELEASE_COREBOOT/X64/CorebootPayloadPkg/FbGop/FbGop/DEBUG/FbGop.dll (Im! I've set some traces in src/lib/coreboot_table.c in static void lb_framebuffer(struct lb_header *header) { ... if (!IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb)) return; printk(BIOS_INFO, "-->> lb_framebuffer: %lld - %dx%d bpl %d bpp %d r %d:%d g %d:%d b %d:%d res %d:%d\n", fb.physical_address, fb.x_resolution, fb.y_resolution, fb.bytes_per_line, fb.bits_per_pixel, fb.red_mask_pos, fb.red_mask_size, fb.green_mask_pos, fb.green_mask_size, fb.blue_mask_pos, fb.blue_mask_size, fb.reserved_mask_pos, fb.reserved_mask_size ); to see in console that when is correct -->> lb_framebuffer: 3758096384 - 800x600 bpl 1664 bpp 16 r 11:5 g 5:6 b 0:5 res 0:0 but when the exception is produced: -->> lb_framebuffer: 3758096384 - 0x0 bpl 0 bpp 0 r 0:0 g 0:0 b 0:0 res 0:0 Maybe some problem computing the values from mode? Regards

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coreboot September 2018