coreboot September 2018

coreboot@coreboot.org

59 participants
160 discussions

Re: [coreboot] T450S + Coreboot
by Peter Stuge 10 Sep '18

10 Sep '18

Youness Alaoui wrote: > So, back to the ME, we know exactly what it does, it's all extremely > well documented and explained I disagree with this. It is absolutely true that *some* of what the ME does is extremely well documented and explained by the vendor, web services APIs and all, but I would argue that in fact *most* of what the ME does is *not* documented by the vendor, nor by independent research. Since the ME is colocated with the x86 VM host, has access to all x86 VM memory *and* is a proprietary machine or subsystem I actually don't believe that we will ever "know exactly what it does". > Now the problem is that it's closed source, and not user controlled Right. //Peter

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MRC saving for apollolake
by Antony AbeePrakash X V 10 Sep '18

10 Sep '18

Hi, We are developing coreboot for Apollo lake custom board. We would like to reduce the boot time. For this, * Enabled "MRC training data save" in FSP2_0 using Binary configuration tool. But we are receiving the following logs: NVM Write Failed. Update is lost. If repeatedly encountered, clear GPP4 and try again Saved MRC training data with status (0x80000007) We would like to get clarification for the following: 1. Can we cache and save MRC training data for Apollo lake platform ? 2. Will it be done through CSE using HECI interface or through the SPI read/write operation in the NVRAM ? 3. Do we need to add Mrc.bin file with coreboot? If yes, where can we get the same ? Thanks & Regards, Antony L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] T450S + Coreboot
by awokd 06 Sep '18

06 Sep '18

On Wed, August 29, 2018 9:41 pm, Youness Alaoui wrote: > > We're about to get full control back of the ME. I've been working for > the past few weeks on reproducing the PTResearch buffer overflow exploit on > the ME, and yesterday they released a PoC for Apollolake (in case you > missed it : https://github.com/ptresearch/IntelTXE-PoC), so with the > progress I made and with that, I should be able to soon port it to skylake > (and write docs on how to port to other platforms > as well) which will at least give us the ability to gain back the > 'user-controlled' aspect of it as we'd have code execution on it. > Which by the way, also means that BootGuard can be disabled (since the > ME is the one checking for the boot guard signatures), which should > enable the ability to port coreboot to a lot more machines (including the > T450S that this thread is supposed to be about). Hopefully.... Look forward to this. Would be good to regain control of parts I paid good money for.

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Re: [coreboot] Divide Error in Tianocore payload
by Jorge Fernandez Monteagudo 06 Sep '18

06 Sep '18

More info from traces. In the correct mode I see VBE: Getting information about VESA mode 4114 VBE: resolution: 800x600@16 VBE: framebuffer: e0000000 VBE: Setting VESA mode 4114 VGA Option ROM was run and in the non working: VBE: Getting information about VESA mode 4115 VBE: resolution: 0x0@0 VBE: framebuffer: e0000000 VBE: Setting VESA mode 4115 VGA Option ROM was run ________________________________ De: coreboot <coreboot-bounces(a)coreboot.org> en nombre de Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com> Enviado: jueves, 6 de septiembre de 2018 8:02:15 Para: coreboot(a)coreboot.org Asunto: [coreboot] Divide Error in Tianocore payload Hi, I'm debugging an problem I have with coreboot & tianocore payload. I'm using ae05d095b36ac835a6b1a221e6858065e5486888 commit from Tue May 8 17:09:57 2018 My board is an AMD Bettong. The options enabled to set the video mode: CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_VBE_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y Configuring 800x600 64k-color (5:6:5) CONFIG_FRAMEBUFFER_VESA_MODE_114=y CONFIG_FRAMEBUFFER_VESA_MODE=0x114 the video mode is set ok but using 800x600 16.8M-color (8:8:8) CONFIG_FRAMEBUFFER_VESA_MODE_115=y CONFIG_FRAMEBUFFER_VESA_MODE=0x115 I get !!!! X64 Exception Type - 00(#DE - Divide Error) CPU Apic ID - 00000010 !!!! RIP - 000000008F5A2EC4, CS - 0000000000000038, RFLAGS - 0000000000010246 RAX - 0000000000000000, RCX - 000000008F58D618, RDX - 0000000000000000 RBX - 000000008F593A98, RSP - 000000008FDA7700, RBP - 0000000000000000 RSI - 000000008F58CF98, RDI - 0000000000000000 R8 - 0000000000000000, R9 - 000000008F5A3A3F, R10 - FFFFFFFF70A73180 R11 - 000000008FDC3F88, R12 - 0000000000000000, R13 - 000000008F58CF18 R14 - 000000008FA32EA0, R15 - 000000008F58D518 DS - 0000000000000030, ES - 0000000000000030, FS - 0000000000000030 GS - 0000000000000030, SS - 0000000000000030 CR0 - 0000000080000011, CR2 - 0000000000000000, CR3 - 000000008FB87000 CR4 - 0000000000000628, CR8 - 0000000000000000 DR0 - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000 DR3 - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400 GDTR - 000000008FB73F98 0000000000000047, LDTR - 0000000000000000 IDTR - 000000008F903018 0000000000000FFF, TR - 0000000000000000 FXSAVE_STATE - 000000008FDA7360 !!!! Find PE image /mnt/develop/bettong/coreboot/master/coreboot_tiano/payloads/external/tianocore/tianocore/Build/CorebootPayloadPkgX64/RELEASE_COREBOOT/X64/CorebootPayloadPkg/FbGop/FbGop/DEBUG/FbGop.dll (Im! I've set some traces in src/lib/coreboot_table.c in static void lb_framebuffer(struct lb_header *header) { ... if (!IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb)) return; printk(BIOS_INFO, "-->> lb_framebuffer: %lld - %dx%d bpl %d bpp %d r %d:%d g %d:%d b %d:%d res %d:%d\n", fb.physical_address, fb.x_resolution, fb.y_resolution, fb.bytes_per_line, fb.bits_per_pixel, fb.red_mask_pos, fb.red_mask_size, fb.green_mask_pos, fb.green_mask_size, fb.blue_mask_pos, fb.blue_mask_size, fb.reserved_mask_pos, fb.reserved_mask_size ); to see in console that when is correct -->> lb_framebuffer: 3758096384 - 800x600 bpl 1664 bpp 16 r 11:5 g 5:6 b 0:5 res 0:0 but when the exception is produced: -->> lb_framebuffer: 3758096384 - 0x0 bpl 0 bpp 0 r 0:0 g 0:0 b 0:0 res 0:0 Maybe some problem computing the values from mode? Regards

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Divide Error in Tianocore payload
by Jorge Fernandez Monteagudo 06 Sep '18

06 Sep '18

Hi, I'm debugging an problem I have with coreboot & tianocore payload. I'm using ae05d095b36ac835a6b1a221e6858065e5486888 commit from Tue May 8 17:09:57 2018 My board is an AMD Bettong. The options enabled to set the video mode: CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_VBE_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y Configuring 800x600 64k-color (5:6:5) CONFIG_FRAMEBUFFER_VESA_MODE_114=y CONFIG_FRAMEBUFFER_VESA_MODE=0x114 the video mode is set ok but using 800x600 16.8M-color (8:8:8) CONFIG_FRAMEBUFFER_VESA_MODE_115=y CONFIG_FRAMEBUFFER_VESA_MODE=0x115 I get !!!! X64 Exception Type - 00(#DE - Divide Error) CPU Apic ID - 00000010 !!!! RIP - 000000008F5A2EC4, CS - 0000000000000038, RFLAGS - 0000000000010246 RAX - 0000000000000000, RCX - 000000008F58D618, RDX - 0000000000000000 RBX - 000000008F593A98, RSP - 000000008FDA7700, RBP - 0000000000000000 RSI - 000000008F58CF98, RDI - 0000000000000000 R8 - 0000000000000000, R9 - 000000008F5A3A3F, R10 - FFFFFFFF70A73180 R11 - 000000008FDC3F88, R12 - 0000000000000000, R13 - 000000008F58CF18 R14 - 000000008FA32EA0, R15 - 000000008F58D518 DS - 0000000000000030, ES - 0000000000000030, FS - 0000000000000030 GS - 0000000000000030, SS - 0000000000000030 CR0 - 0000000080000011, CR2 - 0000000000000000, CR3 - 000000008FB87000 CR4 - 0000000000000628, CR8 - 0000000000000000 DR0 - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000 DR3 - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400 GDTR - 000000008FB73F98 0000000000000047, LDTR - 0000000000000000 IDTR - 000000008F903018 0000000000000FFF, TR - 0000000000000000 FXSAVE_STATE - 000000008FDA7360 !!!! Find PE image /mnt/develop/bettong/coreboot/master/coreboot_tiano/payloads/external/tianocore/tianocore/Build/CorebootPayloadPkgX64/RELEASE_COREBOOT/X64/CorebootPayloadPkg/FbGop/FbGop/DEBUG/FbGop.dll (Im! I've set some traces in src/lib/coreboot_table.c in static void lb_framebuffer(struct lb_header *header) { ... if (!IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb)) return; printk(BIOS_INFO, "-->> lb_framebuffer: %lld - %dx%d bpl %d bpp %d r %d:%d g %d:%d b %d:%d res %d:%d\n", fb.physical_address, fb.x_resolution, fb.y_resolution, fb.bytes_per_line, fb.bits_per_pixel, fb.red_mask_pos, fb.red_mask_size, fb.green_mask_pos, fb.green_mask_size, fb.blue_mask_pos, fb.blue_mask_size, fb.reserved_mask_pos, fb.reserved_mask_size ); to see in console that when is correct -->> lb_framebuffer: 3758096384 - 800x600 bpl 1664 bpp 16 r 11:5 g 5:6 b 0:5 res 0:0 but when the exception is produced: -->> lb_framebuffer: 3758096384 - 0x0 bpl 0 bpp 0 r 0:0 g 0:0 b 0:0 res 0:0 Maybe some problem computing the values from mode? Regards

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Cannot commit code because of "Verify that the word 'coreboot' is lowercase" from an unrelated file
by Josh Cofreros 06 Sep '18

06 Sep '18

Good day! I'm Josh. This will be my first time contributing so please bear with me. I am making a simple change on one of the header files and while following the guidelines on committing I get the error below. It is pointing to a Quark SoC documentation that I have never touched. I have pulled the latest master and still I am seeing this. It is not even related to what I am changing. Can you please advise on how I can proceed with this? Many thanks, Josh josh@ubuntu1604vm:~/Documents/coreboot$ git commit Check that files have license headers (lint-stable-000-license-headers): success Check for superfluous whitespace in the tree (lint-stable-003-whitespace): success Check that C labels begin at start-of-line (lint-stable-004-style-labels): success Check that every board has a meaningful board_info.txt (lint-stable-005-board-status): success Check that every vendor and board has a Kconfig.name (lint-stable-006-board-name): success check Kconfig files for errors (lint-stable-008-kconfig): success verify that files don't have the old style header (lint-stable-009-old-licenses): success Check that we use a single assembler syntax (lint-stable-010-asm-syntax): success Check that source files are not executable (lint-stable-012-executable-bit): success Verify that site-local is not in the coreboot repository (lint-stable-013-site-local): success Check for non-ASCII and unprintable characters (lint-stable-016-non-ascii): success Check that saved config files are miniconfigs (lint-stable-017-configs): success Report any symbolic links (lint-stable-018-symlinks): success Check for auto-included headers (lint-stable-019-header-files): success Verify that the word 'coreboot' is lowercase (lint-stable-021-coreboot-lowercase): Documentation/Intel/SoC/quark.html:22: <li><a target="_blank" href="#CorebootPayloadPkg">CorebootPayloadPkg</a></li> Documentation/Intel/SoC/quark.html:52:<h2><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h2> Documentation/Intel/SoC/quark.html:59:<pre><code>build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -a IA32 \ Documentation/Intel/SoC/quark.html:63:ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd Documentation/Intel/SoC/quark.html:67:<pre><code>build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -a IA32 -t VS2015x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL -DMAX_LOGICAL_PROCESSORS=1 Documentation/Intel/SoC/quark.html:68:dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd Documentation/Intel/SoC/soc.html:575: One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. Documentation/Intel/SoC/soc.html:581: CorebootModulePkg/Library/CbParseLib/<a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbP… ">CbParseLib.c</a> Documentation/Intel/SoC/soc.html:584: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootMod… ">gUefiAcpiBoardInfoGuid</a> Documentation/Intel/SoC/soc.html:586: CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPe… ">CbPeiEntryPoint</a>. Documentation/Intel/SoC/soc.html:603: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbP… ">PmGpeEnBase</a> Documentation/Intel/SoC/soc.html:605: <td><a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re… ">Shutdown</a></td> Documentation/Intel/SoC/soc.html:613: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re… ">Shutdown</a><br> Documentation/Intel/SoC/soc.html:614: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re… ">Suspend</a> Documentation/Intel/SoC/soc.html:622: <td><a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re… ">Shutdown</a></td> Documentation/Intel/SoC/soc.html:630: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Ac… ">Timer</a> Documentation/Intel/SoC/soc.html:639: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re… ">Cold</a> Documentation/Intel/SoC/soc.html:641: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re… ">Warm</a> Documentation/Intel/SoC/soc.html:651: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re… ">Cold</a> Documentation/Intel/SoC/soc.html:653: <a target="_blank" href=" https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re… ">Warm</a> Documentation/Intel/SoC/soc.html:683: One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. Documentation/Intel/development.html:153: <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> Documentation/Intel/development.html:158: <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> Documentation/Intel/index.html:13: <li><a target="_blank" href=" http://wiki.minnowboard.org/Coreboot">MinnowBoard MAX</a></li> Documentation/Intel/index.html:40: <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> test failed Check for illegal characters in filename (lint-stable-023-filenames): success ERROR: 1 test(s) failed. util/testing/Makefile.inc:82: recipe for target 'lint-stable' failed make: *** [lint-stable] Error 1 josh@ubuntu1604vm:~/Documents/coreboot$ git status On branch master Your branch is up-to-date with 'origin/master'. Changes to be committed: (use "git reset HEAD <file>..." to unstage) modified: src/mainboard/intel/leafhill/brd_gpio.h Untracked files: (use "git add <file>..." to include in what will be committed) coreboot_leafhill.patch josh@ubuntu1604vm:~/Documents/coreboot$

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Re: [coreboot] MRC in coreboot
by Aaron Durbin 05 Sep '18

05 Sep '18

On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > Hi, > > > > We are developing coreboot for Apollo lake custom board. MRC training data save is enabled in FSP using Binary configuration tool. > > > > But we are getting logs like, > > > > No MRC cache found. > > MRC SeCUmaSize memory size from SeC ... 0 > > MRC Parameters not valid. Status is Success > > MRC:CpuMemoryTest Successful! > > Saving MRC data using CSE through HECI interface I have never seen this path used in coreboot. This line above is saying CSE is responsible for saving and retrieving training data. In coreboot we use the main processor to save and restore. I suggest reading over the UPD parameters and ensure they match with our typical use cases. BCT tool enabling 'training data save' sounds like it's enabling CSE path. > > Try to find MRC training data HOB. > > No MRC training data found, perform data save via HECI. > > Saved MRC training data with status (0x80000003) > > > > It seems that MRC data is not found and saved. Also I found that there are options to add MRC file path and mrc.bin in menuconfig. The only option I have is save cached MRC settings. > > > > What this mrc.bin will do? > > How to add the mrc.bin in coreboot? > > > > Please explain on this. > > > > Thanks & Regards, > > Antony > > > > L&T Technology Services Ltd > > www.LntTechservices.com > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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MRC in coreboot
by Antony AbeePrakash X V 05 Sep '18

05 Sep '18

Hi, We are developing coreboot for Apollo lake custom board. MRC training data save is enabled in FSP using Binary configuration tool. But we are getting logs like, No MRC cache found. MRC SeCUmaSize memory size from SeC ... 0 MRC Parameters not valid. Status is Success MRC:CpuMemoryTest Successful! Saving MRC data using CSE through HECI interface Try to find MRC training data HOB. No MRC training data found, perform data save via HECI. Saved MRC training data with status (0x80000003) It seems that MRC data is not found and saved. Also I found that there are options to add MRC file path and mrc.bin in menuconfig. The only option I have is save cached MRC settings. What this mrc.bin will do? How to add the mrc.bin in coreboot? Please explain on this. Thanks & Regards, Antony L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] Intel ME what is it? And when did this dangerous thing get installed?
by Philipp Stanner 05 Sep '18

05 Sep '18

Am Mittwoch, den 29.08.2018, 04:09 -0400 schrieb Youness Alaoui: > If there are more specific questions that you have, ask them and I > might be able to answer them! I might have one: What does stop a motherboard-vendor from just buying a CPU and implementing it? Which chips, beside the CPU, do you need from Intel in any case to make the machine work? I always thought of the CPU just as a machine executing code, and assumed it's possible to use it just as any microcontroller: You can add the ME-Chipset, but you don't have to. Philipp

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Re: [coreboot] APIC and lspci
by Nico Huber 04 Sep '18

04 Sep '18

Hi Hilbert, On 03.09.2018 12:36, Hilbert Tu(杜睿哲_Pegatron) wrote: > I have a customized Intel Denverton-NS platform similar like Harcuvar > CRB. In dmesg, I can see following: > [ 10.973387] ACPI: PCI Interrupt Link [LNKA] (IRQs 6 7 10 *11 12 14 15) > [ 10.981587] ACPI: PCI Interrupt Link [LNKB] (IRQs 6 7 *10 11 12 14 15) > [ 10.989776] ACPI: PCI Interrupt Link [LNKC] (IRQs *6 7 10 11 12 14 15) > [ 10.997961] ACPI: PCI Interrupt Link [LNKD] (IRQs 6 *7 10 11 12 14 15) > [ 11.006147] ACPI: PCI Interrupt Link [LNKE] (IRQs 6 7 10 11 *12 14 15) > [ 11.014332] ACPI: PCI Interrupt Link [LNKF] (IRQs 6 7 10 11 12 *14 15) > [ 11.022518] ACPI: PCI Interrupt Link [LNKG] (IRQs 6 7 10 11 12 14 *15) > [ 11.030697] ACPI: PCI Interrupt Link [LNKH] (IRQs 6 7 10 11 12 14 *15) > And by “lspci -s 00:14.0 -vv”, there is a message “Interrupt: pin A > routed to IRQ 28”. Actually I know in the devicetree.cb, the device 14’s > interrupt is configured by IR08 which routes INTA to PIRQE and LNKE is > using IRQ12. This is the legacy interrupt mode as kernel message dumped. > But in ACPI mode, why does lspci report IRQ28 and how to reconfigure it > in Coreboot? Please help to clarify. Thanks. there is actually a third case, MSI interrupts. It's hard to tell if that is used without seeing the lspci output. MSIs are configured by the OS, not coreboot. In APIC mode, there is likely a 1:1 mapping of the PIRQ LNK* to APIC IRQs; e.g. LNKA -> 16, LNKB -> 17, ..., LNKH -> 23 (this usually can't be changed, but I don't know for sure if that is the case for Denver- ton). It should be documented in the BIOS Writer's Guide for your SoC. Nico

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coreboot September 2018