coreboot September 2018

coreboot@coreboot.org

59 participants
160 discussions

Re: [coreboot] Coreboot for Apollolake
by Antony AbeePrakash X V 20 Sep '18

20 Sep '18

Hi All, Thanks for the response , we extracted the flash descriptor from the BIOS Image using the ifdtool as below ./ifdtool -x ~/<BIOS_IMAGE>.bin Peculiar firmware descriptor, assuming Ibex Peak compatibility. Flash Region 0 (Flash Descriptor): 00000000 - 00000fff Flash Region 1 (BIOS): 00001000 - 00efefff Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused) Flash Region 3 (GbE): 07fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) Flash Region 5 (Reserved): 00eff000 - 00ffefff Flash Region 6 (Reserved): 07fff000 - 00000fff (unused) Flash Region 7 (Reserved): 07fff000 - 00000fff (unused) Flash Region 8 (EC): 07fff000 - 00000fff (unused) when we compile the core boot with the Flash Descriptor , we are getting the below error CBFS fallback/postcar CBFS fallback/dsdt.aml CBFS fallback/payload DD Adding Intel Firmware Descriptor IFDTOOL Unlocking Management Engine Platform is: aplk File build/coreboot.pre is 2097152 bytes Peculiar firmware descriptor, assuming Ibex Peak compatibility. Writing new image to build/coreboot.pre.new CBFS coreboot.rom CBFSLAYOUT coreboot.rom This is a legacy image composed entirely of a single CBFS. make: *** [build/coreboot.rom] Error 1 make: *** Deleting file `build/coreboot.rom' Could you please point out where it went wrong , have we missed something Thanks & Regards, Antony From: David Hendricks [mailto:david.hendricks@gmail.com] Sent: Tuesday, September 18, 2018 8:48 PM To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> Cc: Coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] Coreboot for Apollolake Hi Antony, There are a few components which compose a complete firmware image for Intel platforms: coreboot, FSP, microcode, management engine blob, and flash descriptor are the most common ones. For the flash descriptor, refer to the Apollo Lake SoC SPI and signed Master Image Profile (SMIP) Programming Guide, docid 559702. Chapter 4 explains the flash descriptor for Apollo Lake in detail. Once you have created a flash descriptor, you can add it to the firmware image using coreboot's config system (under "Chipset"). On Tue, Sep 18, 2018 at 1:43 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com<mailto:AntonyAbee.PrakashXV@lnttechservices.com>> wrote: Hi, We would like to build coreboot image for Apollo lake platform. We are using * Coreboot-4.8.1 * Apollo lake Intel FSP_2_0 We have built the coreboot source and created coreboot.rom image with the below warning message: ** WARNING ** coreboot will be built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region. Is the coreboot.rom image is enough to flash ? Could you please provide feedback on this ? Thanks & Regards, Antony L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] Tianocore and TPM
by Jorge Fernandez Monteagudo 20 Sep '18

20 Sep '18

Hi Ben! Thanks for the info! I have one question. Have I to implement a CustomizationSample/Boards for my board? With the current tianocore payload I don't have to implement nothing to have a working UEFI... Thanks! Jorge ________________________________ De: You, Benjamin <benjamin.you(a)intel.com> Enviado: jueves, 20 de septiembre de 2018 3:42:33 Para: Jorge Fernandez Monteagudo; coreboot(a)coreboot.org Asunto: RE: Tianocore and TPM Hi, Another note is on the use of NULL|UefiPayloadPkg/Library/Tpm2InstanceLib/Tpm2InstanceLib.inf. This lib is not fully populated right now. Please consider using NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf depending on your needs. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of You, Benjamin Sent: Thursday, September 20, 2018 8:44 AM To: Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com>; coreboot(a)coreboot.org Subject: Re: [coreboot] Tianocore and TPM Hi Jorge, The staging UEFI Payload project (https://github.com/tianocore/edk2-staging/tree/UEFIPayload) has TPM support (although turned off by default, and using "FTPM" as the name (which needs to be fixed)). Please have a look at UefiPayloadPkgIA32X64.dsc for the components under tag "$(FTPM_ENABLE)". These components mainly do the measuring of firmware components and log the results. Also there is parsing logic in Library/PlatformInfoParseLib/ParseLib.c that parses TPM info in ACPI table passed from Coreboot. (This logic hasn't been sufficiently verified as this is still a "staging" project). You might have a try. Please let us know if you see any bugs / problems in these. You might also use the EDKII mailing list for discussing issues with the UEFI Payload. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Jorge Fernandez Monteagudo Sent: Wednesday, September 19, 2018 5:24 PM To: coreboot(a)coreboot.org Subject: [coreboot] Tianocore and TPM Hi all! I'm trying to enable the TPM2 support in the tianocore payload. The TPM2 device is working, because I've enabled the DEBUG_TPM and coreboot reports is up. I guess that I have to modify the 'CorebootPayloadPkgIa32X64.dsc' file to enable the TPM support but there are so many dependencies. Anybody has a working tianocore payload with TPM? Thanks!

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Re: [coreboot] Tianocore and TPM
by You, Benjamin 20 Sep '18

20 Sep '18

Hi, Another note is on the use of NULL|UefiPayloadPkg/Library/Tpm2InstanceLib/Tpm2InstanceLib.inf. This lib is not fully populated right now. Please consider using NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf depending on your needs. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of You, Benjamin Sent: Thursday, September 20, 2018 8:44 AM To: Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com>; coreboot(a)coreboot.org Subject: Re: [coreboot] Tianocore and TPM Hi Jorge, The staging UEFI Payload project (https://github.com/tianocore/edk2-staging/tree/UEFIPayload) has TPM support (although turned off by default, and using "FTPM" as the name (which needs to be fixed)). Please have a look at UefiPayloadPkgIA32X64.dsc for the components under tag "$(FTPM_ENABLE)". These components mainly do the measuring of firmware components and log the results. Also there is parsing logic in Library/PlatformInfoParseLib/ParseLib.c that parses TPM info in ACPI table passed from Coreboot. (This logic hasn't been sufficiently verified as this is still a "staging" project). You might have a try. Please let us know if you see any bugs / problems in these. You might also use the EDKII mailing list for discussing issues with the UEFI Payload. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Jorge Fernandez Monteagudo Sent: Wednesday, September 19, 2018 5:24 PM To: coreboot(a)coreboot.org Subject: [coreboot] Tianocore and TPM Hi all! I'm trying to enable the TPM2 support in the tianocore payload. The TPM2 device is working, because I've enabled the DEBUG_TPM and coreboot reports is up. I guess that I have to modify the 'CorebootPayloadPkgIa32X64.dsc' file to enable the TPM support but there are so many dependencies. Anybody has a working tianocore payload with TPM? Thanks!

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Re: [coreboot] Tianocore and TPM
by You, Benjamin 20 Sep '18

20 Sep '18

Hi Jorge, The staging UEFI Payload project (https://github.com/tianocore/edk2-staging/tree/UEFIPayload) has TPM support (although turned off by default, and using "FTPM" as the name (which needs to be fixed)). Please have a look at UefiPayloadPkgIA32X64.dsc for the components under tag "$(FTPM_ENABLE)". These components mainly do the measuring of firmware components and log the results. Also there is parsing logic in Library/PlatformInfoParseLib/ParseLib.c that parses TPM info in ACPI table passed from Coreboot. (This logic hasn't been sufficiently verified as this is still a "staging" project). You might have a try. Please let us know if you see any bugs / problems in these. You might also use the EDKII mailing list for discussing issues with the UEFI Payload. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Jorge Fernandez Monteagudo Sent: Wednesday, September 19, 2018 5:24 PM To: coreboot(a)coreboot.org Subject: [coreboot] Tianocore and TPM Hi all! I'm trying to enable the TPM2 support in the tianocore payload. The TPM2 device is working, because I've enabled the DEBUG_TPM and coreboot reports is up. I guess that I have to modify the 'CorebootPayloadPkgIa32X64.dsc' file to enable the TPM support but there are so many dependencies. Anybody has a working tianocore payload with TPM? Thanks!

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Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA
by h42＠memeware.net 19 Sep '18

19 Sep '18

I dont get anything on the screen from coreboot. The later os is displaying fine. How i build the image: ran on a fresh git cloned (from today) 'make menuconfig', chose just the mainboard manufacturer and the model, press esc, confirmed saving, ran 'make'. I installed this image and dont get any coreboot output on the screen. When i wait long enough, i get the output from the Linux OS on the screen. From the coreboot logfile: coreboot-4.8-1195-gb75a08b199 [...] FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = fff00000 size = 100000 #areas = 4 FMAP: area RW_MRC_CACHE found @ 10000 (65536 bytes) MRC: No data in cbmem for 'RW_MRC_CACHE'. BS: BS_DEV_ENUMERATE times (us): entry 0 run 150329 exit 16016 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... TOUUD 0x80000000 TOLUD 0x80000000 TOM 0x80000000 IGD decoded, subtracting 64M UMA and 4M GTT TSEG decoded, subtracting 8M Available memory below 4GB: 1972M Adding UMA memory area base=0x7b400000 size=0x04c00000 Adding PCIe config bar base=0xe0000000 size=0x10000000 Done reading resources. [...] [21.707417] CONFIG => [21.709411] (Primary => [21.711924] (Port => Analog , [21.715130] Framebuffer => [21.718076] (Width => 640, [21.721542] Height => 400, [21.725008] Start_X => 0, [21.728301] Start_Y => 0, [21.731594] Stride => 1, [21.734886] V_Stride => 1, [21.738179] Tiling => Linear , [21.741993] Rotation => No_Rotation, [21.746153] Offset => 0xffffffff, [21.749966] BPC => 8), [21.753085] Mode => [21.755424] (Dotclock => 148500000, [21.760192] H_Visible => 1920, [21.764524] H_Sync_Begin => 2008, [21.768857] H_Sync_End => 2052, [21.773190] H_Total => 2200, [21.777523] V_Visible => 1080, [21.781857] V_Sync_Begin => 1084, [21.786189] V_Sync_End => 1089, [21.790522] V_Total => 1125, [21.794855] H_Sync_Active_High => True, [21.799189] V_Sync_Active_High => True, [21.803521] BPC => 5)), [21.807767] Secondary => [21.810281] (Port => Disabled, [21.813487] Framebuffer => [21.816433] (Width => 1, [21.819727] Height => 1, [21.823020] Start_X => 0, [21.826313] Start_Y => 0, [21.829605] Stride => 1, [21.832899] V_Stride => 1, [21.836193] Tiling => Linear , [21.840006] Rotation => No_Rotation, [21.844166] Offset => 0x00000000, [21.847979] BPC => 8), [21.851098] Mode => [21.853438] (Dotclock => 24000000, [21.858118] H_Visible => 1, [21.862191] H_Sync_Begin => 1, [21.866263] H_Sync_End => 1, [21.870336] H_Total => 1, [21.874409] V_Visible => 1, [21.878482] V_Sync_Begin => 1, [21.882555] V_Sync_End => 1, [21.886629] V_Total => 1, [21.890702] H_Sync_Active_High => False, [21.895121] V_Sync_Active_High => False, [21.899541] BPC => 5)), [21.903787] Tertiary => [21.906300] (Port => Disabled, [21.909507] Framebuffer => [21.912453] (Width => 1, [21.915746] Height => 1, [21.919039] Start_X => 0, [21.922331] Start_Y => 0, [21.925624] Stride => 1, [21.928918] V_Stride => 1, [21.932211] Tiling => Linear , [21.936023] Rotation => No_Rotation, [21.940183] Offset => 0x00000000, [21.943996] BPC => 8), [21.947116] Mode => [21.949455] (Dotclock => 24000000, [21.954135] H_Visible => 1, [21.958207] H_Sync_Begin => 1, [21.962280] H_Sync_End => 1, [21.966353] H_Total => 1, [21.970427] V_Visible => 1, [21.974499] V_Sync_Begin => 1, [21.978572] V_Sync_End => 1, [21.982646] V_Total => 1, [21.986719] H_Sync_Active_High => False, [21.991138] V_Sync_Active_High => False, [21.995557] BPC => 5))); PCI: 00:02.0 init finished in 307222 usecs PCI: 00:02.1 init ... PCI: 00:02.1 init finished in 2009 usecs PCI: 00:1b.0 init ... [...] So it seems to have detected that my screen is 1920*1080. GPU + screen detection seems to be working. But i dont get any coreboot output on the screen. The output had worked fine on this screen with the OEM BIOS.

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Re: [coreboot] Kabylake unable to boot with post code 0x71
by Jose Trujillo 19 Sep '18

19 Sep '18

Hi Haresh, I am working on it, but before making changes into VR parameters i need to understand each one of them and make sure they are correct. VrVoltageLimit is 1.52V according to Kabylake EDS. I found icc_max values for SA and GT but not for IA and GT Unsliced on my board schematics. But I still don't have idea where to get psixthreshold values. You mentioned to get the parameters from the descriptor you meant with FIT tool or how? Also I wanted to ask you if is possible to dump those parameters from the original FW with a coreboot/intel tool or linux commands? About the previous SLP state when hangs is S5 and S0 and when hangs it looks awake S0 otherwise I would see the state change in the post code. Thank you, Jose Trujillo. ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Tuesday, September 18, 2018 6:09 PM, Naresh G. Solanki <naresh.solanki.2011(a)gmail.com> wrote: > Hi Jose, > > Ideally, FSP silicon init returns if there is error & error code is displayed. > Since return has not happended then it is most likely that input to > FSPS UPD which comes from devicetree.cb might have gone wrong. > In other word, can you match devicetree.cb setting with descriptor & > board schematics. > Especially check: domain_vr_config > > Additionally can you provide info like when the hang happens, what is > state of SLP_S0/3/4/5. > Also check voltage level for VCC_CORE/GT/SA > > Regards, > Naresh G Solanki > On Tue, Sep 18, 2018 at 3:01 PM Jose Trujillo via coreboot > coreboot(a)coreboot.org wrote: > > > Dear Naresh / All: > > I added their corresponding FSP headers but still the system never returns from the FSP function (fsp_silicon_init) post 0x71. > > My question is if somebody can tell me how to enable (if possible) FSP port 80 post codes and/or FSP serial debug from SIO (non SOC) UART. > > Thank you, > > Jose Trujillo > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > On Monday, September 17, 2018 6:14 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > Location in coreboot folder: > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp… > > > Header Files can be taken from location: > > > https://github.com/IntelFsp/FSP/tree/master/KabylakeFspBinPkg/Include > > > FSP binary can be taken from: > > > https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Fsp.fd > > > This file needs to be split into fspm.bin fsps.bin . For this refer: > > > https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/UserManual… > > > On Mon, Sep 17, 2018 at 7:51 PM Jose Trujillo ce.autom(a)protonmail.com wrote: > > > > > > > Thank you Naresh, > > > > How to do the copy? > > > > Could you give me some details? > > > > You too have an excellent day. > > > > Jose. > > > > Sent with ProtonMail Secure Email. > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > On Monday, September 17, 2018 5:17 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > I guess the FSP version you have is 3.5.0 > > > > You should have received fsp header along with fsp binary in single package. > > > > However you can get FSP binaries and header from https://github.com/IntelFsp/FSP > > > > Also make sure you copy FSP header version equal fsp binary version. > > > > All the best! > > > > On Mon 17 Sep, 2018, 3:34 PM Jose Trujillo via coreboot, coreboot(a)coreboot.org wrote: > > > > > > > > > Dear Naresh: > > > > > You are right; it never returns from the FSP function (fsp_silicon_init). > > > > > chip_fsp20.c Ln.169 > > > > > void soc_init_pre_device(void chip_info) > > > > > { > > > > > printk(BIOS_INFO, "Entering: fsp_silicon_init"); // Added > > > > > / Perform silicon specific init. / > > > > > fsp_silicon_init(romstage_handoff_is_resume()); > > > > > / swap enabled PCI ports in device tree if needed */printk(BIOS_INFO, "Entering: pcie_override_devicetree"); // Added > > > > > pcie_override_devicetree_after_silicon_init(); > > > > > printk(BIOS_INFO, "Exit: soc_init_pre_device"); // Added > > > > > } > > > > > Serial dump. > > > > > .... > > > > > Enabling SMIs. > > > > > Locking SMM. > > > > > VMX : param.enable = 0 > > > > > VMX: pre-conditions not met > > > > > VMX: pre-conditions not met > > > > > VMX: pre-conditions not met > > > > > SGX: pre-conditions not met > > > > > VMX: pre-conditions not met > > > > > SGX: pre-conditions not met > > > > > POST: 0x71 > > > > > SGX: pre-conditions not met > > > > > SGX: pre-conditions not met > > > > > Entering: fsp_silicon_init <------ never returns from FSP. > > > > > .... > > > > > About the FSP header version I am not sure how exactly to obtain it but getting the binary decription from BCT I got: > > > > > Header Revision: 0x3 > > > > > Image Revision: 0x3050000 > > > > > 3.0.5 ???? > > > > > See the attached file for more details about the FSP binary. > > > > > Please advise. > > > > > Thank you, > > > > > Jose Trujillo. > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > On Friday, September 14, 2018 6:58 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > > > > > > > With available data. It is most likely that it might have stuck > > > > > > somewhere in function > > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/ch… > > > > > > You can add printk in that function & other functions called by it to > > > > > > bisect & confirm the exact position of hang.. > > > > > > Also can you please check FSP binary version you are using versus FSP > > > > > > header version checked-out in coreboot(which is currently 2.9.2). > > > > > > They should be > > > > > > On Fri, Sep 14, 2018 at 7:55 PM Jose Trujillo via coreboot > > > > > > coreboot(a)coreboot.org wrote: > > > > > > > > > > > > > Here is Naresh.... > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > On Friday, September 14, 2018 4:49 PM, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > > > Can you also provide latest complete log. > > > > > > > On Fri 14 Sep, 2018, 2:10 PM Jose Trujillo via coreboot, coreboot(a)coreboot.org wrote: > > > > > > > > > > > > > > > Thank you Naresh, > > > > > > > > I added the missing PCH device id following your advise, also enabled DEBUG_BOOT_STATE but I am still not able to get more information via serial debug about the exact location of the problem (but now I am certain is in the coreboot code not in FSP). > > > > > > > > I suspect the code involved aound this issue is hardwaremain.c and device.c.... > > > > > > > > Only the first "boot" just after flash I notice that the ethernet and SATA LEDs blink for a fraction of a second then reboots. > > > > > > > > After that, the following attempts to boot I don't see LED activity neither reboots, just halted in some kind of loop. > > > > > > > > According to the serial dump the las printed text is "0x71" but my question is if the serial port gets broken still during "BS_DEV_INIT_CHIPS" or is already doing "BS_DEV_ENUMERATE". > > > > > > > > As Naresh pointed my PCH H chipset "Kabylake-H HM175" was not added to the list; I added it but may be is needed to do something else to make it work. > > > > > > > > Or istill is misconfigured (attached my .config file for your review)... I someone has a similar system working and want to share its configuration files to compare them myself I will be grateful. > > > > > > > > Jose Trujillo. > > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > > On Wednesday, 12 September 2018 19:33, Naresh G. Solanki naresh.solanki.2011(a)gmail.com wrote: > > > > > > > > Hi > > > > > > > > > > > > > > > > > PCH: device id a152 (rev 31) is Unknown > > > > > > > > > > > > > > > > This indicates that LPCID 0xa152 is not added. > > > > > > > > The #define should be added in source path: https://review.coreboot.org/cgit/coreboot.git/tree/src/include/device/pci_i… > > > > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/blo… > > > > > > > > & > > > > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/bo… > > > > > > > > as well. > > > > > > > > Additionally you can enable config DEBUG_BOOT_STATE to understand where exactly its stuck. > > > > > > > > Regards, > > > > > > > > Naresh G. Solanki > > > > > > > > On Wed, Sep 12, 2018 at 9:24 PM Jose Trujillo via coreboot coreboot(a)coreboot.org wrote: > > > > > > > > > > > > > > > > > Dear All, > > > > > > > > > About the memory I just changed the dimm to address A0 and now coreboot is reporting correctly 1 dimm detected. > > > > > > > > > But still no luck on the 0x71 post code loop (looks it is in some kind of loop because is still responsive to power and reset buttons). > > > > > > > > > I don't know where this loop could be located (coreboot or FSP). > > > > > > > > > The description on the post_codes.h file shows the following: > > > > > > > > > .... > > > > > > > > > /** > > > > > > > > > > > > > > > > > > - \brief Initializing Chips > > > > > > > > > - > > > > > > > > > - Boot State Machine: bs_dev_init_chips() > > > > > > > > > */ > > > > > > > > > #define POST_BS_DEV_INIT_CHIPS 0x71 > > > > > > > > > .... > > > > > > > > > > > > > > > > > > > > > > > > > > > Any advice on this issue? > > > > > > > > > Attached is the serial dump with extra information. > > > > > > > > > Thank you > > > > > > > > > Jose Trujillo > > > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > > > On Wednesday, 12 September 2018 16:12, Jose Trujillo ce.autom(a)protonmail.com wrote: > > > > > > > > > To begin with the system didn't find memory attached... > > > > > > > > > but there is memory attached, SPD address mismatch? I will check. > > > > > > > > > .... > > > > > > > > > .......Timeout while sending command 0x0d to EC! > > > > > > > > > recv_ec_data: 0xff > > > > > > > > > recv_ec_data: 0xff > > > > > > > > > SPD index 7 > > > > > > > > > No memory dimm at address A0 > > > > > > > > > No memory dimm at address A2 > > > > > > > > > No memory dimm at address A6 > > > > > > > > > .... > > > > > > > > > 0 DIMMs found > > > > > > > > > .... > > > > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > > > > > > > > On Wednesday, 12 September 2018 13:29, Jose Trujillo via coreboot coreboot(a)coreboot.org wrote: > > > > > > > > > Dear coreboot engineers: > > > > > > > > > Right now I am stuck with a Kabylake system with the following message: > > > > > > > > > .... > > > > > > > > > CPU #1 initialized > > > > > > > > > apic_id: 0x06 done. > > > > > > > > > microcode: updated to revision 0x8d date=2018-01-21 > > > > > > > > > CPU #3 initialized > > > > > > > > > bsp_do_flight_plan done after 220 msecs. > > > > > > > > > CPU: frequency set to 3600 MHz > > > > > > > > > Enabling SMIs. > > > > > > > > > Locking SMM. > > > > > > > > > VMX : param.enable = 0 > > > > > > > > > VMX: pre-conditions not met > > > > > > > > > SGX: pre-conditions not met > > > > > > > > > VMX: pre-conditions not met > > > > > > > > > VMX: pre-conditions not met > > > > > > > > > SGX: pre-conditions not met > > > > > > > > > SGX: pre-conditions not met > > > > > > > > > VMX: pre-conditions not met > > > > > > > > > SGX: pre-conditions not met > > > > > > > > > POST: 0x71 > > > > > > > > > .... > > > > > > > > > May be some configuration is missing and I am trying to find this out myself but if someone of you can give a hint on how to resolve it I will be grateful. > > > > > > > > > Attached is the full serial dump. > > > > > > > > > Thank you, > > > > > > > > > Jose Trujillo > > > > > > > > > > > > > > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > > > > > > > > > -- > > > > > > > > Best regards, > > > > > > > > Naresh G. Solanki > > > > > > > > > > > > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > > > > > > > -- > > > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > > > > > -- > > > > > > Best regards, > > > > > > Naresh G. Solanki > > > > > > > > > > -- > > > > > coreboot mailing list: coreboot(a)coreboot.org > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > -- > > > Best regards, > > > Naresh G. Solanki > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > > -- > > Best regards, > Naresh G. Solanki

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Tianocore and TPM
by Jorge Fernandez Monteagudo 19 Sep '18

19 Sep '18

Hi all! I'm trying to enable the TPM2 support in the tianocore payload. The TPM2 device is working, because I've enabled the DEBUG_TPM and coreboot reports is up. I guess that I have to modify the 'CorebootPayloadPkgIa32X64.dsc' file to enable the TPM support but there are so many dependencies. Anybody has a working tianocore payload with TPM? Thanks!

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Re: [coreboot] Coreboot for Apollolake
by Angel Pons 19 Sep '18

19 Sep '18

Resending because I forgot to mail it to the list: Hello Antony, Firstly, the quoted message matches the one added by CB:28382 [1], which makes me think you are not using 4.8.1, but master instead. This is not the primary issue, though it is worth noting. With regard to the message you mentioned, its purpose is to warn unsuspecting people against flashing a *complete* coreboot.rom when it lacks an IFD (Intel Flash Descriptor). AFAIK, most modern systems will fail to function properly without it. That does not mean the image is unbootable, but it is not usable on its own. If you want to flash it to a flash chip, your flasher software must be able to write only to the BIOS region (defined by the IFD). flashrom [2] is capable of doing so, with the IFD or layout options. The former uses the existing flash chip contents to determine the region to flash. Another option is to extract the IFD and other regions from the flash chip, add them to coreboot (either using coreboot's Kconfig options or manually splicing the files) and flash the resulting, complete image. I do not recommend this unless absolutely necessary (it rewrites the whole flash chip instead of the desired region, which is more error-prone). Best regards, Angel Pons Pons [1]: https://review.coreboot.org/c/coreboot/+/28382 [2]: https://www.flashrom.org/Flashrom (I do not know about Chromium flashrom's capabilities)

1 0

Recovery
by Sebastian 18 Sep '18

18 Sep '18

Could there be some mechanism to repair broken OS setups? Maybe chroot or like android does with factory reset? I mean, I've been using Arch on Pi3 and updated libidn but not systemd and now I've got access to Coreboot only. My fault, but some mechanism for repairing broken installs seems vital as various things might happen. On the other hand I could just forget all that and...

3 2

Re: [coreboot] Coreboot for Apollolake
by David Hendricks 18 Sep '18

18 Sep '18

Hi Antony, There are a few components which compose a complete firmware image for Intel platforms: coreboot, FSP, microcode, management engine blob, and flash descriptor are the most common ones. For the flash descriptor, refer to the Apollo Lake SoC SPI and signed Master Image Profile (SMIP) Programming Guide, docid 559702. Chapter 4 explains the flash descriptor for Apollo Lake in detail. Once you have created a flash descriptor, you can add it to the firmware image using coreboot's config system (under "Chipset"). On Tue, Sep 18, 2018 at 1:43 AM Antony AbeePrakash X V < AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > Hi, > > > > We would like to build coreboot image for Apollo lake platform. We are > using > > - Coreboot-4.8.1 > - Apollo lake Intel FSP_2_0 > > > > We have built the coreboot source and created coreboot.rom image with the > below warning message: > > * ** WARNING *** > > *coreboot will be built without an Intel Firmware Descriptor.* > > *Never write a complete coreboot.rom without an IFD to your* > > *board's flash chip! You can use flashrom's IFD or layout* > > *parameters to flash only to the BIOS region.* > > > > Is the coreboot.rom image is enough to flash ? Could you please provide > feedback on this ? > > > > Thanks & Regards, > > Antony > > > > *L&T Technology Services Ltd* > > www.LntTechservices.com <http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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coreboot September 2018