coreboot September 2018

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Re: [coreboot] Tianocore and TPM
by Jorge Fernandez Monteagudo 21 Sep '18

21 Sep '18

Hi, I'll try modifying the Setup/Miscs/Setup.ini from CustomizationSample/Boards/Qemu to enable ftpm and generate an external payload but when boot with this coreboot.rom flashed I only get a black screen once the tianocore is executed with the next traces: BS: BS_PAYLOAD_LOAD times (us): entry 0 run 101395 exit 0 Jumping to boot code at 006009a0(8fe0f000) CPU0: stack: 8ff20000 - 8ff21000, lowest used address 8ff205e0, stack used: 2592 bytes PROGRESS CODE: V03020003 I0 PROGRESS CODE: V03020002 I0 PROGRESS CODE: V03020003 I0 PROGRESS CODE: V03020002 I0 PROGRESS CODE: V03020003 I0 PROGRESS CODE: V03021001 I0 PROGRESS CODE: V03040003 I0 PROGRESS CODE: V03040002 I0 PROGRESS CODE: V03040003 I0 PROGRESS CODE: V03040002 I0 I've tried mixing the dsc, dec and fdf files from the edk2-staging and the CorebootPayloadPkg ones but no TPM menu in the device manager menu is shown. I'm using NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf instead of NULL|UefiPayloadPkg/Library/Tpm2InstanceLib/Tpm2InstanceLib.inf Is it correct? Or I have to integrate this library in the CorebootPayloadPkg? Now I'm trying with the tianocore master version instead of the stable one. Do you know if there is a TPM menu shown in the device manager menu once is detected? How the TPM2 is detected? Do you have a "generic" CustomizationSample/Board? I think it's more complicated that I expected! Any hint is welcome! Jorge ________________________________ De: coreboot <coreboot-bounces(a)coreboot.org> en nombre de Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com> Enviado: jueves, 20 de septiembre de 2018 10:31:20 Para: You, Benjamin; coreboot(a)coreboot.org Asunto: Re: [coreboot] Tianocore and TPM Hi Ben, Adding the 'generic' board it's an interesting option as a starting point to develop/porting to new boards. I'll try your suggestion to incorporate the changes from dsc and fdf files to my current working Tianocore coreboot payload. I'll report back the results! Thanks! Jorge ________________________________ De: You, Benjamin <benjamin.you(a)intel.com> Enviado: jueves, 20 de septiembre de 2018 10:21:55 Para: Jorge Fernandez Monteagudo; coreboot(a)coreboot.org Asunto: RE: [coreboot] Tianocore and TPM Hi Jorge, You could use UEFI Payload's .dsc and .fdf files as a reference and modify the TianoCore CorebootPayload's .dsc and .fdf files accordingly for those TPM related modules. UEFI Payload is under development (in staging area) and hasn't reached the quality standard required by EDKII master. On CustomizationSample/Boards, yes it is required. However, a board's content may be trivial (as in the Qemu folder). Per your suggestion, probably we can add a board named "generic" that has all the minimalized settings so user won't have to create a new one if the "generic" one meets the needs. Thanks! - ben From: Jorge Fernandez Monteagudo [mailto:jorgefm@cirsa.com] Sent: Thursday, September 20, 2018 3:24 PM To: You, Benjamin <benjamin.you(a)intel.com>; coreboot(a)coreboot.org Subject: Re: Tianocore and TPM Hi Ben! Thanks for the info! I have one question. Have I to implement a CustomizationSample/Boards for my board? With the current tianocore payload I don't have to implement nothing to have a working UEFI... Thanks! Jorge ________________________________________ De: You, Benjamin <benjamin.you(a)intel.com> Enviado: jueves, 20 de septiembre de 2018 3:42:33 Para: Jorge Fernandez Monteagudo; coreboot(a)coreboot.org Asunto: RE: Tianocore and TPM Hi, Another note is on the use of NULL|UefiPayloadPkg/Library/Tpm2InstanceLib/Tpm2InstanceLib.inf. This lib is not fully populated right now. Please consider using NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf depending on your needs. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of You, Benjamin Sent: Thursday, September 20, 2018 8:44 AM To: Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com>; coreboot(a)coreboot.org Subject: Re: [coreboot] Tianocore and TPM Hi Jorge, The staging UEFI Payload project (https://github.com/tianocore/edk2-staging/tree/UEFIPayload) has TPM support (although turned off by default, and using "FTPM" as the name (which needs to be fixed)). Please have a look at UefiPayloadPkgIA32X64.dsc for the components under tag "$(FTPM_ENABLE)". These components mainly do the measuring of firmware components and log the results. Also there is parsing logic in Library/PlatformInfoParseLib/ParseLib.c that parses TPM info in ACPI table passed from Coreboot. (This logic hasn't been sufficiently verified as this is still a "staging" project). You might have a try. Please let us know if you see any bugs / problems in these. You might also use the EDKII mailing list for discussing issues with the UEFI Payload. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Jorge Fernandez Monteagudo Sent: Wednesday, September 19, 2018 5:24 PM To: coreboot(a)coreboot.org Subject: [coreboot] Tianocore and TPM Hi all! I'm trying to enable the TPM2 support in the tianocore payload. The TPM2 device is working, because I've enabled the DEBUG_TPM and coreboot reports is up. I guess that I have to modify the 'CorebootPayloadPkgIa32X64.dsc' file to enable the TPM support but there are so many dependencies. Anybody has a working tianocore payload with TPM? Thanks!

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Re: [coreboot] Coreboot for Apollolake
by Nico Huber 20 Sep '18

20 Sep '18

Hi Antony, On 20.09.2018 09:28, Antony AbeePrakash X V wrote: > Thanks for the response , we extracted the flash descriptor from the > BIOS Image using the ifdtool as below if you already have a working firmware combination for your board (I assume the BIOS Image you mention is one), I can only advice against tinkering with any flash region but the BIOS region. If you have wor- king IFD/ME regions in flash, better treat them as read-only (if you use flashrom, use a layout or --ifd and only include the BIOS region). It's ok to ignore the Firmware Descriptor warning, as long as you only flash the BIOS region. Writing the whole flash at once on an Intel platform is rather error-prone. > CBFSLAYOUT coreboot.rom > > This is a legacy image composed entirely of a single CBFS. It's hard to tell where things went wrong. At some step above the FMAP in the coreboot image must have been corrupted. One way to figure out would be to run `cbfstool <file> layout` on each intermediate file. You can see all the steps and file names if you run make with V=1. Yet again, I can only advice to skip the descriptor integration and flash regions individually instead. Nico

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Re: [coreboot] Kabylake unable to boot with post code 0x71 "SGX: pre-conditions not met"
by Jose Trujillo 20 Sep '18

20 Sep '18

Dear Naresh, I choose the RVP8 board because is the only match in terms of CPU and memory, other templates made by google supports kabylake U/Y only processors and no DDR4. My system has differences and I will check them after I finish GPIO. I already determined the proper VR settings and set them in devicetree (the default voltage setting was 0V -power was shutdown??-) and I will see if after the corrections of VR and GPIO the system boots. I will follow your advise of checking EC and about the base FW I am using the original UEFI AMI FW but, if still doesn't boot I will replace ME and descriptor as you suggested. Thank you, Jose Trujillo. ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Thursday, September 20, 2018 4:03 PM, Naresh G. Solanki <naresh.solanki.2011(a)gmail.com> wrote: > RVP8 is known to boot. GPIO config should be fine unless you are modifying HW. > > In logs you provided, ec communication seems to fail. Thus can you > make sure right EC is flashed in the RVP8. > In my board, it looks like this: > recv_ec_data: 0x10 > recv_ec_data: 0x69 > > Also make sure that you have right descriptor & ME are for RVP8 > > Attached is config I've tried & it executed till end of ramstage. > > On Thu, Sep 20, 2018 at 1:25 PM Jose Trujillo via coreboot > coreboot(a)coreboot.org wrote: > > > Hello Nico, > > Yes, I am using Intel Kabylake DDR4 RVP8 board. > > > > > Never use another board's GPIO settings. > > > Reading the mail list yesterday I saw that warning maybe from you and I will do the correct changes to GPIO just after editing VR settings. > > > > I am just started coreboot several months ago and there is still a lot of road to go for me and still don't understand many things; but I am doing my best to get aligned with the coreboot project. > > After the GPIO changes I will check my schematics to check for hardware differences before I flash it into my device. > > Thank you ALL for your help. > > Jose Trujillo > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > On Wednesday, September 19, 2018 10:15 PM, Nico Huber nico.h(a)gmx.de wrote: > > > > > Hi Jose, > > > On 12.09.2018 15:12, Jose Trujillo via coreboot wrote: > > > > > > > To begin with the system didn't find memory attached... > > > > but there is memory attached, SPD address mismatch? I will check. > > > > .... > > > > .......Timeout while sending command 0x0d to EC! > > > > > > I'm not sure what this is about. Did you try to talk to your board's > > > EC? Can you share the code? Or do you run another board's code on your > > > board? That would explain why things go wrong. Also, my usual warning: > > > Never use another board's GPIO settings. > > > Nico > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > > -- > > Best regards, > Naresh G. Solanki

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Re: [coreboot] Kabylake unable to boot with post code 0x71 "SGX: pre-conditions not met"
by Naresh G. Solanki 20 Sep '18

20 Sep '18

RVP8 is known to boot. GPIO config should be fine unless you are modifying HW. In logs you provided, ec communication seems to fail. Thus can you make sure right EC is flashed in the RVP8. In my board, it looks like this: recv_ec_data: 0x10 recv_ec_data: 0x69 Also make sure that you have right descriptor & ME are for RVP8 Attached is config I've tried & it executed till end of ramstage. On Thu, Sep 20, 2018 at 1:25 PM Jose Trujillo via coreboot <coreboot(a)coreboot.org> wrote: > > Hello Nico, > > Yes, I am using Intel Kabylake DDR4 RVP8 board. > > > Never use another board's GPIO settings. > Reading the mail list yesterday I saw that warning maybe from you and I will do the correct changes to GPIO just after editing VR settings. > > I am just started coreboot several months ago and there is still a lot of road to go for me and still don't understand many things; but I am doing my best to get aligned with the coreboot project. > > After the GPIO changes I will check my schematics to check for hardware differences before I flash it into my device. > > Thank you ALL for your help. > Jose Trujillo > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > On Wednesday, September 19, 2018 10:15 PM, Nico Huber <nico.h(a)gmx.de> wrote: > > > Hi Jose, > > > > On 12.09.2018 15:12, Jose Trujillo via coreboot wrote: > > > > > To begin with the system didn't find memory attached... > > > but there is memory attached, SPD address mismatch? I will check. > > > .... > > > .......Timeout while sending command 0x0d to EC! > > > > I'm not sure what this is about. Did you try to talk to your board's > > EC? Can you share the code? Or do you run another board's code on your > > board? That would explain why things go wrong. Also, my usual warning: > > Never use another board's GPIO settings. > > > > Nico > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- Best regards, Naresh G. Solanki

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Re: [coreboot] SAR in Coreboot
by Jonathan Neuschäfer 20 Sep '18

20 Sep '18

On Thu, Sep 20, 2018 at 01:49:57PM +0530, galla rao wrote: > Hi All, > > This is my first email to coreboot open source team Hi and welcome! > Does coreboot 4.8/4.9 support > *Specific absorption rate* (*SAR*) > > How does Linux or Kernel driver uses the SAR Tx Power limits, Anyone > working on this task, Kindly respond The Intel Wifi driver (or rather ACPI/SMBIOS table generator) has an option called USE_SAR[1], which controls whether SAR related tables are generated[2]. This option is used by a few Chromebooks[3]. I don't know how these power limits work in detail, but this may be a good starting point for further investigation. Jonathan Neuschäfer [1]: https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/intel/wifi/K… [2]: https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/intel/wifi/w… [3]: poppy, glados, eve, reef, and octopus in https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/google

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Re: [coreboot] SAR in Coreboot
by David Hendricks 20 Sep '18

20 Sep '18

Hi Gallo, coreboot does not do anything with SAR, as far as I know. There may be some data (e.g. regulatory domain setting) that you need to provide to the modem, though. You should check the driver and documentation for the modem to get more details. On Thu, Sep 20, 2018 at 1:21 AM galla rao <galla.rao80(a)gmail.com> wrote: > Hi All, > > This is my first email to coreboot open source team > > Does coreboot 4.8/4.9 support > *Specific absorption rate* (*SAR*) > > How does Linux or Kernel driver uses the SAR Tx Power limits, Anyone > working on this task, Kindly respond > > regards > Galla > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Tianocore and TPM
by Jorge Fernandez Monteagudo 20 Sep '18

20 Sep '18

Hi Ben, Adding the 'generic' board it's an interesting option as a starting point to develop/porting to new boards. I'll try your suggestion to incorporate the changes from dsc and fdf files to my current working Tianocore coreboot payload. I'll report back the results! Thanks! Jorge ________________________________ De: You, Benjamin <benjamin.you(a)intel.com> Enviado: jueves, 20 de septiembre de 2018 10:21:55 Para: Jorge Fernandez Monteagudo; coreboot(a)coreboot.org Asunto: RE: [coreboot] Tianocore and TPM Hi Jorge, You could use UEFI Payload's .dsc and .fdf files as a reference and modify the TianoCore CorebootPayload's .dsc and .fdf files accordingly for those TPM related modules. UEFI Payload is under development (in staging area) and hasn't reached the quality standard required by EDKII master. On CustomizationSample/Boards, yes it is required. However, a board's content may be trivial (as in the Qemu folder). Per your suggestion, probably we can add a board named "generic" that has all the minimalized settings so user won't have to create a new one if the "generic" one meets the needs. Thanks! - ben From: Jorge Fernandez Monteagudo [mailto:jorgefm@cirsa.com] Sent: Thursday, September 20, 2018 3:24 PM To: You, Benjamin <benjamin.you(a)intel.com>; coreboot(a)coreboot.org Subject: Re: Tianocore and TPM Hi Ben! Thanks for the info! I have one question. Have I to implement a CustomizationSample/Boards for my board? With the current tianocore payload I don't have to implement nothing to have a working UEFI... Thanks! Jorge ________________________________________ De: You, Benjamin <benjamin.you(a)intel.com> Enviado: jueves, 20 de septiembre de 2018 3:42:33 Para: Jorge Fernandez Monteagudo; coreboot(a)coreboot.org Asunto: RE: Tianocore and TPM Hi, Another note is on the use of NULL|UefiPayloadPkg/Library/Tpm2InstanceLib/Tpm2InstanceLib.inf. This lib is not fully populated right now. Please consider using NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf depending on your needs. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of You, Benjamin Sent: Thursday, September 20, 2018 8:44 AM To: Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com>; coreboot(a)coreboot.org Subject: Re: [coreboot] Tianocore and TPM Hi Jorge, The staging UEFI Payload project (https://github.com/tianocore/edk2-staging/tree/UEFIPayload) has TPM support (although turned off by default, and using "FTPM" as the name (which needs to be fixed)). Please have a look at UefiPayloadPkgIA32X64.dsc for the components under tag "$(FTPM_ENABLE)". These components mainly do the measuring of firmware components and log the results. Also there is parsing logic in Library/PlatformInfoParseLib/ParseLib.c that parses TPM info in ACPI table passed from Coreboot. (This logic hasn't been sufficiently verified as this is still a "staging" project). You might have a try. Please let us know if you see any bugs / problems in these. You might also use the EDKII mailing list for discussing issues with the UEFI Payload. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Jorge Fernandez Monteagudo Sent: Wednesday, September 19, 2018 5:24 PM To: coreboot(a)coreboot.org Subject: [coreboot] Tianocore and TPM Hi all! I'm trying to enable the TPM2 support in the tianocore payload. The TPM2 device is working, because I've enabled the DEBUG_TPM and coreboot reports is up. I guess that I have to modify the 'CorebootPayloadPkgIa32X64.dsc' file to enable the TPM support but there are so many dependencies. Anybody has a working tianocore payload with TPM? Thanks!

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Re: [coreboot] Tianocore and TPM
by You, Benjamin 20 Sep '18

20 Sep '18

Hi Jorge, You could use UEFI Payload's .dsc and .fdf files as a reference and modify the TianoCore CorebootPayload's .dsc and .fdf files accordingly for those TPM related modules. UEFI Payload is under development (in staging area) and hasn't reached the quality standard required by EDKII master. On CustomizationSample/Boards, yes it is required. However, a board's content may be trivial (as in the Qemu folder). Per your suggestion, probably we can add a board named "generic" that has all the minimalized settings so user won't have to create a new one if the "generic" one meets the needs. Thanks! - ben From: Jorge Fernandez Monteagudo [mailto:jorgefm@cirsa.com] Sent: Thursday, September 20, 2018 3:24 PM To: You, Benjamin <benjamin.you(a)intel.com>; coreboot(a)coreboot.org Subject: Re: Tianocore and TPM Hi Ben! Thanks for the info! I have one question. Have I to implement a CustomizationSample/Boards for my board? With the current tianocore payload I don't have to implement nothing to have a working UEFI... Thanks! Jorge ________________________________________ De: You, Benjamin <benjamin.you(a)intel.com> Enviado: jueves, 20 de septiembre de 2018 3:42:33 Para: Jorge Fernandez Monteagudo; coreboot(a)coreboot.org Asunto: RE: Tianocore and TPM Hi, Another note is on the use of NULL|UefiPayloadPkg/Library/Tpm2InstanceLib/Tpm2InstanceLib.inf. This lib is not fully populated right now. Please consider using NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf depending on your needs. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of You, Benjamin Sent: Thursday, September 20, 2018 8:44 AM To: Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com>; coreboot(a)coreboot.org Subject: Re: [coreboot] Tianocore and TPM Hi Jorge, The staging UEFI Payload project (https://github.com/tianocore/edk2-staging/tree/UEFIPayload) has TPM support (although turned off by default, and using "FTPM" as the name (which needs to be fixed)). Please have a look at UefiPayloadPkgIA32X64.dsc for the components under tag "$(FTPM_ENABLE)". These components mainly do the measuring of firmware components and log the results. Also there is parsing logic in Library/PlatformInfoParseLib/ParseLib.c that parses TPM info in ACPI table passed from Coreboot. (This logic hasn't been sufficiently verified as this is still a "staging" project). You might have a try. Please let us know if you see any bugs / problems in these. You might also use the EDKII mailing list for discussing issues with the UEFI Payload. Thanks, - ben From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Jorge Fernandez Monteagudo Sent: Wednesday, September 19, 2018 5:24 PM To: coreboot(a)coreboot.org Subject: [coreboot] Tianocore and TPM Hi all! I'm trying to enable the TPM2 support in the tianocore payload. The TPM2 device is working, because I've enabled the DEBUG_TPM and coreboot reports is up. I guess that I have to modify the 'CorebootPayloadPkgIa32X64.dsc' file to enable the TPM support but there are so many dependencies. Anybody has a working tianocore payload with TPM? Thanks!

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SAR in Coreboot
by galla rao 20 Sep '18

20 Sep '18

Hi All, This is my first email to coreboot open source team Does coreboot 4.8/4.9 support *Specific absorption rate* (*SAR*) How does Linux or Kernel driver uses the SAR Tx Power limits, Anyone working on this task, Kindly respond regards Galla

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Re: [coreboot] Kabylake unable to boot with post code 0x71 "SGX: pre-conditions not met"
by Nico Huber 20 Sep '18

20 Sep '18

Hi Jose, On 12.09.2018 15:12, Jose Trujillo via coreboot wrote: > To begin with the system didn't find memory attached... > but there is memory attached, SPD address mismatch? I will check. > .... > .......Timeout while sending command 0x0d to EC! I'm not sure what this is about. Did you try to talk to your board's EC? Can you share the code? Or do you run another board's code on your board? That would explain why things go wrong. Also, my usual warning: Never use another board's GPIO settings. Nico

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coreboot September 2018