coreboot November 2018

coreboot@coreboot.org

71 participants
149 discussions

Re: [coreboot] Supported Motherboards
by Kinky Nekoboi 07 Nov '18

07 Nov '18

kinda... the wiki and the supported board lists are maintained by devs in their freetime i guess so it is not always 100% up to date. u can see all target board currently supported (more or less ) in the nconfig build menu while compieling coreboot. Am 07.11.18 um 17:37 schrieb J Clamp: > > I also was curious to know if the website that I found lists all of > the motherboards that coreboot currently supports? > > On 07/11/2018 16:07, kinky_nekoboi wrote: >> Hi J.Clamp, >> what kind of usecase to u have for your mainboard? >> I use the G41m-es2l for my homeserver. >> It supports core 2 quad CPUs and has 2 DDR2 slots. >> Also it is usable without any nonfree blobs. >> if u need something more powerful look for the ivy bridge boards or >> one that does support the 15th gen Amd cpus >> >> Am 7. November 2018 16:56:57 MEZ schrieb J Clamp via coreboot >> <coreboot(a)coreboot.org>: >> >> Hi all, >> >> I am new to coreboot and was looking for a motherboard that would >> support coreboot. I have checked and looked at this page but I don't >> know if coreboot is supported on all of these motherboards or if only >> certain motherboards support coreboot? Any help would be greatly >> appreciated. >> >> Here is the link to the page that I found - >> https://coreboot.org/status/board-status.html >> >>

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Re: [coreboot] Coreboot hangs during SYS_RESET
by Naresh G. Solanki 07 Nov '18

07 Nov '18

1. Can you make sure right microcode based on the CPUID is added. This is must. Based on CPUID(I guess 506cX for APL), you can locate them at 3rdparty/blobs/.. Select CBFS GENERATE and specify CPU UCODE BINARIES path. 2. Can you provide complete log and config(after adding microcode into cbfs) if you still see sys_reset issue. Regards, Naresh On Wed 7 Nov, 2018, 8:56 PM Aaron Durbin via coreboot <coreboot(a)coreboot.org wrote: > On Wed, Nov 7, 2018 at 6:47 AM Antony AbeePrakash X V > <AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > > > Hi, > > > > > > > > We are developing coreboot (with Intel FSP) for apollo lake platform > custom board. We are facing a hang issue during the SYS_RESET button press. > > > > > > > > Observations: > > > > With soft reset the board gets hang(occurs within 2 or 3 reboot) with > POST code 0x38 and the coreboot log stops during the romstage relocation. > (Logs attached for Ref.) > > When the SYS_RESET is pressed again the board boots and hangs at same > POST code 0x38. > > > > > > > > Please provide feedback and help us to resolve this issue. > > > > I'm confused by the following logs in romstage: > > CBFS @ 0 size 70000 > CBFS: Locating 'romstage.rel' > CBFS: Found @ offset 64c0 size 480 > romstage is relocated from fef40054 to 0x7abf1000 > > I'm not familiar where this code is coming from. Are you carrying > external patches or have I forgotten what is going on here? > > > > > > > Currently our coreboot build does not include any microcode > (CPU_MICROCODE_CBFS_NONE). We tried to change it as “Generate from tree” in > memuconfig. > > > > But the build fails with fatal error saying no microcode/microcode.h > file. > > > > > > > > Whether the CPU by default have microcode ? or we need to build the > microcode in coreboot ? > > > > Please advise on this. > > > > > > > > Thanks & Regards, > > > > Antony > > > > > > > > L&T Technology Services Ltd > > > > www.LntTechservices.com > > > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Supported Motherboards
by kinky_nekoboi 07 Nov '18

07 Nov '18

as far as i know it uses xen? so you need AMD-V or Intel VT-x + VT-d i think and sandy/ivy bridge platform with fsp blob would fit this needs best there is the asus maximus ... and there is the T520 with a vpro cpu with feeds this needs best i guess Am 7. November 2018 17:33:40 MEZ schrieb J Clamp <jamieclamp(a)lavabit.com>: >I am thinking of installing QubesOS on the mainboard. One of the >requirements for QubesOS 4.0 is that it has to run coreboot. > >On 07/11/2018 16:07, kinky_nekoboi wrote: >> Hi J.Clamp, >> what kind of usecase to u have for your mainboard? >> I use the G41m-es2l for my homeserver. >> It supports core 2 quad CPUs and has 2 DDR2 slots. >> Also it is usable without any nonfree blobs. >> if u need something more powerful look for the ivy bridge boards or >> one that does support the 15th gen Amd cpus >> >> Am 7. November 2018 16:56:57 MEZ schrieb J Clamp via coreboot >> <coreboot(a)coreboot.org>: >> >> Hi all, >> >> I am new to coreboot and was looking for a motherboard that would >> support coreboot. I have checked and looked at this page but I >don't >> know if coreboot is supported on all of these motherboards or if >only >> certain motherboards support coreboot? Any help would be greatly >> appreciated. >> >> Here is the link to the page that I found - >> https://coreboot.org/status/board-status.html >> >>

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Supported Motherboards
by J Clamp 07 Nov '18

07 Nov '18

Hi all, I am new to coreboot and was looking for a motherboard that would support coreboot. I have checked and looked at this page but I don't know if coreboot is supported on all of these motherboards or if only certain motherboards support coreboot? Any help would be greatly appreciated. Here is the link to the page that I found - https://coreboot.org/status/board-status.html

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Using LPC bus serial interrupts
by yanvasilij yan 07 Nov '18

07 Nov '18

Hello! I am trying to use LPC wire on my Intel Atom E3800 based board for communication with my custom FPGA device. There is sja1000 CAN transivere realized on this device. So I can work with this device by polling with no problem. But for some strange reason, I don’t get interrupts from this device. I see by oscilloscope serial irq requests from CPU and the device is response, but my OS (Linux) does not get this interrupts. Here my board directory https://github.com/yanvasilij/nefteavtomatika. I think I have a similar problem like this https://mail.coreboot.org/pipermail/coreboot/2016-January/080839.html. But my device use IRQ7, not IRQ4. So I made like described here https://mail.coreboot.org/pipermail/coreboot/2016-January/080848.html. There are adviced to me to describe my LPC device in devicetree. But should I realy to do it, if I working with LPC bus directly from Linux? What am I doing wrong? What am I doing wrong? May be I have a problem with IRQ route? Linux dmesg output and .config are in attachments. Regards Vasily Предварительный просмотр файла dmesg.txt dmesg.txt 36 KB <https://mail.google.com/mail/u/0?ui=2&ik=5c96cffe3a&attid=0.2&permmsgid=msg…> Предварительный просмотр файла .config .config 20 KB <https://mail.google.com/mail/u/0?ui=2&ik=5c96cffe3a&attid=0.1&permmsgid=msg…> <https://mail.google.com/mail/u/0?ui=2&ik=5c96cffe3a&attid=0.2&permmsgid=msg…>

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Re: [coreboot] Coreboot hangs during SYS_RESET
by Aaron Durbin 07 Nov '18

07 Nov '18

On Wed, Nov 7, 2018 at 6:47 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > Hi, > > > > We are developing coreboot (with Intel FSP) for apollo lake platform custom board. We are facing a hang issue during the SYS_RESET button press. > > > > Observations: > > With soft reset the board gets hang(occurs within 2 or 3 reboot) with POST code 0x38 and the coreboot log stops during the romstage relocation. (Logs attached for Ref.) > When the SYS_RESET is pressed again the board boots and hangs at same POST code 0x38. > > > > Please provide feedback and help us to resolve this issue. > I'm confused by the following logs in romstage: CBFS @ 0 size 70000 CBFS: Locating 'romstage.rel' CBFS: Found @ offset 64c0 size 480 romstage is relocated from fef40054 to 0x7abf1000 I'm not familiar where this code is coming from. Are you carrying external patches or have I forgotten what is going on here? > > > Currently our coreboot build does not include any microcode (CPU_MICROCODE_CBFS_NONE). We tried to change it as “Generate from tree” in memuconfig. > > But the build fails with fatal error saying no microcode/microcode.h file. > > > > Whether the CPU by default have microcode ? or we need to build the microcode in coreboot ? > > Please advise on this. > > > > Thanks & Regards, > > Antony > > > > L&T Technology Services Ltd > > www.LntTechservices.com > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Coreboot hangs during SYS_RESET
by Antony AbeePrakash X V 07 Nov '18

07 Nov '18

Hi, We are developing coreboot (with Intel FSP) for apollo lake platform custom board. We are facing a hang issue during the SYS_RESET button press. Observations: * With soft reset the board gets hang(occurs within 2 or 3 reboot) with POST code 0x38 and the coreboot log stops during the romstage relocation. (Logs attached for Ref.) * When the SYS_RESET is pressed again the board boots and hangs at same POST code 0x38. Please provide feedback and help us to resolve this issue. Currently our coreboot build does not include any microcode (CPU_MICROCODE_CBFS_NONE). We tried to change it as "Generate from tree" in memuconfig. But the build fails with fatal error saying no microcode/microcode.h file. Whether the CPU by default have microcode ? or we need to build the microcode in coreboot ? Please advise on this. Thanks & Regards, Antony L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] Can we please remove the FSP TempRamInit option (where applicable)
by Nico Huber 07 Nov '18

07 Nov '18

Hi Lance, On 11/6/18 11:39 PM, Lance Zhao wrote: > Yes, I believe we should let mainboard to select CAR implementation instead > of force selection in soc Kconfig. I will suggest to remove that line. having a `select` for the CAR implementation is not what I had in mind but definitely something we can discuss. The current situation is _not_ that the SoC selects it, but rather that the SoC offers a choice with questionable defaults and possible settings that don't even compile. So, if we'd want to set the CAR implementation in stone per mainboard, I think we should discuss first, how to decide (as a developer that adds a mainboard) what to choose. And there is the problem: I myself don't see a choice and would always take the open-source implementation. Take FSP2.0 for instance, most SoCs currently offer a choice between: o "Enhanced Non-evict mode" o "Use FSP CAR" While I can find many arguments to select the former, I can't find any for the latter. Can you help me there? Nico PS. I presume that both options technically offer the same feature. Is there something I'm missing?

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Sorry about that.
by mad.scientist.at.large＠tutanota.com 07 Nov '18

07 Nov '18

Sorry about that, misaddressed an email.

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Re: [coreboot] coreboot Digest, Vol 165, Issue 9
by mad.scientist.at.large＠tutanota.com 07 Nov '18

07 Nov '18

Voted, no one tried to run me over this time. daytime definitely helps, though i did wind up talking to a drunken schizophrenic, but he wasn't rude to me (just other people). and i'm definitely keeping this signature line, how else can i keep more promises than i've made? "Better dead than red." Famous conservative saying..... 6. Nov 2018 15:43 by coreboot-request(a)coreboot.org <mailto:coreboot-request@coreboot.org>: > Send coreboot mailing list submissions to > > coreboot(a)coreboot.org <mailto:coreboot@coreboot.org> > > To subscribe or unsubscribe via the World Wide Web, visit > > https://mail.coreboot.org/mailman/listinfo/coreboot <https://mail.coreboot.org/mailman/listinfo/coreboot> > or, via email, send a message with subject or body 'help' to > > coreboot-request(a)coreboot.org <mailto:coreboot-request@coreboot.org> > > You can reach the person managing the list at > > coreboot-owner(a)coreboot.org <mailto:coreboot-owner@coreboot.org> > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of coreboot digest..." > > > Today's Topics: > > 1. Re: Hardware diagnostic (yanvasilij yan) > 2. New Defects reported by Coverity Scan for coreboot > (> scan-admin(a)coverity.com <mailto:scan-admin@coverity.com>> ) > 3. Re: How to get correct memory params for FSP (Alex Feinman) > 4. Re: How to get correct memory params for FSP (R S) > 5. Re: How to get correct memory params for FSP (Alex Feinman) > 6. Can we please remove the FSP TempRamInit option (where > applicable) (Nico Huber) > 7. Re: How to get correct memory params for FSP (R S) > 8. Use VBIOS from vendor's original bin file (Zvi Vered) > 9. Re: How to get correct memory params for FSP (Alex Feinman) > 10. Re: Can we please remove the FSP TempRamInit option (where > applicable) (Lance Zhao) > 11. Re: Use VBIOS from vendor's original bin file (Mike Banon) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Tue, 6 Nov 2018 16:51:49 +0500 > From: yanvasilij yan <> yanvasilij(a)gmail.com <mailto:yanvasilij@gmail.com>> > > To: > nico.h(a)gmx.de <mailto:nico.h@gmx.de> > Cc: > peter(a)stuge.se <mailto:peter@stuge.se>> , > coreboot(a)coreboot.org <mailto:coreboot@coreboot.org> > Subject: Re: [coreboot] Hardware diagnostic > Message-ID: > <> CAATv5Wb7yg3u6OLJjXr5E_iCXSn_2uXeB58_Fo-=KghN0ZAPEQ(a)mail.gmail.com <mailto:CAATv5Wb7yg3u6OLJjXr5E_iCXSn_2uXeB58_Fo-=KghN0ZAPEQ@mail.gmail.com>> > > Content-Type: text/plain; charset="utf-8" > > Thank lot too all! > > Sory for last response! > > You were right, the problem was in power up sequence. After fixing all > become correct. The 0x8086/0x0000 device disappeared, and payload > succesfuly downloaded. > > Peter Stuge, thank you for detailed comments! > > Nico Huber, thank you for active participation! > > > > ??, 28 ???. 2018 ?. ? 4:18, Nico Huber <> nico.h(a)gmx.de <mailto:nico.h@gmx.de>> >: > >> On 10/28/18 12:25 AM, Peter Stuge wrote: >> > Why are there no RAM regions? I don't know. >> >> Quite simple, because the code that adds them is tied to 8086:0f00. >> >> >> nico_h in the IRC chat noticed that in non-working board appears a >> starnge >> >> device with vid/did PCI: 00:00.0 [8086/0000]. >> > >> > The 0000 is a HUGE red sign, screaming to be thoroughly investigated. >> > >> > This also hints that the power up changes may be the problem. >> >> I agree, but note that in the datasheet (or EDS at least), the DID is >> not read-only. A strap (that I coudn't find more about) is supposed to >> set the initial value plus there is a message mentioned (to be sent to >> sth. I didn't look into) that may change it. >> >> So alternatively to diagnosing the hardware changes, you could also >> follow the bread crumbs in the documentation. >> >> Nico >> >

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coreboot November 2018