coreboot November 2018

coreboot@coreboot.org

71 participants
149 discussions

How to get correct memory params for FSP
by Alexey Borovikov 03 Nov '18

03 Nov '18

Hi. I port the Coreboot to a board with an SOC Intel Atom E3845 and use FSP for the Baytrail family. The result - postcode is 0x2A. From the descriptions on the Internet, I understand that the problem is in the incorrect memory parameters. Question: are there any utilities or methods that will help to get the correct memory parameters when working a regular BIOS from Linux or Windows systems? Many thanks!

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There are ASMB5's on fleabay right now for $30/ea (firmware storage module required for OpenBMC on the KGPE-D16/KCMA-D8)
by Taiidan＠gmx.com 03 Nov '18

03 Nov '18

(This is the firmware storage module required to use OpenBMC on the KGPE-D16/KCMA-D8 boards - with it at last one can have feature equivalency with a proprietary system) Great opportunity if you need but don't have one - they appear to be brand new. Raptor says either the ASMB4 or the ASMB5 will work. While the facebook version of OpenBMC is stripped down (they used that one for smaller firmware size afaik) and not as nice as the IBM OpenBMC found on the various OpenPOWER machines it is still secure and much nicer than the exploit filled default BMC firmware from ASUS.

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Re: [coreboot] Status Update of F2A85M
by kinky_nekoboi 02 Nov '18

02 Nov '18

I tried only the one included in current master tree. But CBFS reports me an 0KB blob as an output ... so that its mostlikele the reason it halts after boot (maybe updating an not working microcode to the cpu than ?) i have microcodes enabled per linux kernel update dmesg | grep microcode: [ 3.794585] microcode: CPU0: patch_level=0x0600110f [ 3.794588] microcode: CPU1: patch_level=0x0600110f [ 3.794595] microcode: CPU2: patch_level=0x0600110f [ 3.794602] microcode: CPU3: patch_level=0x0600110f [ 3.794653] microcode: Microcode Update Driver: v2.2. Am 02.11.2018 um 17:12 schrieb Mike Banon: > Which microcode gives you a brick? Have you tried those new 2018 > microcodes (not merged yet to coreboot) for 15h generation - > https://review.coreboot.org/c/coreboot/+/28273 ? If not, here is a > quick & secure way to get them - > http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#AMD_microcode_upda… > (although this script is at "Lenovo G505S hacking" page, the same > microcodes should work for desktop Richland CPUs as well) . By the > way, it could help you to get your hardware virtualization (IOMMU) > working > On Fri, Nov 2, 2018 at 7:06 PM kinky_nekoboi > <kinky_nekoboi(a)bluetardis.de> wrote: >> Hi Mike, i hope i can help u i am just a User of coreboot and noo skilled coreboot hacker yet lol. >> The A10-6800K should work as its the same CPU core/ gen. >> do not include microcode it makes the rom a brick mode. >> U have to add a VGA bios if u are using the Internal GPU. >> i am using a F2A85M rev 1.1 (not pro and not LE, they are quite rare) >> >> Am 2. November 2018 17:01:24 MEZ schrieb Mike Banon <mikebdp2(a)gmail.com>: >>> Nice report. Do you think A10-6800K CPU would have worked at this >>> motherboard? Or only A8-6600K is supported? Also, what hardware >>> revision of this motherboard do you have? (there were F2A85M / --//-- >>> PRO and some other revisions, so I'm a bit confused) . I am seriously >>> considering doing a similar build, but would like to get the fastest >>> available CPU you could install there >>> On Fri, Nov 2, 2018 at 4:29 AM kinky_nekoboi >>> <kinky_nekoboi(a)bluetardis.de> wrote: >>>> >>>> something like that happens if u connect anything to a USB2 Port >>>> >>>> [ 2600.001601] usb 7-1: new full-speed USB device number 3 using ohci-pci >>>> [ 2600.001612] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2600.001619] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2600.001624] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2600.185864] usb 7-1: device descriptor read/64, error -11 >>>> [ 2600.293659] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2600.293669] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2600.293674] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2600.477668] usb 7-1: device descriptor read/64, error -11 >>>> [ 2600.585647] usb usb7-port1: attempt power cycle >>>> [ 2601.090486] usb 7-1: new full-speed USB device number 4 using ohci-pci >>>> [ 2601.090494] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2601.301659] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2601.509672] usb 7-1: device not accepting address 4, error -11 >>>> [ 2601.693678] usb 7-1: new full-speed USB device number 5 using ohci-pci >>>> [ 2601.693693] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2601.901677] ohci-pci 0000:00:12.0: dma_direct_map_page: overflow 0x00000001c52c2ea8+8 of device mask ffffffff >>>> [ 2602.109672] usb 7-1: device not accepting address 5, error -11 >>>> [ 2602.109723] usb usb7-port1: unable to enumerate USB device >>>> >>>> >>>> Am 02.11.2018 um 02:01 schrieb kinky_nekoboi: >>>> >>>> heeey >>>> >>>> i am very happy that i have coreboot running now on my desktop machine... >>>> >>>> ADDON-GPU card works now >>>> >>>> Nvramcui works >>>> >>>> Optionrom execution works. >>>> >>>> IOMMU does not work .. debian has to boot with iommu=off. >>>> >>>> but KVM virtualsation works somehow. >>>> >>>> Suspend does not work. >>>> >>>> USB is still extremely buggy ... only the USB3 Ports are useable. >>>> >>>> >>>> here some output >>>> >>>> Architektur: x86_64 >>>> CPU Operationsmodus: 32-bit, 64-bit >>>> Byte-Reihenfolge: Little Endian >>>> CPU(s): 4 >>>> Liste der Online-CPU(s): 0-3 >>>> Thread(s) pro Kern: 2 >>>> Kern(e) pro Socket: 2 >>>> Sockel: 1 >>>> NUMA-Knoten: 1 >>>> Anbieterkennung: AuthenticAMD >>>> Prozessorfamilie: 21 >>>> Modell: 19 >>>> Modellname: AMD A8-6600K APU with Radeon(tm) HD Graphics >>>> Stepping: 1 >>>> CPU MHz: 2068.754 >>>> Maximale Taktfrequenz der CPU: 3900,0000 >>>> Minimale Taktfrequenz der CPU: 1900,0000 >>>> BogoMIPS: 7786.16 >>>> Virtualisierung: AMD-V >>>> L1d Cache: 16K >>>> L1i Cache: 64K >>>> L2 Cache: 2048K >>>> NUMA-Knoten0 CPU(s): 0-3 >>>> Markierungen: fpu vme de pse tsc msr pae mce cx8 apic >>>> sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx >>>> mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc >>>> cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 >>>> sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic >>>> cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt >>>> lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb cpb >>>> hw_pstate ssbd vmmcall bmi1 arat npt lbrv svm_lock nrip_save tsc_scale >>>> vmcb_clean flushbyasid decodeassists pausefilter pfthreshold >>>> >>>> >>>> 23 entries total: >>>> >>>> 0:1st timestamp 13,116 >>>> 1:start of romstage 13,477 (361) >>>> 2:before ram initialization 75,515 (62,038) >>>> 3:after ram initialization 1,308,025 (1,232,510) >>>> 4:end of romstage 1,319,893 (11,867) >>>> 8:starting to load ramstage 1,319,966 (73) >>>> 15:starting LZMA decompress (ignore for x86) 1,319,984 (18) >>>> 16:finished LZMA decompress (ignore for x86) 1,370,088 (50,103) >>>> 9:finished loading ramstage 1,370,357 (269) >>>> 10:start of ramstage 1,371,078 (720) >>>> 30:device enumeration 1,461,571 (90,493) >>>> 40:device configuration 1,470,758 (9,186) >>>> 50:device enable 1,501,692 (30,933) >>>> 60:device initialization 1,569,453 (67,761) >>>> 65:Option ROM initialization 1,769,162 (199,708) >>>> 65:Option ROM initialization 1,936,860 (167,697) >>>> 70:device setup done 2,011,094 (74,234) >>>> 75:cbmem post 2,366,967 (355,873) >>>> 80:write tables 2,371,915 (4,947) >>>> 85:finalize chips 2,750,289 (378,374) >>>> 90:load payload 2,755,411 (5,122) >>>> 15:starting LZMA decompress (ignore for x86) 2,797,472 (42,060) >>>> 16:finished LZMA decompress (ignore for x86) 2,823,100 (25,628) >>>> 99:selfboot jump 2,838,148 (15,048) >>>> >>>> Total Time: 2,825,023 >>>> >>>> >>>> >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] [LinuxBoot] FOSDEM 2019 deadline today
by David Hendricks 02 Nov '18

02 Nov '18

On Fri, Nov 2, 2018 at 9:15 AM 'Ron Minnich' via linuxboot < linuxboot(a)googlegroups.com> wrote: > I"m leaning to yes, by which I mean if you do it, I'll show up. > > I can't believe I said that. > On Fri, Nov 2, 2018 at 7:20 AM Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > > Hi! > > > > FOSDEM next year will be on 2 & 3 February 2019. > > The deadline for applying for a stand is today. > > Do we want a coreboot/flashrom/LinuxBoot stand/booth? > Same as what Ron said. I think someone from FB can be there to talk about coreboot/LinuxBoot stuff and perhaps bring some hardware to demo.

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FOSDEM 2019 deadline today
by Carl-Daniel Hailfinger 02 Nov '18

02 Nov '18

Hi! FOSDEM next year will be on 2 & 3 February 2019. The deadline for applying for a stand is today. Do we want a coreboot/flashrom/LinuxBoot stand/booth? There will be a hardware enablement devroom as well, and we might be able to participate there, but that's not necessarily giving us a chance to talk to people all day. Regards, Carl-Daniel

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Status Update of F2A85M
by kinky_nekoboi 02 Nov '18

02 Nov '18

heeey i am very happy that i have coreboot running now on my desktop machine... ADDON-GPU card works now Nvramcui works Optionrom execution works. IOMMU does not work .. debian has to boot with iommu=off. but KVM virtualsation works somehow. Suspend does not work. USB is still extremely buggy ... only the USB3 Ports are useable. here some output Architektur: x86_64 CPU Operationsmodus: 32-bit, 64-bit Byte-Reihenfolge: Little Endian CPU(s): 4 Liste der Online-CPU(s): 0-3 Thread(s) pro Kern: 2 Kern(e) pro Socket: 2 Sockel: 1 NUMA-Knoten: 1 Anbieterkennung: AuthenticAMD Prozessorfamilie: 21 Modell: 19 Modellname: AMD A8-6600K APU with Radeon(tm) HD Graphics Stepping: 1 CPU MHz: 2068.754 Maximale Taktfrequenz der CPU: 3900,0000 Minimale Taktfrequenz der CPU: 1900,0000 BogoMIPS: 7786.16 Virtualisierung: AMD-V L1d Cache: 16K L1i Cache: 64K L2 Cache: 2048K NUMA-Knoten0 CPU(s): 0-3 Markierungen: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb cpb hw_pstate ssbd vmmcall bmi1 arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold 23 entries total: 0:1st timestamp 13,116 1:start of romstage 13,477 (361) 2:before ram initialization 75,515 (62,038) 3:after ram initialization 1,308,025 (1,232,510) 4:end of romstage 1,319,893 (11,867) 8:starting to load ramstage 1,319,966 (73) 15:starting LZMA decompress (ignore for x86) 1,319,984 (18) 16:finished LZMA decompress (ignore for x86) 1,370,088 (50,103) 9:finished loading ramstage 1,370,357 (269) 10:start of ramstage 1,371,078 (720) 30:device enumeration 1,461,571 (90,493) 40:device configuration 1,470,758 (9,186) 50:device enable 1,501,692 (30,933) 60:device initialization 1,569,453 (67,761) 65:Option ROM initialization 1,769,162 (199,708) 65:Option ROM initialization 1,936,860 (167,697) 70:device setup done 2,011,094 (74,234) 75:cbmem post 2,366,967 (355,873) 80:write tables 2,371,915 (4,947) 85:finalize chips 2,750,289 (378,374) 90:load payload 2,755,411 (5,122) 15:starting LZMA decompress (ignore for x86) 2,797,472 (42,060) 16:finished LZMA decompress (ignore for x86) 2,823,100 (25,628) 99:selfboot jump 2,838,148 (15,048) Total Time: 2,825,023

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 02 Nov '18

02 Nov '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1396558: Control flow issues (MISSING_BREAK) /src/mainboard/google/poppy/variants/nami/mainboard.c: 238 in variant_devtree_update() ________________________________________________________________________________________________________ *** CID 1396558: Control flow issues (MISSING_BREAK) /src/mainboard/google/poppy/variants/nami/mainboard.c: 238 in variant_devtree_update() 232 switch (sku_id) { 233 case SKU_0_SONA: 234 case SKU_1_SONA: 235 case SKU_0_SYNDRA: 236 case SKU_1_SYNDRA: 237 case SKU_2_SYNDRA: >>> CID 1396558: Control flow issues (MISSING_BREAK) >>> The case for value "179296U" is not terminated by a 'break' statement. 238 case SKU_3_SYNDRA: 239 pl2_id = PL2_ID_SONA_SYNDRA; 240 case SKU_0_VAYNE: 241 case SKU_1_VAYNE: 242 case SKU_2_VAYNE: 243 case SKU_0_PANTHEON: ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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CoffeeLake RVP master: Code changed... How to enable SATA and LAN?
by Jose Trujillo 02 Nov '18

02 Nov '18

Hello coreboot developers: Looks that coreboot development has been very active lately integrating FSP, adding new platforms and getting ready for the 4.9 release. And also I can see new payloads "WOW" (like LinuxBoot, Yabits)... what a revolution of features and code. I am using coreboot "master" from yesterday and using CoffeeLake RVP tree on my CoffeeLake H (non RVP) system and reconfiguring . I am in the process of testing the functionality of coreboot on my devices and I know I need to wait for the release. I am trying to figure out how is going to be the way of enabling SATA and LAN (and other devices) on the platforms with renewed code. 1.- In "device pci" list of devicetree.cb file (that previously had issues). 2.- As register in devicetree.cb (EnableLan and EnableSata no longer works). 3.- Kconfig or somewere else. I am trying several ways to enable LAN and SATA in the "user domain" code but failed. Unless I still have something not configured correctly I would like to know the right way of enable those devices. Thank you all, Jose.

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[G505S] Discrete GPU - trying to configure PCI correctly, need your help
by Mike Banon 01 Nov '18

01 Nov '18

Finally we have succeeded in forcing coreboot to enable AMD discrete GPU of Lenovo G505S and load its' AtomBIOS ROM there :-) (see P.S.) But that's not enough - seems that a correct PCI config is needed! Otherwise, without a nomodeset option there is a strange kernel panic at the very beginning of booting, and with nomodeset this dGPU is simply disabled at Linux - later modprobe'ing a driver doesn't work. We will appreciate if you could take a quick glance and tell what PCI config space bits are wrong there, and we will try a hack of multiple config space writes according to your ideas coreinfo_pci_with_0_02_00_enabled - extracted with coreinfo before trying to boot Linux 1) Bridge (enabled) .C. 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00: 22 10 12 14 07 00 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 11 11 00 00 20: 00 F0 00 F0 01 E0 F1 EF 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 03 00 40: all 00's 50: 01 58 03 C8 00 00 00 00 10 A0 42 01 21 80 00 00 60: 30 28 00 00 02 0D 70 00 00 00 82 B0 00 00 04 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 1F 00 70 00 80: 06 80 00 00 06 00 00 00 02 00 00 00 00 00 00 00 90: all 00's A0: 05 B0 80 00 00 00 00 00 00 00 00 00 00 00 00 00 B0: 0D B8 00 00 22 10 34 12 08 00 03 A8 00 00 00 00 C0-D0: all 00's E0: 50 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 F0: all 00's 2) Discrete GPU (R5 M230) behind the bridge .F. 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00: 02 10 65 66 03 00 10 00 00 00 80 03 10 00 00 00 10: 0C 00 00 E0 00 00 00 00 04 00 00 F0 00 00 00 00 20: 01 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 04 F0 48 00 00 00 00 00 00 00 00 01 00 00 40: 00 00 00 00 00 00 00 00 09 50 08 00 00 00 00 00 50: 01 58 03 76 00 00 00 00 10 A0 12 00 A1 8F 00 00 60: 30 28 00 00 82 0C 40 00 00 00 82 10 00 00 00 00 70: all 00's 80: 00 00 00 00 0E 00 00 00 02 00 00 00 00 00 00 00 90: all 00's A0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 B0-F0: all 00's If more info is needed, all the PCI config spaces and their differences are highlighted at this "hybrid PDF" (editable with LibreOffice Writer), view it in your web browser here - https://github.com/mikebdp2/coreboot-related/blob/master/PCI.pdf - also attached to an e-mail. There are the pages like "dont_enable_bridge_and_let_it_configure_in_linux : normalmode vs nomodeset", "coreinfo_PCI_with_0_02_00_enabled" and also the PCI config spaces of proprietary UEFI normalmode - discrete GPU is working there! - as well as UEFI nomodeset (to get an understanding what normalmode vs nomodeset differences are acceptable and maybe try to apply this logic to coreboot's situation to understand how a coreboot's normalmode could have looked if no kernel panic) . UEFI config space can't be copied blindly because e.g. a different ROM address is OK and should be preserved , but some bits could be borrowed to ensure a correct configuration. P.S. 1) discrete GPU = PCI device 01:00.0 / 04:00.0 with VID,PID=1002,6665 (for R5 M230) - or ,6663 (for HD 8570M) - is behind a PCI bridge 00:02.0 with VID,PID=1022,1412 . At coreboot/src/mainboard/lenovo/g505s/devicetree.cb there is a line 32 : device pci 2.0 off end ===> Change it to device pci 2.0 on end 2) at ./coreboot/src/device/pci_device.c --> pci_dev_init, lines 784-787: /* Only execute VGA ROMs. */ if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) return; PCI device classes are declared at ./coreboot/src/include/device/pci_ids.h , e.g. lines 31-35 : #define PCI_BASE_CLASS_DISPLAY 0x03 #define PCI_CLASS_DISPLAY_VGA 0x0300 #define PCI_CLASS_DISPLAY_XGA 0x0301 #define PCI_CLASS_DISPLAY_3D 0x0302 #define PCI_CLASS_DISPLAY_OTHER 0x0380 Inserted printk's told us that dev->class for dGPU is 28672 = 0x38000 , right shift by 8 bits : ( 0x38000 >> 8 ) = 0x0380 - this is PCI_CLASS_DISPLAY_OTHER . Expanded the code above to /* Only execute VGA ROMs. */ if ((((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))&&(((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER))) { printk(BIOS_DEBUG, "((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA), PCI_CLASS_DISPLAY_OTHER also\n"); return; } and now it loads the AtomBIOS ROM on a discrete GPU also (but a correct PCI config is still needed to get it working, please see above) Best regards, Mike Banon

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coreboot November 2018