coreboot November 2018

coreboot@coreboot.org

71 participants
149 discussions

Re: [coreboot] Supported Motherboards
by Nico Huber 09 Nov '18

09 Nov '18

On 11/8/18 3:29 PM, Mike Banon wrote: > Please consider AMD Lenovo G505S laptop: all the hardware > virtualizations AMD-V / SLAT / IOMMU are fully supported there > (although you have to install a microcode update to avoid the possible > glitches), no Intel ME / AMD PSP, quad-core CPU, 16GB DDR3 RAM > possible, recent build_status report, Please avoid the G505s if possible. There might be neither ME nor PSP, but that just means the controllers that are known and researched are absent (it doesn't tell you anything about less researched ones). Also, if you want to use its integrated graphics, you can't run fully free software (not even on the main CPU) because AMD graphics driver develo- pers force you to put a usually proprietary AtomBIOS into your firmware. The Linux radeon/amdgpu drivers are only open source because they hide the proprietary parts in the host firmware (BIOS/coreboot, not some firmware that runs on the gfx processor). > and there's a cosy community > around it and we intend to support it for a looong time - as long as > all our G505S last That's good to hear. But here comes a warning: The G505s still uses AGESA (a hard to maintain AMD reference code). This (and actually the native coreboot AMD code too) might get moved away from our master branch after any release. I believe it's only a question of time until coreboot maintainers are finally fed up with it*. A good solution would be to write native coreboot code for this platform from scratch. Something at least of the quality of intel/x4x (and the compatible southbridges) would be much appreciated and would likely maintain itself for some years. Nico * The last time I worked on a bigger patch set in my spare time, I nearly gave up after some nights of work because of the unmain- tainable mess around {cpu,nb,sb}/amd/. It's dragging the whole project down, IMHO.

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T430s prop BIOS Image
by Maillist 09 Nov '18

09 Nov '18

Hey Guys, does anyone happen to have a t430s bios image? I kinda had way to much mate this morning, so i was a little bit to enthusiastically while desoldering and ripped the WSON-8 chip from the board. I soldered wires to the pins, but wasnt able to recover the image, and without ifd, i cant build coreboot. cheers

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Re: [coreboot] Using LPC bus serial interrupts
by Nico Huber 09 Nov '18

09 Nov '18

Hi Vasily, On 11/9/18 6:25 AM, yanvasilij yan wrote: > PIRQ_PIC(C, 7), \ this is likely the culprit. Tony mentioned you must make sure that IRQ7 isn't used by PCI devices. Which was also my original suspicion, but the datasheet doesn't mention that :-/ Nico

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Re: [coreboot] Video not seen with BayTrail-I platform Board which has DVI/HDMI interface
by Jose Trujillo 09 Nov '18

09 Nov '18

I never needed to make changes to vga.dat on my E3845 system. The vga.dat was taken from the FSP package the same as you. The coreboot version that I used was 4.7. ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Thursday, November 8, 2018 2:02 PM, galla rao <galla.rao80(a)gmail.com> wrote: > Hi Jose, > > Thanks for a quick response > > Enabled framebuffer in Config as given in inserted picture and am using uefipayload but not seabios > > [image.png] > > To add more to this > > MinnowMax + VGA -> Display is seen > BayleyBay + VGA -> Display is not seen > > Does the FSP-master\FSP-master\BayTrailFspBinPkg\Vbios\vga.dat needs any change? > > Do you think in the hardware the DDI0, DDI1 pins and clk/data can have an impact and needs to be measured > > Regards > Ranga > > On Thu, Nov 8, 2018 at 10:16 AM Jose Trujillo <ce.autom(a)protonmail.com> wrote: > >> Hello Ranga: >> >> If you are using tianocore as payload you should choose vesa framebuffer option and text mode in seabios >> JT >> >> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ >> On Thursday, November 8, 2018 1:08 PM, galla rao <galla.rao80(a)gmail.com> wrote: >> >>> Hi All, >>> >>> Am facing Gfx Enablement failure, i don't see any Video output on my screen >>> >>> Config file has below settings >>> >>> CONFIG_VGA_BIOS_ID="8086,0f31" >>> CONFIG_DRIVERS_PS2_KEYBOARD is not set >>> CONFIG_ONBOARD_VGA_IS_PRIMARY=y >>> CONFIG_VGA_BIOS=y >>> CONFIG_UDELAY_IO is not set >>> CONFIG_DCACHE_RAM_BASE=0xfef00000 >>> CONFIG_DCACHE_RAM_SIZE=0x4000 >>> CONFIG_ACPI_SSDTX_NUM=0 >>> CONFIG_VGA_BIOS_FILE="../intel/cpu/baytrail/vbios/Vga.dat" >>> CONFIG_PCI_64BIT_PREF_MEM is not set >>> >>> BIOS log specific to Video output onto terminal >>> >>> ------------------------ VLV SSA Platform Policy dump Begin --------------- >>> Graphics Configuration: >>> GttSize : 2 MB >>> IgdDvmt50PreAlloc : 2 >>> PrimaryDisplay : 0 >>> ApertureSize : 2 >>> Turbo Enable : 1 >>> >>> IGD enabled. >>> >>> dGFXBase = 0x7BE00000 >>> >>> Do i need to configure any setting in \FSP-master\FSP-master\BayTrailFspBinPkg\Vbios\vga.bsf file from BCT? >>> >>> Please let me know what could be the reason and if anyone has seen such behavior earlier >>> >>> Best Regards >>> Ranga

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Re: [coreboot] Using LPC bus serial interrupts
by yanvasilij yan 09 Nov '18

09 Nov '18

Hello, Tony Marchini! Thank you for response! To configure LPC I made: 1) Added line to devicetree: ... device pci 1f.0 on end # 8086 0F1C - LPC bridge ... 2) Enabled alternative function for gpio pins: GPIO_FUNC1, // GPIO_S0_SC[042] - ILB_LPC_AD[0] GPIO_FUNC1, // GPIO_S0_SC[043] - ILB_LPC_AD[1] GPIO_FUNC1, // GPIO_S0_SC[044] - ILB_LPC_AD[2] GPIO_FUNC1, // GPIO_S0_SC[045] - ILB_LPC_AD[3] GPIO_FUNC1, // GPIO_S0_SC[046] - ILB_LPC_FRAME GPIO_FUNC1, // GPIO_S0_SC[047] - ILB_LPC_CLK[0] GPIO_NC, // GPIO_S0_SC[048] - No Connect GPIO_FUNC1, // GPIO_S0_SC[049] - ILB_LPC_CLKRUN GPIO_FUNC1, // GPIO_S0_SC[050] - ILB_LPC_SERIRQ 3) irqrout.h (was taken from MinnowMax): #define BRIDGE1_DEV PCIE_DEV #define PCIE_BRIDGE_IRQ_ROUTES \ PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) #define PCI_DEV_PIRQ_ROUTES \ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) #define PIRQ_PIC_ROUTES \ PIRQ_PIC(A, 3), \ PIRQ_PIC(B, 5), \ PIRQ_PIC(C, 7), \ PIRQ_PIC(D, 10), \ PIRQ_PIC(E, 11), \ PIRQ_PIC(F, 12), \ PIRQ_PIC(G, 14), \ PIRQ_PIC(H, 15) 4) In /coreboot/src/soc/intel/fsp_baytrail/southcluster.c enabled SETUPSERIQ and CONFIG_SERIRQ_CONTINUOUS_MODE to 1. Does it enought? Regrads, Vasily

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Re: [coreboot] Video not seen with BayTrail-I platform Board which has DVI/HDMI interface
by Nico Huber 08 Nov '18

08 Nov '18

Hello Ranga, On 11/8/18 12:02 PM, galla rao wrote: > Does the FSP-master\FSP-master\BayTrailFspBinPkg\Vbios\vga.dat needs any > change? this Video BIOS includes a VBT (Video BIOS Table) full of options (Vga.bsf in the same directory describes all of them). You usually use a VBT that is adapted to your mainboard (or adapt it yourself using Intels binary modification tool and that .bsf file). Best option is probably to find a VBIOS or VBT for BayleyBay and use that. Hope that helps, Nico

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Re: [coreboot] Using LPC bus serial interrupts
by Tony Marchini 08 Nov '18

08 Nov '18

Assuming you are generating the serial IRQ stream to the CPU correctly, if you are using IRQ7 , then you need to make sure the IRQ 7 isn't being assigned to any PCI devices. You need to eliminate and IRQs you want from the LPC from the PIRQ table. There are also some configuration of the 8259 for level vs edge triggering. Also, it is handy for the SERIRQ to be in continuous mode. Sincerely, Anthony A. Marchini Software Engineer

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Re: [coreboot] Status Thinkpad T410
by kinky_nekoboi 08 Nov '18

08 Nov '18

I have hardware to test, T410 with intel gpu + little flashing tool collection. i am waiting for instructions Am 8. November 2018 17:30:00 MEZ schrieb Peter Lemenkov <lemenkov(a)gmail.com>: >Hello! > >чт, 8 нояб. 2018 г. в 10:50, Angel Pons <th3fanbus(a)gmail.com>: >> >> Hello nekoboi, >> >> On Thu, Nov 8, 2018, 10:39 kinky_nekoboi <kinky_nekoboi(a)bluetardis.de >wrote: >>> >>> is there any work going on in the T410 Port ? >>> >>> Hardware is simular to X201 >>> >>> I heard some people succesfully flashed x201 roms. >> >> >> I recall seeing a gerrit patch for it, though it is old. I would work >on it but I don't have any Thinkpad (let alone a T410). > >Btw I've updated recently both t410 and t410s patches from gerrit >according to the recent coreboot changes, but I've got the same story >- I don't have hardware to test. > > >-- >With best regards, Peter Lemenkov.

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Re: [coreboot] Status Thinkpad T410
by Peter Lemenkov 08 Nov '18

08 Nov '18

Hello! чт, 8 нояб. 2018 г. в 10:50, Angel Pons <th3fanbus(a)gmail.com>: > > Hello nekoboi, > > On Thu, Nov 8, 2018, 10:39 kinky_nekoboi <kinky_nekoboi(a)bluetardis.de wrote: >> >> is there any work going on in the T410 Port ? >> >> Hardware is simular to X201 >> >> I heard some people succesfully flashed x201 roms. > > > I recall seeing a gerrit patch for it, though it is old. I would work on it but I don't have any Thinkpad (let alone a T410). Btw I've updated recently both t410 and t410s patches from gerrit according to the recent coreboot changes, but I've got the same story - I don't have hardware to test. -- With best regards, Peter Lemenkov.

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Re: [coreboot] Supported Motherboards
by Kinky Nekoboi 08 Nov '18

08 Nov '18

seems like it was quite silent around these board in the mailing list except my emails. the first rom i test was send me by vidwer(a)gmail.com it was labeled coreboot_asus_f2a85-m_1532513585.rom .. i dont know if this is the commit code of it. this one was working it think also with IOMMU but it was not able to drive a radeon addon card. Does someone no who was working on this boards first .. in the past the original developer of a port could help me with some problems. Am 08.11.18 um 15:48 schrieb Mike Banon: > A10-5750M CPU of AMD Lenovo G505S laptop is from the same Richland 15h > family as your F2A85M-* , and its' southbridge A76M should be also > very similar to what you have: its' Bolton-M3 but there's a relatively > small difference between these Bolton and Hudson since they are from > the same family of FCH ( > https://en.wikipedia.org/wiki/List_of_AMD_chipsets#Fusion_controller_hubs_(… > ) . Although I don't know why your IOMMU isn't working and why these > Raminit problems are happening, its definitely possible to fix them, > maybe even by wisely borrowing some of G505S specific source code > (comparing the sources and trying to borrow some sources your board > might be lacking). In addition, try looking through the mailing lists > / board_status reports to find the people who have the same > motherboard as you and CC them your e-mails in case they aren't > subscribed to coreboot mailing list; maybe they could tell you some > useful info: e.g. what if IOMMU and Raminit were working before but > got broken by some bad commit; if you'd know that some of this has > been working before together with an approximate date, it'd be > possible to triangulate the "things-breaking" commit by doing the > dichotomy (e.g. it should take just 10 tries to go through 1024 > commits and find which one broke it) > > Best regards, > Mike Banon > On Thu, Nov 8, 2018 at 5:33 PM kinky_nekoboi > <kinky_nekoboi(a)bluetardis.de> wrote: >> >> hello mike that are great news! >> it would be nice if this success would benefit the hudson boards (f2a85m-*) too. >> IOMMU and Raminit(no dual channel) >> even with microcode are still buggy as hell. But at least this port makes my home workstation as fast and blobfree as possible. >> >> greetings >> the nekoboi >> >> Am 8. November 2018 15:29:05 MEZ schrieb Mike Banon <mikebdp2(a)gmail.com>: >>> >>> Please consider AMD Lenovo G505S laptop: all the hardware >>> virtualizations AMD-V / SLAT / IOMMU are fully supported there >>> (although you have to install a microcode update to avoid the possible >>> glitches), no Intel ME / AMD PSP, quad-core CPU, 16GB DDR3 RAM >>> possible, recent build_status report, and there's a cosy community >>> around it and we intend to support it for a looong time - as long as >>> all our G505S last >>> >>> Best regards, >>> Mike Banon >>> On Thu, Nov 8, 2018 at 1:37 AM Timothy Pearson >>> <tpearson(a)raptorengineering.com> wrote: >>>> >>>> > On 11/07/2018 01:56 PM, kinky_nekoboi wrote: > >>>>> > >>>>> sounds promissing i will give it a deeper look later. > >>>>> this makes the SNB/IVY platform much more attractive to me. > >>>>> thx for the information. > > > Be aware there's still an Intel ME requirement for those platforms; > while they are old enough that the ME can be significantly reduced, it > cannot be completely eliminated. > >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> https://mail.coreboot.org/mailman/listinfo/coreboot >

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coreboot November 2018