coreboot October 2018

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145 discussions

Post code 0xCE: coreboot.rom with fsp
by Zvi Vered 10 Oct '18

10 Oct '18

Hello, After selecting "Use Intel Firmware Support Package" and specified fsp file, I got post code: 0xCE Before using this FSP I got post code: 0xb0 Where can I find documentation for those post codes ? Thank you, Zvika

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Watchdog timer (WDT) support on Kabylake w/FSP2.0
by Matt DeVillier 10 Oct '18

10 Oct '18

greetings! I'm trying to enable WDT support for Kabylake Chromeboxes (google/fizz) but not having any luck. The current SoC code doesn't expose the FSP fields which appear to control this (WdtDisableAndLock, WatchDog, WatchDogTimerOS, WatchDogTimerBIOS), so I added them to chip_fsp20.c and set them accordingly in devicetree (though it's unclear what the values of WatchDogTimerOS/WatchDogTimerBIOS are to be, the documentation doesn't state if this is a timeout value, units, etc). Still, I'm unable to remotely trigger a reset via /dev/watchdog0. Has anyone else used this feature, or have any insight as to the proper FSP settings? AIUI this works properly on older non-FSP Chromeboxes (Haswell/Broadwell) cheers, Matt

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post code 0xb0 after coreboot.rom BIOs burn
by Zvi Vered 09 Oct '18

09 Oct '18

Hello, After injecting coreboot.rom into the original bin file + boot I got post code 0xb0. Can you tell what does it mean ? I modified devicetree.cb accorindg to lspci + superiotool. In romstage.c I added: post_code(0x30); in early_mainboard_romstage_entry post_code(0x31); in late_mainboard_romstage_entry I did not modiled FSP yet. Is it possible that 0xb0 was sent from a code not developed in ELAT Thank you, Zvika

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 09 Oct '18

09 Oct '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 9 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 9 of 9 defect(s) ** CID 1396055: Incorrect expression (SIZEOF_MISMATCH) /src/drivers/generic/generic/generic.c: 67 in generic_autogen_name() ________________________________________________________________________________________________________ *** CID 1396055: Incorrect expression (SIZEOF_MISMATCH) /src/drivers/generic/generic/generic.c: 67 in generic_autogen_name() 61 char *name = &config->autogen_name[0]; 62 static unsigned int id; 63 64 if (name[0] != '\0') 65 return name; 66 >>> CID 1396055: Incorrect expression (SIZEOF_MISMATCH) >>> Passing argument "name" of type "char *" and argument "4UL /* sizeof (name) */" to function "snprintf" is suspicious. 67 snprintf(name, sizeof(name), "G%03.3X", id++); 68 name[4] = '\0'; 69 return name; 70 } 71 72 static const char *generic_dev_acpi_name(const struct device *dev) ** CID 1396054: Null pointer dereferences (NULL_RETURNS) ________________________________________________________________________________________________________ *** CID 1396054: Null pointer dereferences (NULL_RETURNS) /src/drivers/generic/generic/generic.c: 38 in generic_dev_fill_ssdt_generator() 32 33 if (!config->hid) { 34 printk(BIOS_ERR, "%s: ERROR: _HID required\n", dev_path(dev)); 35 return; 36 } 37 >>> CID 1396054: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a pointer that might be null "acpi_device_scope(dev)" when calling "acpigen_write_scope". 38 acpigen_write_scope(acpi_device_scope(dev)); 39 acpigen_write_device(acpi_device_name(dev)); 40 acpigen_write_name_string("_HID", config->hid); 41 if (config->cid) 42 acpigen_write_name_string("_CID", config->cid); 43 acpigen_write_name_integer("_UID", config->uid); ** CID 1396053: Parse warnings (PARSE_ERROR) /src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c: 652 in () ________________________________________________________________________________________________________ *** CID 1396053: Parse warnings (PARSE_ERROR) /src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c: 652 in () 646 } __packed; 647 648 struct lp0_header header __attribute__((section(".header"))) = 649 { 650 .length_insecure = (uintptr_t)&blob_total_size, 651 .length_secure = (uintptr_t)&blob_total_size, >>> CID 1396053: Parse warnings (PARSE_ERROR) >>> identifier "blob_data" is undefined 652 .destination = (uintptr_t)&blob_data, 653 .entry_point = (uintptr_t)&lp0_resume, 654 .code_length = (uintptr_t)&blob_data_size ** CID 1396052: (RESOURCE_LEAK) /util/intelvbttool/intelvbttool.c: 993 in fix_vbios_checksum() /util/intelvbttool/intelvbttool.c: 998 in fix_vbios_checksum() ________________________________________________________________________________________________________ *** CID 1396052: (RESOURCE_LEAK) /util/intelvbttool/intelvbttool.c: 993 in fix_vbios_checksum() 987 if (!fo) { 988 printerr("%s open failed\n", filename); 989 return 1; 990 } 991 992 if (fo->size < sizeof(optionrom_header_t)) >>> CID 1396052: (RESOURCE_LEAK) >>> Variable "fo" going out of scope leaks the storage it points to. 993 return 1; 994 995 optionrom_header_t *oh = (optionrom_header_t *)fo->data; 996 997 if (oh->size * 512 > fo->size) 998 return 1; /util/intelvbttool/intelvbttool.c: 998 in fix_vbios_checksum() 992 if (fo->size < sizeof(optionrom_header_t)) 993 return 1; 994 995 optionrom_header_t *oh = (optionrom_header_t *)fo->data; 996 997 if (oh->size * 512 > fo->size) >>> CID 1396052: (RESOURCE_LEAK) >>> Variable "fo" going out of scope leaks the storage it points to. 998 return 1; 999 1000 /* fix checksum */ 1001 oh->checksum = -(checksum_vbios(oh) - oh->checksum); 1002 1003 if (write_file(filename, fo)) { ** CID 1396051: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /util/intelvbttool/intelvbttool.c: 394 in read_file() ________________________________________________________________________________________________________ *** CID 1396051: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /util/intelvbttool/intelvbttool.c: 394 in read_file() 388 printerr("%s seek failed: %s\n", filename, strerror(errno)); 389 fclose(fd); 390 return NULL; 391 } 392 393 const off_t size = ftell(fd); >>> CID 1396051: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "size > 18446744073709551615UL" is always false regardless of the values of its operands. This occurs as the logical second operand of "||". 394 if (size < 0 || size > SIZE_MAX) { 395 printerr("%s tell failed: %s\n", filename, strerror(errno)); 396 fclose(fd); 397 return NULL; 398 } 399 ** CID 1396050: Resource leaks (RESOURCE_LEAK) /util/intelvbttool/intelvbttool.c: 794 in parse_vbt() ________________________________________________________________________________________________________ *** CID 1396050: Resource leaks (RESOURCE_LEAK) /util/intelvbttool/intelvbttool.c: 794 in parse_vbt() 788 if (!bdb_head->header_size || bdb_head->header_size > fo->size) { 789 printerr("invalid BDB header size\n"); 790 return; 791 } 792 793 /* Duplicate fo as caller is owner and remalloc frees the object */ >>> CID 1396050: Resource leaks (RESOURCE_LEAK) >>> Failing to save or free storage allocated by "malloc_fo_sub(fo, 0UL)" leaks it. 794 *vbt = remalloc_fo(malloc_fo_sub(fo, 0), head->vbt_size); 795 } 796 797 /* Option ROM checksum */ 798 static u8 checksum_vbios(const optionrom_header_t *oh) 799 { ** CID 1396049: Parse warnings (PARSE_ERROR) /src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c: 653 in () ________________________________________________________________________________________________________ *** CID 1396049: Parse warnings (PARSE_ERROR) /src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c: 653 in () 647 648 struct lp0_header header __attribute__((section(".header"))) = 649 { 650 .length_insecure = (uintptr_t)&blob_total_size, 651 .length_secure = (uintptr_t)&blob_total_size, 652 .destination = (uintptr_t)&blob_data, >>> CID 1396049: Parse warnings (PARSE_ERROR) >>> identifier "lp0_resume" is undefined 653 .entry_point = (uintptr_t)&lp0_resume, 654 .code_length = (uintptr_t)&blob_data_size ** CID 1396048: (PARSE_ERROR) /src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c: 266 in () /src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c: 430 in () ________________________________________________________________________________________________________ *** CID 1396048: (PARSE_ERROR) /src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c: 266 in () 260 static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20); 261 262 263 264 /* Utility functions. */ 265 >>> CID 1396048: (PARSE_ERROR) >>> expected a ";" 266 static __always_inline void __noreturn halt(void) 267 { 268 for (;;); 269 } 270 271 static inline uint32_t read32(const void *addr) /src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c: 430 in () 424 #define MAX77621_VOUT_VAL (0x80 | 0x27) 425 #define MAX77621_VOUT_DATA (MAX77621_VOUT_REG | (MAX77621_VOUT_VAL << 8)) 426 427 428 /* Utility functions. */ 429 >>> CID 1396048: (PARSE_ERROR) >>> expected a ";" 430 static __always_inline void __noreturn halt(void) 431 { 432 for (;;); 433 } 434 435 static inline uint32_t read32(const void *addr) ** CID 1396047: (RESOURCE_LEAK) /util/intelvbttool/intelvbttool.c: 1041 in patch_vbios() /util/intelvbttool/intelvbttool.c: 1045 in patch_vbios() ________________________________________________________________________________________________________ *** CID 1396047: (RESOURCE_LEAK) /util/intelvbttool/intelvbttool.c: 1041 in patch_vbios() 1035 parse_vbios(fo, &old_vbt); 1036 1037 if (old_vbt) { 1038 if (oh->vbt_offset + vbt_size(old_vbt) == fo->size) { 1039 /* Located at the end of file - reduce file size */ 1040 if (fo->size < vbt_size(old_vbt)) >>> CID 1396047: (RESOURCE_LEAK) >>> Variable "old_vbt" going out of scope leaks the storage it points to. 1041 return 1; 1042 fo = remalloc_fo(fo, fo->size - vbt_size(old_vbt)); 1043 if (!fo) { 1044 printerr("Failed to allocate memory\n"); 1045 return 1; 1046 } /util/intelvbttool/intelvbttool.c: 1045 in patch_vbios() 1039 /* Located at the end of file - reduce file size */ 1040 if (fo->size < vbt_size(old_vbt)) 1041 return 1; 1042 fo = remalloc_fo(fo, fo->size - vbt_size(old_vbt)); 1043 if (!fo) { 1044 printerr("Failed to allocate memory\n"); >>> CID 1396047: (RESOURCE_LEAK) >>> Variable "old_vbt" going out of scope leaks the storage it points to. 1045 return 1; 1046 } 1047 oh->vbt_offset = 0; 1048 } else if (vbt_size(old_vbt) < vbt_size(fo_vbt)) { 1049 /* In the middle of the file - Remove old VBT */ 1050 memset(fo->data + oh->vbt_offset, 0xff, ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Re: [coreboot] Change superio in "Bayley Bay FSP-based CRB"
by Zvi Vered 08 Oct '18

08 Oct '18

Hi Jose, All, According to lspci I modified devicetree.cp copied from the "Bay Trail" reference: 1. Should I add the devices at the end of the list marked with # in domain 1.2.3 ? 2. How can I know to set 'on' or 'off' ? /***************************************************************************************************** device domain 0 on device pci 00.0 on end # 8086 0F00 - SoC router device pci 02.0 on end # 8086 0F31 - GFX device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins) device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23) device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time device pci 1b.0 on end # 8086 0F04 - HD Audio device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (x4 slot) device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot) device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot) device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot) device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end #superio/winbond/w83627hf end # 8086 0F1C - LPC bridge device pci 1f.3 on end # 8086 0F12 - SMBus 0 end #01:00.0 0604: 10b5:8505 #02:01.0 0604: 10b5:8505 #02:02.0 0604: 10b5:8505 #02:03.0 0604: 10b5:8505 #02:04.0 0604: 10b5:8505 #03:00.0 0604: 10b5:8112 #0a:00.0 0200: 8086:157b *********************************************************************************************************/ Thank you very much, Zvika On Mon, Oct 8, 2018 at 10:16 AM Jose Trujillo <ce.autom(a)protonmail.com> wrote: > > Hello Zvika, > > Add your device in Konfig and configure it under devicetree. > Look for examples and/or previous threads in this mail list. > > Jose. > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > On Monday, October 8, 2018 12:02 AM, Zvi Vered <veredz72(a)gmail.com> wrote: > > > Hello, > > > > I have to port coreboot to a "Bay Trail" board (KONTRON). > > I selected "Bayley Bay FSP-based CRB" as a reference. > > > > In my board, the output of superiotool is: > > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e > > > > But the configuration of the reference board is: > > *** Super I/O *** > > > > How can I change it ? > > > > I wish there was a basic configuration that could be easily modified. > > > > Thank you, > > Zvika > > > > ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ > > > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] Lenovo G505S - spkmodem console sound, is correct? Please listen and tell
by Denis 'GNUtoo' Carikli 08 Oct '18

08 Oct '18

On Thu, 27 Sep 2018 01:22:49 +0300 Ivan Ivanov <qmastery16(a)gmail.com> wrote: > If you've ever heard the spkmodem output, please could you try to > decode this stuff if its' easy for you, or at least to tell if it > sounds OK or not? Its the first ~4 minutes of like 30 minutes log > output, then the sounds stop: I've attached a recording. I recorded it on a T60, in GRUB, with an audio cable, after messing with the volume. > $ xzcat spkmodem.raw.xz | ./spkmodem-recv > hello world > Hello World Denis.

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Re: [coreboot] Lenovo G505S - spkmodem console sound, is correct? Please listen and tell
by Peter Stuge 08 Oct '18

08 Oct '18

Ivan Ivanov wrote: > If you've ever heard the spkmodem output, please could you try to > decode this stuff if its' easy for you, or at least to tell if it > sounds OK or not? It sounds somehow like I remember spkmodem, but the file is very low amplitude (too quiet) and I can't confirm whether the signal is the correct speed. I've only received spkmodem successfully with the microphone right next to the speaker - moving the mic only a few cm lost signal. Note that spkmodem-recv requires 48k s16le mono PCM. I tried decoding, resampling and normalizing the ogg file without success so I suggest increasing amplitude at the source; move the mic closer to the speaker and use the parecord | spkmodem-recv command as documented in spkmodem-recv.c. Make sure to set your mic input volume to 0dB (and not higher!) so that you get the best possible signal, without attenuation. //Peter

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Re: [coreboot] USB 2.0 EHCI debug dongle doesn't print logs (at Lenovo G505S)
by Denis 'GNUtoo' Carikli 08 Oct '18

08 Oct '18

On Sat, 29 Sep 2018 00:50:18 +0300 Ivan Ivanov <qmastery16(a)gmail.com> wrote: > Thank you for spkmodem comments, now I'm trying out a more reliable > way - FT232H dongle - to extract the logs from AMD Lenovo G505S. [...] If the usb debug dongle you could also try adding grub as a payload and launching it from SeaBIOS. GRUB has the cbmemc command that can print coreboot log. Denis.

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Re: [coreboot] Change superio in "Bayley Bay FSP-based CRB"
by Jose Trujillo 08 Oct '18

08 Oct '18

Hello Zvika, Add your device in Konfig and configure it under devicetree. Look for examples and/or previous threads in this mail list. Jose. ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Monday, October 8, 2018 12:02 AM, Zvi Vered <veredz72(a)gmail.com> wrote: > Hello, > > I have to port coreboot to a "Bay Trail" board (KONTRON). > I selected "Bayley Bay FSP-based CRB" as a reference. > > In my board, the output of superiotool is: > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e > > But the configuration of the reference board is: > *** Super I/O *** > > How can I change it ? > > I wish there was a basic configuration that could be easily modified. > > Thank you, > Zvika > > ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ > > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Source code for "Intel Firmware"
by Merlin Büge 07 Oct '18

07 Oct '18

On Sat, 6 Oct 2018 16:24:15 -0700 ron minnich <rminnich(a)gmail.com> wrote: > There are people on this list who know better than I what the most > "open" one is. > > Anyone out there have some advice? These are interesting: Samsung Chromebook Plus (based on RK3399, not available in EU) and Asus Chromebook R13 "ECC'17: Run upstream coreboot on an ARM Chromebook" https://www.youtube.com/watch?v=N7_9okzPeHo Cheers, Merlin > > On Sat, Oct 6, 2018 at 3:17 PM Andrew Luke Nesbit < > ullbeking(a)andrewnesbit.org> wrote: > > > > > On 6 Oct 2018, at 22:17, ron minnich <rminnich(a)gmail.com> wrote: > > > > It depends on what you mean by fully. If there is a so-called Mask > > ROM (i.e. initial boot program that's part of the chip itself, not > > replaceable, you can disassemble it however) and the rest of the > > chip is fully open, does that count? > > > > > > That's a good start. In my experience, these are what I've mostly > > seen. > > > > Ideally I mean one where the boot loader (and payload?) are not > > proprietary. Or that an open source boot loader could be used, > > preferably without added blobs. > > > > For my money the ARM chromebooks are still one of the best bets out > > there for messing about with ARM firmware. > > > > > > Yes, I've been looking at getting one for this very purpose, > > especially as it's already a whole, usable system. Have you any > > particular recommendations? > > > > On Sat, Oct 6, 2018 at 12:30 PM Andrew Luke Nesbit < > > ullbeking(a)andrewnesbit.org> wrote: > > > >> > >> > On 6 Oct 2018, at 17:42, ron minnich <rminnich(a)gmail.com> wrote: > >> > > >> [...] > >> > > >> > if you really want 100% open, the only real options at this > >> > point are > >> power 9, RISCV and some ARM CPUs. > >> > >> Ron, thanks for your reasoned reply and the contextual > >> background. I believe this is important when embarking on any > >> project with a legacy. > >> > >> I know of libre-friendly POWER9 and RISC-V options. For example, > >> I am currently learning my way around the Talos II (which is > >> excellent). ARM-based systems have been elusive to me. > >> > >> Could you please give some examples of fully libre-friendly > >> ARM-based boards or systems? Thanks!! > >> > >> Kind regards, > >> > >> Andrew > >> > > -- Merlin Büge

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coreboot October 2018