coreboot October 2018

coreboot@coreboot.org

53 participants
145 discussions

Modifying FSP in Binary Configuration Tool (BCT)
by Zvi Vered 12 Oct '18

12 Oct '18

Hello, The BCT has a "Memory Down" section. Can you please advise how can I know the right values for my board ? DIMM 0/1 Enable: DIMM DWidth: DIMM Density: DIMM_BusWidth: DIMM Sides: tCL: tRP_tRCD: tWR: tWTR: tRRD: tRTP: tFAW: Thank you in advance, Zvika

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 12 Oct '18

12 Oct '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1396100: Memory - corruptions (ARRAY_VS_SINGLETON) ________________________________________________________________________________________________________ *** CID 1396100: Memory - corruptions (ARRAY_VS_SINGLETON) /src/lib/selfboot.c: 236 in selfload() 230 data = rdev_mmap_full(prog_rdev(payload)); 231 232 if (data == NULL) 233 return false; 234 235 cbfssegs = &((struct cbfs_payload *)data)->segments; >>> CID 1396100: Memory - corruptions (ARRAY_VS_SINGLETON) >>> Passing "cbfssegs" to function "load_payload_segments" which uses it as an array. This might corrupt or misinterpret adjacent memory locations. 236 if (load_payload_segments(cbfssegs, check_regions, &entry)) 237 goto out; 238 239 printk(BIOS_SPEW, "Loaded segments\n"); 240 241 rdev_munmap(prog_rdev(payload), data); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Re: [coreboot] MRC in coreboot
by Aaron Durbin 12 Oct '18

12 Oct '18

On Fri, Oct 12, 2018 at 4:38 AM Antony AbeePrakash X V < AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > Hi Aron, > > > > I am not able to get the cbmem timestamps. I am using cbmem utility to > find the timestamps. > > > > *$ . /cbmem -t* > > > > The above command gives the following error. > > > > *Failed to mmap /dev/mem : Operation not permitted* > > > > Could you please help on this? > https://01.org/linuxgraphics/gfx-docs/drm/admin-guide/kernel-parameters.html Adding 'iomem=relaxed' to the kernel cmdline would fix that particular problem. Note, with that current error, that you should see a PAT error in dmesg. > > Thanks & Regards, > > Antony > > *From:* Aaron Durbin [mailto:adurbin@google.com] > *Sent:* Thursday, October 11, 2018 9:44 PM > *To:* Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> > *Cc:* Coreboot <coreboot(a)coreboot.org>; Dinesh Kumar < > DINESHKUMAR.VARADARAJAN(a)LNTTECHSERVICES.COM> > *Subject:* Re: [coreboot] MRC in coreboot > > > > cbmem timstamps will be needed. > > > > Looks like FSP is manipulating the tsc: > > BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 exit 0 > > > > I have a hard time believing that took 4291 seconds. > > > > On Thu, Oct 11, 2018 at 10:11 AM Antony AbeePrakash X V < > AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > Hi Aaron, > > PFA the console log for your reference. > > Please look into this and provide feedback. > > Thanks, > Antony > > -----Original Message----- > From: Aaron Durbin [mailto:adurbin@google.com] > Sent: Thursday, October 11, 2018 7:27 PM > To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> > Cc: Coreboot <coreboot(a)coreboot.org>; Dinesh Kumar < > DINESHKUMAR.VARADARAJAN(a)LNTTECHSERVICES.COM> > Subject: Re: [coreboot] MRC in coreboot > > On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V < > AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > > > Hi All, > > > > We are able to achieve the memory initialization time reduction. Now we > have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf > boot). > > > > We have reduced the unwanted codes. We would like to reduce the boot > time to less than 2sec. > > > > Could anyone please tell what can be done further ? > > You're going to need to post more information (cbmem timings and console > logs). > > > > > Thanks, > > Antony > > > > -----Original Message----- > > From: Aaron Durbin [mailto:adurbin@google.com] > > Sent: Wednesday, September 05, 2018 7:39 PM > > To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> > > Cc: Coreboot <coreboot(a)coreboot.org> > > Subject: Re: [coreboot] MRC in coreboot > > > > On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V < > AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > > > > > Hi, > > > > > > > > > > > > We are developing coreboot for Apollo lake custom board. MRC training > data save is enabled in FSP using Binary configuration tool. > > > > > > > > > > > > But we are getting logs like, > > > > > > > > > > > > No MRC cache found. > > > > > > MRC SeCUmaSize memory size from SeC ... 0 > > > > > > MRC Parameters not valid. Status is Success > > > > > > MRC:CpuMemoryTest Successful! > > > > > > Saving MRC data using CSE through HECI interface > > > > I have never seen this path used in coreboot. This line above is saying > CSE is responsible for saving and retrieving training data. In coreboot we > use the main processor to save and restore. I suggest reading over the UPD > parameters and ensure they match with our typical use cases. BCT tool > enabling 'training data save' sounds like it's enabling CSE path. > > > > > > > > Try to find MRC training data HOB. > > > > > > No MRC training data found, perform data save via HECI. > > > > > > Saved MRC training data with status (0x80000003) > > > > > > > > > > > > It seems that MRC data is not found and saved. Also I found that there > are options to add MRC file path and mrc.bin in menuconfig. The only option > I have is save cached MRC settings. > > > > > > > > > > > > What this mrc.bin will do? > > > > > > How to add the mrc.bin in coreboot? > > > > > > > > > > > > Please explain on this. > > > > > > > > > > > > Thanks & Regards, > > > > > > Antony > > > > > > > > > > > > L&T Technology Services Ltd > > > > > > www.LntTechservices.com > > > > > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. > > > > > > -- > > > coreboot mailing list: coreboot(a)coreboot.org > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > L&T Technology Services Ltd > > > > www.LntTechservices.com<http://www.lnttechservices.com/> > > > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. > L&T Technology Services Ltd > > www.LntTechservices.com<http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. > > *L&T Technology Services Ltd* > > www.LntTechservices.com <http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. >

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Re: [coreboot] MRC in coreboot
by Antony AbeePrakash X V 12 Oct '18

12 Oct '18

Hi Aron, I am not able to get the cbmem timestamps. I am using cbmem utility to find the timestamps. $ . /cbmem -t The above command gives the following error. Failed to mmap /dev/mem : Operation not permitted Could you please help on this? Thanks & Regards, Antony From: Aaron Durbin [mailto:adurbin@google.com] Sent: Thursday, October 11, 2018 9:44 PM To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> Cc: Coreboot <coreboot(a)coreboot.org>; Dinesh Kumar <DINESHKUMAR.VARADARAJAN(a)LNTTECHSERVICES.COM> Subject: Re: [coreboot] MRC in coreboot cbmem timstamps will be needed. Looks like FSP is manipulating the tsc: BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 exit 0 I have a hard time believing that took 4291 seconds. On Thu, Oct 11, 2018 at 10:11 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com<mailto:AntonyAbee.PrakashXV@lnttechservices.com>> wrote: Hi Aaron, PFA the console log for your reference. Please look into this and provide feedback. Thanks, Antony -----Original Message----- From: Aaron Durbin [mailto:adurbin@google.com<mailto:adurbin@google.com>] Sent: Thursday, October 11, 2018 7:27 PM To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com<mailto:AntonyAbee.PrakashXV@LntTechservices.com>> Cc: Coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>>; Dinesh Kumar <DINESHKUMAR.VARADARAJAN(a)LNTTECHSERVICES.COM<mailto:DINESHKUMAR.VARADARAJAN@LNTTECHSERVICES.COM>> Subject: Re: [coreboot] MRC in coreboot On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com<mailto:AntonyAbee.PrakashXV@lnttechservices.com>> wrote: > > Hi All, > > We are able to achieve the memory initialization time reduction. Now we have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf boot). > > We have reduced the unwanted codes. We would like to reduce the boot time to less than 2sec. > > Could anyone please tell what can be done further ? You're going to need to post more information (cbmem timings and console logs). > > Thanks, > Antony > > -----Original Message----- > From: Aaron Durbin [mailto:adurbin@google.com<mailto:adurbin@google.com>] > Sent: Wednesday, September 05, 2018 7:39 PM > To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com<mailto:AntonyAbee.PrakashXV@LntTechservices.com>> > Cc: Coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> > Subject: Re: [coreboot] MRC in coreboot > > On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com<mailto:AntonyAbee.PrakashXV@lnttechservices.com>> wrote: > > > > Hi, > > > > > > > > We are developing coreboot for Apollo lake custom board. MRC training data save is enabled in FSP using Binary configuration tool. > > > > > > > > But we are getting logs like, > > > > > > > > No MRC cache found. > > > > MRC SeCUmaSize memory size from SeC ... 0 > > > > MRC Parameters not valid. Status is Success > > > > MRC:CpuMemoryTest Successful! > > > > Saving MRC data using CSE through HECI interface > > I have never seen this path used in coreboot. This line above is saying CSE is responsible for saving and retrieving training data. In coreboot we use the main processor to save and restore. I suggest reading over the UPD parameters and ensure they match with our typical use cases. BCT tool enabling 'training data save' sounds like it's enabling CSE path. > > > > > Try to find MRC training data HOB. > > > > No MRC training data found, perform data save via HECI. > > > > Saved MRC training data with status (0x80000003) > > > > > > > > It seems that MRC data is not found and saved. Also I found that there are options to add MRC file path and mrc.bin in menuconfig. The only option I have is save cached MRC settings. > > > > > > > > What this mrc.bin will do? > > > > How to add the mrc.bin in coreboot? > > > > > > > > Please explain on this. > > > > > > > > Thanks & Regards, > > > > Antony > > > > > > > > L&T Technology Services Ltd > > > > www.LntTechservices.com<http://www.LntTechservices.com> > > > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> > > https://mail.coreboot.org/mailman/listinfo/coreboot > L&T Technology Services Ltd > > www.LntTechservices.com<http://www.LntTechservices.com><http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. L&T Technology Services Ltd www.LntTechservices.com<http://www.LntTechservices.com><http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] MRC in coreboot
by Aaron Durbin 11 Oct '18

11 Oct '18

cbmem timstamps will be needed. Looks like FSP is manipulating the tsc: BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 exit 0 I have a hard time believing that took 4291 seconds. On Thu, Oct 11, 2018 at 10:11 AM Antony AbeePrakash X V < AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > Hi Aaron, > > PFA the console log for your reference. > > Please look into this and provide feedback. > > Thanks, > Antony > > -----Original Message----- > From: Aaron Durbin [mailto:adurbin@google.com] > Sent: Thursday, October 11, 2018 7:27 PM > To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> > Cc: Coreboot <coreboot(a)coreboot.org>; Dinesh Kumar < > DINESHKUMAR.VARADARAJAN(a)LNTTECHSERVICES.COM> > Subject: Re: [coreboot] MRC in coreboot > > On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V < > AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > > > Hi All, > > > > We are able to achieve the memory initialization time reduction. Now we > have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf > boot). > > > > We have reduced the unwanted codes. We would like to reduce the boot > time to less than 2sec. > > > > Could anyone please tell what can be done further ? > > You're going to need to post more information (cbmem timings and console > logs). > > > > > Thanks, > > Antony > > > > -----Original Message----- > > From: Aaron Durbin [mailto:adurbin@google.com] > > Sent: Wednesday, September 05, 2018 7:39 PM > > To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> > > Cc: Coreboot <coreboot(a)coreboot.org> > > Subject: Re: [coreboot] MRC in coreboot > > > > On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V < > AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > > > > > Hi, > > > > > > > > > > > > We are developing coreboot for Apollo lake custom board. MRC training > data save is enabled in FSP using Binary configuration tool. > > > > > > > > > > > > But we are getting logs like, > > > > > > > > > > > > No MRC cache found. > > > > > > MRC SeCUmaSize memory size from SeC ... 0 > > > > > > MRC Parameters not valid. Status is Success > > > > > > MRC:CpuMemoryTest Successful! > > > > > > Saving MRC data using CSE through HECI interface > > > > I have never seen this path used in coreboot. This line above is saying > CSE is responsible for saving and retrieving training data. In coreboot we > use the main processor to save and restore. I suggest reading over the UPD > parameters and ensure they match with our typical use cases. BCT tool > enabling 'training data save' sounds like it's enabling CSE path. > > > > > > > > Try to find MRC training data HOB. > > > > > > No MRC training data found, perform data save via HECI. > > > > > > Saved MRC training data with status (0x80000003) > > > > > > > > > > > > It seems that MRC data is not found and saved. Also I found that there > are options to add MRC file path and mrc.bin in menuconfig. The only option > I have is save cached MRC settings. > > > > > > > > > > > > What this mrc.bin will do? > > > > > > How to add the mrc.bin in coreboot? > > > > > > > > > > > > Please explain on this. > > > > > > > > > > > > Thanks & Regards, > > > > > > Antony > > > > > > > > > > > > L&T Technology Services Ltd > > > > > > www.LntTechservices.com > > > > > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. > > > > > > -- > > > coreboot mailing list: coreboot(a)coreboot.org > > > https://mail.coreboot.org/mailman/listinfo/coreboot > > L&T Technology Services Ltd > > > > www.LntTechservices.com<http://www.lnttechservices.com/> > > > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. > L&T Technology Services Ltd > > www.LntTechservices.com<http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. >

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Re: [coreboot] MRC in coreboot
by Antony AbeePrakash X V 11 Oct '18

11 Oct '18

Hi Aaron, PFA the console log for your reference. Please look into this and provide feedback. Thanks, Antony -----Original Message----- From: Aaron Durbin [mailto:adurbin@google.com] Sent: Thursday, October 11, 2018 7:27 PM To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> Cc: Coreboot <coreboot(a)coreboot.org>; Dinesh Kumar <DINESHKUMAR.VARADARAJAN(a)LNTTECHSERVICES.COM> Subject: Re: [coreboot] MRC in coreboot On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > Hi All, > > We are able to achieve the memory initialization time reduction. Now we have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf boot). > > We have reduced the unwanted codes. We would like to reduce the boot time to less than 2sec. > > Could anyone please tell what can be done further ? You're going to need to post more information (cbmem timings and console logs). > > Thanks, > Antony > > -----Original Message----- > From: Aaron Durbin [mailto:adurbin@google.com] > Sent: Wednesday, September 05, 2018 7:39 PM > To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> > Cc: Coreboot <coreboot(a)coreboot.org> > Subject: Re: [coreboot] MRC in coreboot > > On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > > > Hi, > > > > > > > > We are developing coreboot for Apollo lake custom board. MRC training data save is enabled in FSP using Binary configuration tool. > > > > > > > > But we are getting logs like, > > > > > > > > No MRC cache found. > > > > MRC SeCUmaSize memory size from SeC ... 0 > > > > MRC Parameters not valid. Status is Success > > > > MRC:CpuMemoryTest Successful! > > > > Saving MRC data using CSE through HECI interface > > I have never seen this path used in coreboot. This line above is saying CSE is responsible for saving and retrieving training data. In coreboot we use the main processor to save and restore. I suggest reading over the UPD parameters and ensure they match with our typical use cases. BCT tool enabling 'training data save' sounds like it's enabling CSE path. > > > > > Try to find MRC training data HOB. > > > > No MRC training data found, perform data save via HECI. > > > > Saved MRC training data with status (0x80000003) > > > > > > > > It seems that MRC data is not found and saved. Also I found that there are options to add MRC file path and mrc.bin in menuconfig. The only option I have is save cached MRC settings. > > > > > > > > What this mrc.bin will do? > > > > How to add the mrc.bin in coreboot? > > > > > > > > Please explain on this. > > > > > > > > Thanks & Regards, > > > > Antony > > > > > > > > L&T Technology Services Ltd > > > > www.LntTechservices.com > > > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > L&T Technology Services Ltd > > www.LntTechservices.com<http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] MRC in coreboot
by Aaron Durbin 11 Oct '18

11 Oct '18

On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > Hi All, > > We are able to achieve the memory initialization time reduction. Now we have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf boot). > > We have reduced the unwanted codes. We would like to reduce the boot time to less than 2sec. > > Could anyone please tell what can be done further ? You're going to need to post more information (cbmem timings and console logs). > > Thanks, > Antony > > -----Original Message----- > From: Aaron Durbin [mailto:adurbin@google.com] > Sent: Wednesday, September 05, 2018 7:39 PM > To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> > Cc: Coreboot <coreboot(a)coreboot.org> > Subject: Re: [coreboot] MRC in coreboot > > On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > > > Hi, > > > > > > > > We are developing coreboot for Apollo lake custom board. MRC training data save is enabled in FSP using Binary configuration tool. > > > > > > > > But we are getting logs like, > > > > > > > > No MRC cache found. > > > > MRC SeCUmaSize memory size from SeC ... 0 > > > > MRC Parameters not valid. Status is Success > > > > MRC:CpuMemoryTest Successful! > > > > Saving MRC data using CSE through HECI interface > > I have never seen this path used in coreboot. This line above is saying CSE is responsible for saving and retrieving training data. In coreboot we use the main processor to save and restore. I suggest reading over the UPD parameters and ensure they match with our typical use cases. BCT tool enabling 'training data save' sounds like it's enabling CSE path. > > > > > Try to find MRC training data HOB. > > > > No MRC training data found, perform data save via HECI. > > > > Saved MRC training data with status (0x80000003) > > > > > > > > It seems that MRC data is not found and saved. Also I found that there are options to add MRC file path and mrc.bin in menuconfig. The only option I have is save cached MRC settings. > > > > > > > > What this mrc.bin will do? > > > > How to add the mrc.bin in coreboot? > > > > > > > > Please explain on this. > > > > > > > > Thanks & Regards, > > > > Antony > > > > > > > > L&T Technology Services Ltd > > > > www.LntTechservices.com > > > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > L&T Technology Services Ltd > > www.LntTechservices.com<http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] intel/i82801dx SMM memory size?
by Kyösti Mälkki 11 Oct '18

11 Oct '18

On Wed, Oct 3, 2018 at 7:00 AM ron minnich <rminnich(a)gmail.com> wrote: > I'm wondering ... does anyone know the limits on SMM memory size for this > part? > > SMM memory size was determined by the MCH part, not ICH. The boards we had with i82801dx used ASEG with 128 kiB of SMRAM. The only remaining user of i82801dx couples with e7505 that could handle 1 MiB of TSEG. > I'm looking for a mainboard emulation which can support the larger sizes, > e.g. 8M. > > Out of the box, not supported. But emulation/qemu-q35 can do that if you add "select SMM_TSEG" and some glue logic to write those TSEG related registers. You also need a recent QEMU, 2.10 or later. thanks > > ron > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Wired problems with Intel skylake based board
by Peter Stuge 11 Oct '18

11 Oct '18

Christian Gmeiner wrote: > Most of the time the system works as expected but from time to rebooting > the system fails completely. Only ever when rebooting, or does cold boot also fail sometimes? (Make a test system to cold boot your system in a loop.) > there are two FPGAs connected via PCIe to the system where one is used > to reset the system. The reset is done via SYS_RESET#. Are the FPGAs also reset by that? If yes, how long do they need to initialize to where HDL acts correctly on PCIe? If no, how long do they need to move from resetting the system to where HDL acts correctly on PCIe for the newly resetted platform? > Now I run into different kind of issues: > - pcie link training fails from time to time On both links, or only one of them? Can you tell? > - looks like PLTRST# of the sunrisepoint pch holds the system in reset > for minutes. I don't know if there's enough PCH documentation to know exactly why it would do that - but I can imagine that it holds reset as long as some conditions are not met, I can also imagine that the FPGAs cause some undefined PCIe behavior in the PCH which happens to get it stuck in reset for a while. > Are there any hints to debug my issues? As always, try to isolate the problem. Can you completely remove one or ideally both FPGAs from the equation? You mention that one of them is used for reset. At least disable the other one, destructively if need be. //Peter

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Re: [coreboot] MRC in coreboot
by Antony AbeePrakash X V 11 Oct '18

11 Oct '18

Hi All, We are able to achieve the memory initialization time reduction. Now we have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf boot). We have reduced the unwanted codes. We would like to reduce the boot time to less than 2sec. Could anyone please tell what can be done further ? Thanks, Antony -----Original Message----- From: Aaron Durbin [mailto:adurbin@google.com] Sent: Wednesday, September 05, 2018 7:39 PM To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> Cc: Coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] MRC in coreboot On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > > Hi, > > > > We are developing coreboot for Apollo lake custom board. MRC training data save is enabled in FSP using Binary configuration tool. > > > > But we are getting logs like, > > > > No MRC cache found. > > MRC SeCUmaSize memory size from SeC ... 0 > > MRC Parameters not valid. Status is Success > > MRC:CpuMemoryTest Successful! > > Saving MRC data using CSE through HECI interface I have never seen this path used in coreboot. This line above is saying CSE is responsible for saving and retrieving training data. In coreboot we use the main processor to save and restore. I suggest reading over the UPD parameters and ensure they match with our typical use cases. BCT tool enabling 'training data save' sounds like it's enabling CSE path. > > Try to find MRC training data HOB. > > No MRC training data found, perform data save via HECI. > > Saved MRC training data with status (0x80000003) > > > > It seems that MRC data is not found and saved. Also I found that there are options to add MRC file path and mrc.bin in menuconfig. The only option I have is save cached MRC settings. > > > > What this mrc.bin will do? > > How to add the mrc.bin in coreboot? > > > > Please explain on this. > > > > Thanks & Regards, > > Antony > > > > L&T Technology Services Ltd > > www.LntTechservices.com > > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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coreboot October 2018