coreboot July 2017

coreboot@coreboot.org

54 participants
131 discussions

Re: [coreboot] Volunteer needed to host the North American coreboot conference 2018
by ron minnich 20 Jul '17

20 Jul '17

To add to this, if you wish to take this task on, don't underestimate the work involved. You can't start working on it 2 months before; a safe lead time is 7-9 months. You should work out the conference rooms and hotel by Jan. 1 at the latest. Don't plan to take this on unless you're ready to do a lot of work. Martin makes it look easy, but it's not :-) On Thu, Jul 20, 2017 at 10:33 AM Martin Roth <gaumless(a)gmail.com> wrote: > We are currently looking for a volunteer to host the 2018 North American > coreboot conference. > > The only real requirements for the location is that it's relatively close > to a major airport and that it can hold 30-50 people comfortably. From the > feedback we got after the Denver conference, it sounds like a 4 day > conference is most desirable, with 2 formal days of presentations, and 2 > optional days of hacking. > > Main responsibilities would include: > - Booking and setting up the venue (or venues) > - Organizing Lunches, beverages, and snacks > - Organizing after-conference activities > - Setup for Presentations and recording the presentations > > Additional tasks that the coreboot project can help with: > - Organizing talks > - Promotion (Website, announcements on the mailing list, and IRC) > - Billing > - Badges > - Swag > > If you're interested or have any questions, feel free reply here or to > email me off-list. > > Thanks. > Martin > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Wiki page for Lenovo Thinkpad W520
by Charlotte Plusplus 20 Jul '17

20 Jul '17

Hello I did the rebase in Denver. I have the same ram issues. Unless you mean the changes have happened in the last few weeks? I have some exams in August, I can try to rebase again in August or just send the current patch. But it should come with a big fat warning that memory errors do occur as show on a memtest Charlotte On Tue, Jul 18, 2017 at 2:55 AM, Iru Cai <mytbk920423(a)gmail.com> wrote: > Hi Charlotte, > > On Tue, Jul 18, 2017 at 1:37 PM, Charlotte Plusplus < > pluspluscharlotte(a)gmail.com> wrote: > >> Hello >> >> I would be very happy to help with pictures, source, binaries, info etc. >> But since Denver, I have been just a bit behind. Too many side projects :-) >> >> Anyway, I will get back in touch soon. If you use my previously released >> binary, you should be fine. >> >> The port to the current coreboot I did in Denver has new ram issues that >> I am investigating. It may need again some dirty workarounds, like adding >> +1 or +2 to some SPD settings to get memtest work without any failure. >> Optimus is still not working yet. >> > > Maybe you need to rebase your code on master coreboot, which has some > improvements on Sandy/Ivy Bridge RAM init. There's also some changes in the > codebase. > > Iru > > >> Thanks >> Charlotte >> >> >> On Sun, Jul 16, 2017 at 8:49 AM, Nico Rikken <nico(a)nicorikken.eu> wrote: >> >>> I created a wiki page for the Lenovo W520 based on information shared >>> on this mailinglist: >>> >>> https://www.coreboot.org/Board:lenovo/w520 >>> >>> I hope others can contribute more details, so I can benefit when taking >>> on the challenge of flashing a W520 myself. >>> >>> Kind regards, >>> Nico Rikken (NL) >>> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > Please do not send me Microsoft Office/Apple iWork documents. Send > OpenDocument instead! http://fsf.org/campaigns/opendocument/ >

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Volunteer needed to host the North American coreboot conference 2018
by Martin Roth 20 Jul '17

20 Jul '17

We are currently looking for a volunteer to host the 2018 North American coreboot conference. The only real requirements for the location is that it's relatively close to a major airport and that it can hold 30-50 people comfortably. From the feedback we got after the Denver conference, it sounds like a 4 day conference is most desirable, with 2 formal days of presentations, and 2 optional days of hacking. Main responsibilities would include: - Booking and setting up the venue (or venues) - Organizing Lunches, beverages, and snacks - Organizing after-conference activities - Setup for Presentations and recording the presentations Additional tasks that the coreboot project can help with: - Organizing talks - Promotion (Website, announcements on the mailing list, and IRC) - Billing - Badges - Swag If you're interested or have any questions, feel free reply here or to email me off-list. Thanks. Martin

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Re: [coreboot] more smm questions
by ron minnich 20 Jul '17

20 Jul '17

OK, I have it working. For the Q35 qemu mainboard, I can direct SMI to the kernel. The final issue was that the existing linux trampoline can't work at present if you have enabled NX and set the top bit of a PTE to 1, since the trampoline doesn't enable NX correctly. Easy fix: add nonx=off to the commandline. that's not a typo, even though one might expect it to be nonx=on So, it's possible to have your kernel handle SMIs and run code that otherwise would be in ring -2. We've been advised that the best thing to do with SMI is disable it totally (I agree -- that's what we did in in linuxbios 1999-2006) and so we'll probably pursue that path instead. But it's good to know that this is possible. For more, see https://github.com/rminnich/linux/tree/monitor The test is simple, outb to 0xb2 (IIRC) and you'll see the SMI handler in the kernel print something.

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Hi-DPI displays and showing text information for kevin in depthcharge
by Paul Kocialkowski 20 Jul '17

20 Jul '17

I am using upstream coreboot with top-of-tree depthcharge and vboot on kevin (Chromebook Plus from Samsung) and I've patched depthcharge[0] to display text messages instead of looking up bitmaps in the GBB/cbfs. I noticed that corebootfb is using[1] a fixed 8x16 font for showing text there. In addition, the RK3399 eDP code will always go with the "recommended resolution" from the EDID, which is the highest one. The result of this is that the displayed text looks really small on- screen, which does not really provide a great user experience. So I am wondering what the best way to solve this would be. I see a few options: * Having larger fonts for hi-dpi displays * Scaling the font to reach a particular DPI (e.g. based on the physical screen size reported from the EDID) * Reducing the resolution, by optionally providing a preferred one from the config Among these, which ones do you think is the way to go? I think the question is also whether we want a generic way to handle this or to do it per-device (and also keep in mind that not every device has EDID available, but may have a single hardcoded resolution, which could still superseded by the suggested config option). I like the idea of reducing the resolution. It may however also break compatibility with e.g. ChromeOS that expects the framebuffer to be set at the max resolution by coreboot. [0]: http://git.code.paulk.fr/gitweb/?p=libettereboot.git;a=tree;f=projects/dept… [1]: https://review.coreboot.org/cgit/coreboot.git/tree/payloads/libpayload/driv… Cheers, -- Paul Kocialkowski, developer of free digital technology and hardware support. Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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Re: [coreboot] Coreboot and INT13H
by ron minnich 19 Jul '17

19 Jul '17

to expand on patrick's comment, any sort of output in the boot stage of coreboot significantly slows boot time. This is not a problem on most firmware, but on coreboot it's a big issue. Even the addition of 100 milliseconds is a real detriment to boot time.

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Coreboot and INT13H
by ingegneriaforense＠alice.it 19 Jul '17

19 Jul '17

Hello everybody, i'm interesting in the way Coreboot manages the INT13H interrupt. Please, can you tell me: 1- where (the name of the file) the INT 13H is implemented in the coreboot source code ? 2- if the INT 13H interrupt, when invoked by OS (or application programs), can do writing operations in the filesystem of the drive attached to the PC or only limits to writing operations in memory regions different by the filesystem ? 3- Is a way to see on the screen the fully sequence of operations coreboot execute during the boot ? (i don't use QUEMU but program directly the bios eeprom chip). Best Regards. Vincenzo. Forensic Consultant Tribunale di Lecce Studio: Strada di Garibaldi - Contrada Paradisi 73010 Lequile (LE) cell: 339.7968555 skype: vincenzo.di_salvo

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Re: [coreboot] question on libgfxinit DP port number
by Nico Huber 19 Jul '17

19 Jul '17

Hi Iru, On 18.07.2017 09:28, Iru Cai wrote: > Hi, > > I found the mainboard DP port doesn't have output before kernel starts in > hp/2570p (https://review.coreboot.org/c/20489/). After I added DP3 and > HDMI3 in port list, the DP port had output, and cbmem log said it's DP3. > However, xrandr says this port is DP2. What is the problem? libgfxinit only knows about physical ports (i.e. how they are ordered* in the datasheet). Linux ignores ports that aren't strapped to be active (or are disabled by VBT) and renumbers the ports to fill the holes. Nico * The numbering is not perfect. As historically VGA was the first port (port A in datasheets), digital ports are counted from B, so DP1 is port B, DP2 is port C, etc.

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kexec --reset-vga from an inteldrmfb frame buffer
by Trammell Hudson 18 Jul '17

18 Jul '17

When I have my coreboot payload Linux kernel setup a console framebuffer and then kexec into Xen + another kernel, the video glitches out quite a bit before falling back to text mode. The kexec --reset-vga option doesn't seem to have any effect. I read in the docs that kexec and framebuffers don't get along and it seems that the patch from 2006 only works with VESA: https://lkml.org/lkml/2006/7/17/58 My system is using i915 graphics, and there is no option ROM, so I don't think it even shows up with any VESA compatible modes. Is there any way to reset the card or to transfer the mode info to the next kernel? -- Trammell

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(depthcharge, vboot) Difficulties booting on Chromebook
by Linus Heckemann 18 Jul '17

18 Jul '17

Hi all, I've been following the instructions for getting Debian running on an Asus C201 Chromebook[1]. This has been going well, mostly, except that when I try to actually boot it (power on and press Ctrl-U) I am greeted by a loud and low-pitched beep and not much else. Any ideas as to what I may be missing? Relevant stuff: # crossystem | grep dev_boot dev_boot_usb = 1 # Enable developer mode boot from USB/SD (writable) dev_boot_legacy = 0 # Enable developer mode boot Legacy OSes (writable) dev_boot_signed_only = 0 # Enable developer mode boot only from official kernels (writable) I've uploaded an image of the SD card resulting from the instructions (208M, 2G uncompressed) at [2]. Best regards Linus [1]: https://wiki.debian.org/InstallingDebianOn/Asus/C201 [2]: https://sphalerite.org/chromebook-debian-boot-sd.img.gz

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coreboot July 2017