coreboot July 2017

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54 participants
131 discussions

question on libgfxinit DP port number
by Iru Cai 18 Jul '17

18 Jul '17

Hi, I found the mainboard DP port doesn't have output before kernel starts in hp/2570p (https://review.coreboot.org/c/20489/). After I added DP3 and HDMI3 in port list, the DP port had output, and cbmem log said it's DP3. However, xrandr says this port is DP2. What is the problem? I also checked lenovo/x230, but the port named DP2 in xrandr or /sys/class/drm/card0-DP-2 is also shown as DP2 in cbmem log. Thanks, Iru -- Please do not send me Microsoft Office/Apple iWork documents. Send OpenDocument instead! http://fsf.org/campaigns/opendocument/

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Re: [coreboot] Wiki page for Lenovo Thinkpad W520
by Iru Cai 18 Jul '17

18 Jul '17

Hi Charlotte, On Tue, Jul 18, 2017 at 1:37 PM, Charlotte Plusplus < pluspluscharlotte(a)gmail.com> wrote: > Hello > > I would be very happy to help with pictures, source, binaries, info etc. > But since Denver, I have been just a bit behind. Too many side projects :-) > > Anyway, I will get back in touch soon. If you use my previously released > binary, you should be fine. > > The port to the current coreboot I did in Denver has new ram issues that I > am investigating. It may need again some dirty workarounds, like adding +1 > or +2 to some SPD settings to get memtest work without any failure. > Optimus is still not working yet. > Maybe you need to rebase your code on master coreboot, which has some improvements on Sandy/Ivy Bridge RAM init. There's also some changes in the codebase. Iru > Thanks > Charlotte > > > On Sun, Jul 16, 2017 at 8:49 AM, Nico Rikken <nico(a)nicorikken.eu> wrote: > >> I created a wiki page for the Lenovo W520 based on information shared >> on this mailinglist: >> >> https://www.coreboot.org/Board:lenovo/w520 >> >> I hope others can contribute more details, so I can benefit when taking >> on the challenge of flashing a W520 myself. >> >> Kind regards, >> Nico Rikken (NL) >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > -- Please do not send me Microsoft Office/Apple iWork documents. Send OpenDocument instead! http://fsf.org/campaigns/opendocument/

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Wiki page for Lenovo Thinkpad W520
by Nico Rikken 18 Jul '17

18 Jul '17

I created a wiki page for the Lenovo W520 based on information shared on this mailinglist: https://www.coreboot.org/Board:lenovo/w520 I hope others can contribute more details, so I can benefit when taking on the challenge of flashing a W520 myself. Kind regards, Nico Rikken (NL)

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Re: [coreboot] Haswell port
by Zoran Stojsavljevic 18 Jul '17

18 Jul '17

> It's all because of wrong memory map (only 16MB allocated). Kostja, Attached logs would be nice to have (from FSP up). Spasibo, Zoran On Tue, Jul 18, 2017 at 5:35 AM, Константин <theshtabel(a)gmail.com> wrote: > Hello, dear Coreboot community! > We are trying to make Haswell port (H87) after B75 port. Now It's loading > in SeaBIOS, but payload doesn't see any HDD or DVD. It's all because of > wrong memory map (only 16MB allocated). Mrc included, "System agent: Memory > Initialization//System agent: Done" logged. > Is anybody made desktop Haswell port? > > With greetings, Konstantin Novikov. > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] kabylake board suggestions?
by Zoran Stojsavljevic 18 Jul '17

18 Jul '17

Interesting... *EDK II Minimized firmware for Intel(R)Kabylake platforms!* There were really very aggressive people on this list opposing at the time my idea (about two years ago) to make minimalistic UEFI (to make minimal set of necessary drivers and run time environment for OS boot and to create /boot/efi (FAT32 fs) directory. Suddenly, boom!? Here we are. ;-) INTEL CCG rvp3? It was heavy shortage of these ones about a year and a half ago. This one (IIRC) supports Y versions of silicon. In other words: ##Known limitations 1. This firmware project has only been validated on the Intel KabylakeRVP3 board (*using FSP for Y silicons, which is probably different that U and other types*). 2. This firmware project has only been validated booting to Microsoft Windows 10 x64 with AHCI mode and Integrated Graphic Device (*external GFX PCIe system init probably expunged from EDKII*). 3. This firmware project has only been validated using the Microsoft Visual Studio 2015 compiler (*old, good INTEL - still stubbornly supports MSFT OSes due to CCG's 180 degrees Linux blindness*). Zoran

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Re: [coreboot] Any intro available for adding cbmem support to an old platform?
by Keith Hui 18 Jul '17

18 Jul '17

Hi Paul, For some reason your replies ended up in junk mail. :-\ I've pulled them out and can now reply properly. :) It boots, all the way into Slackware and able to get an SSH conversation going (for board_status). On Sat, Jul 15, 2017 at 10:21 AM, Paul Menzel <paulepanter(a)users.sourceforge.net> wrote: > > Thank you for uploading the log files to the board status repository. > Unfortunately the build is marked as *dirty*, which means, you probably > had uncommitted changes in the tree, that might or might not have been > needed to boot the machine. So it’s hard for somebody else rebuilding > the same image, and it’s less likely that it’ll boot. > > `git status` and `git diff`, maybe with the switch `--cached`, could be > used to find out, what is uncommitted. If you run `make gitconfig`, you > will also have the alias `git sup`, which checks out the correct > commits of the submodules, which are often a reason > > If you need help to get rid of the *dirty* state, please don’t hesitate > to ask. > It probably caught the changes I made for what I set out to do (which are not yet even staged for submission), but the binary I compiled when I ran board_status is without any of those. The binary now in the flash chip carries those changes and I can test. I am also staging them for submission into gerrit (took hours and quite a few tries to get git right), so it should not be dirty for long. Cheers Keith

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Haswell port
by Константин 18 Jul '17

18 Jul '17

Hello, dear Coreboot community! We are trying to make Haswell port (H87) after B75 port. Now It's loading in SeaBIOS, but payload doesn't see any HDD or DVD. It's all because of wrong memory map (only 16MB allocated). Mrc included, "System agent: Memory Initialization//System agent: Done" logged. Is anybody made desktop Haswell port? With greetings, Konstantin Novikov.

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kabylake board suggestions?
by ron minnich 18 Jul '17

18 Jul '17

This is kind of interesting: https://github.com/tianocore/edk2-platforms/tree/devel-MinPlatform is there a board that is close to the rvp3?

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Re: [coreboot] Hi-DPI displays and showing text information for kevin in depthcharge
by Patrick Georgi 17 Jul '17

17 Jul '17

I wouldn't scale at compile time (as said, storage constrained payloads might not be happy about that). I wouldn't scale each character up on each access though (we won't hardware accelerate the scaling, and yes, that does get slow - framebuffers aren't always the fastest type of memory and that way the access pattern is the same set of memcpy()s as for any other huge font, so we won't need to deal with "fast fonts" and "slow fonts" beyond basic geometry characteristics), but synthesize a new font in the regular font table at init-time and then use it like any pre-existing font (just that it happened to be added after load). 2017-07-17 21:47 GMT+02:00 Julius Werner <jwerner(a)chromium.org>: > I agree with most of what Patrick said, I think dynamic scaling to integer > multiples may be best. Scaling the font up at compile-time seems like > unnecessary bloat to the binary (although I'm not sure, how big are these > fonts?). If you do want to include them at compile time, you may as well > include a real larger font rather than just a scaled one. > -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

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Re: [coreboot] x86: best approach to debug consumer hardware?
by Andrey Korolyov 17 Jul '17

17 Jul '17

On Sun, Jul 9, 2017 at 2:56 AM, Andrey Korolyov <andrey(a)xdel.ru> wrote: >> >> I'd expect the clockgen to be the culprit too. But this C-state number >> could be a typo and also be the reason for your trouble (though, I'd >> wonder why it works on the T60). This number is used to map ACPI C-state >> semantics to the states presented in _CST. ACPI knows three C states and >> those rarely match the actual C states of the hardware. Basically, a 3 >> instead of a 2 tells ACPI to flush caches before entering this state. >> Also, ACPI C3 is to be avoided if bus-master activity is expected. >> > > It turned out to be again very simple thing: by some reason yet to be > found, write within ics954309_init could succeed only for first eight > data addresses on this board, it would ultimately return nothing for > higher data addresses within 0x69 so boot which is trying to write > smbus-type-width block will hang as it has been reported earlier. > Magically, cutting chip initialization in this crude way appears to > work against C3 behavour. I would take a look on the exact PLL chip > model upon next disassembly and also would dump i2c data with vendor > BIOS to get this properly (vendor BIOS does prevent access to clock > generator bits, as well to SPD data, just to mention). > > Forgot to mention that I`ve of course tried straightforward _CST fix > before, with no success at all. Someone with working T60/X60 could try > to check 'fixed' cst_entries ordering in mainboard.c and post the > results, right now all mine X60s are far away from the working state. As expected, vendor bios sets up the PLL with completely different parameters, though setting lower eight bytes from x60-based setup was 'good enough' to make C3 work. As vendor does not allow allow clockgen bits to be accessed programmatically, most complex part was to solder two unshielded wires on neighbor pins of the MLF64 package. There are a few issues remaining (certain regression with i915 consolefb while using binary vgabios on newest kernels and interrupt assignment issue with iw3945 in Win7), I would resolve them before pushing the board supporting code. Thanks again for useful hints!

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coreboot July 2017