coreboot July 2017

coreboot@coreboot.org

54 participants
131 discussions

Re: [coreboot] Broadwell-U hangs at VGA init
by Nico Huber 31 Jul '17

31 Jul '17

Hi Zheng, On 30.07.2017 16:13, Zheng Bao wrote: > I have got the mrc.bin and mem init has got passed. > Now the new problem is that it hangs at VGA init. > > static void igd_setup_panel(struct device *dev) > { > config_t *conf = dev->chip_info; > u32 reg32; > > /* Setup Digital Port Hotplug */ > reg32 = gtt_read(PCH_PORT_HOTPLUG); <------- It hangs here. > if (!reg32) { > reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; > reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; > reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; > gtt_write(PCH_PORT_HOTPLUG, reg32); > } > > It turns out as soon as i access VGA bar0+0xc4030, it hangs. > while accessing bar0 + 0xa00a is ok. sounds like the PCH part of the display engine isn't operational (pro- bably not all, but most register offsets with bit 19 set reside in the PCH). There are few steps to enable it [1], yet the Broadwell port seems to rely on the blob to do it. The datasheet [2] suggests that the same settings should be done for Broadwell too, but I can't find it in the source. So that leads to the conclusion: You forgot to add the second blob (HAVE_REFCODE_BLOB, it's BS, it's annoying, but you need it). That publicly documented settings move from the open source code into blobs is a very bad sign, IMO. Now, anybody tell me again, that things with Intel are getting better and they might become more open (the sta- tistics seem to say the opposite: the blobs get bigger, weirder, take over more responsibilities _and_ do a lot of stuff we already had open source for earlier platforms). Nico [1] src/southbridge/intel/lynxpoint/lpc.c:725 [2] Intel Document Number: 330837

2 1

Re: [coreboot] About Paging, Realmode and what is going on
by Philipp Stanner 31 Jul '17

31 Jul '17

Well, many thanks. I didn't expect it to work that way. Would be interesting to know what Windows 7 needs BIOS calls for. Any idea of traditional IBM-PC-Bios-calls are still available in UEFI-Firmware? On 31.07.2017 11:43, Patrick Georgi via coreboot wrote: > 2017-07-31 10:52 GMT+02:00 Philipp Stanner <stanner(a)posteo.de>: >> 1. cb switches the CPU immediately to Protected Mode, yet Payloads like seaBIOS work in Real Mode. Does coreboot switch the CPU always back to RM before jumping to the payload? > No, payloads are started in pmode. > >> 2. When CB switches to PM - who generates and administrates the Page Tables and where? > We use flat mode: 4gb segments starting at 0, for code and data. > Virtual address == logical address == physical address > >> 3. Gustavo Duarte writes that GRUB switches from protected mode to real mode and vice versa all the time to address >1MiB of RAM and also use the BIOS-calls. If this is true using GRUB as payload would not work, as GRUB needs to call the non-existent BIOS, right? > It uses BIOS calls, except when built for coreboot. > >> 4. Once CB is in PM it can't access physical addresses anymore? It doesn't need to, too? > We use flat mode, see above. > >> 5. PM means RAM-access is only possible through virtual addresses which are translated by the MMU using the Page Tables. This question is similar to [2.]: If coreboot generates the Page Tables and the payload would start in PM as well (is this even possible? At least the Linux-Kernel has entry points for RM and PM) this would mean the payload needs to use the Page Tables generated by CB. That wouldn't be a problem as they're linked in the register CR3 anyways? > As stated above, payloads start in pmode. As stated above, we use a > flat representation which comes with no surprises. The payload can > then reconfigure the system to setup its own configuration. > >> Why does every modern CPU still start in RM? I do get the compatibility problem, but on the other hand: Do you need it for anything beside booting MS-DOS on your Ryzen? Is it really impossible for AMD and Intel to create a new CPU-generation with the x86-instruction set without RM, 16-bit-registers and 20-bit-mode registers like CS, SS etc. No modern OS uses bios calls. No CPU is ever switched to RM again after booting up. They should get rid of this old stuff. > "Every modern x86 CPU". In the end, that's something to ask the CPU > vendors (but don't expect any answers). Some guesses: > > 1. Windows 7 uses BIOS calls (although they stopped switching back to > real mode for that, they use x86 16bit emulation. still, BIOS services > need to be there) > 2. CPUs might not be switched back to real mode today, but from 32bit > modes it's a pretty short route to vm86 modes, which are effectively > identical to real mode and still in use. > 3. Why change a working system and risk compatibility issues? x86's > biggest selling point is compatibility, and if you forfeit that, users > may move off your architecture entirely. > > > Regards, > Patrick

3 2

Re: [coreboot] Broadwell-U hangs at VGA init
by Zheng Bao 30 Jul '17

30 Jul '17

Fix a typo. Accessing upper area (like 0xc4030) of VGA bar0 causes hanging. Accessing lower area (like 0xa00a) is OK. Zheng ________________________________ From: coreboot <coreboot-bounces(a)coreboot.org> on behalf of Zheng Bao <fishbaoz(a)hotmail.com> Sent: Sunday, July 30, 2017 2:13 PM To: coreboot(a)coreboot.org; Matt DeVillier; stefan.reinauer(a)coreboot.org Subject: [coreboot] Broadwell-U hangs at VGA init I have got the mrc.bin and mem init has got passed. Now the new problem is that it hangs at VGA init. static void igd_setup_panel(struct device *dev) { config_t *conf = dev->chip_info; u32 reg32; /* Setup Digital Port Hotplug */ reg32 = gtt_read(PCH_PORT_HOTPLUG); <------- It hangs here. if (!reg32) { reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; gtt_write(PCH_PORT_HOTPLUG, reg32); } It turns out as soon as i access VGA bar0+0xc4030, it hangs. while accessing bar0 + 0xa00a is ok. To be exact, accessing upper area of VGA bar0 is OK. Accessing lower area causes hanging. I don't know the exact divison line. Any Idea? Zheng coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage starting... PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 08fe08fc 12400f35 6005e200 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: 0200 2024 4206 Previous Sleep State: S5 CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f CPU: AES supported, TXT supported, VT supported MCH: device id 1604 (rev 09) is Broadwell F0 PCH: device id 9cc3 (rev 03) is Broadwell U Premium IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W) CPU: frequency set to 2200 MHz SPD: index 0 (GPIO65=0 GPIO67=0 GPIO68=0 GPIO69=0) CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 54740 size 1000 SPD: module type is DDR3 SPD: module part is 99U5469-011.A01LF SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b ERROR: ME failed to respond FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = ffc00000 size = 400000 #areas = 3 MRC: no data in 'RW_MRC_CACHE' No MRC cache found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 36998 Starting Memory Reference Code Initializing Policy Installing common PPI MRC: Starting... Initializing Memory MRC: Done. MRC Version 2.6.0 Build 0 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank CBMEM: IMD: root @ 7cfff000 254 entries. IMD: root @ 7cffec00 62 entries. External stage cache: IMD: root @ 7d3ff000 254 entries. IMD: root @ 7d3fec00 62 entries. MRC data at ff7d0d9c 6246 bytes create cbmem for dimm information Missing Chromium EC memory map. Google Chrome set keyboard backlight: 0 status (23) Missing Chromium EC memory map. MLB: board version EVT4 CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 1c4c0 size 14197 Decompressing stage fallback/ramstage @ 0x7cf98fc0 (253008 bytes) Loading module at 7cf99000 with entry 7cf99000. filesize: 0x2bdc0 memsize: 0x3dc10 Processing 2798 relocs. Offset value of 0x7ce99000 coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 ramstage starting... Normal boot. BS: BS_PRE_DEVICE times (us): entry 5 run 8 exit 4 BS: BS_DEV_INIT_CHIPS times (us): entry 5 run 11 exit 4 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage starting... PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 08fe08fc 10400f35 6005e200 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: 0200 2024 4206 Previous Sleep State: S5 CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f CPU: AES supported, TXT supported, VT supported MCH: device id 1604 (rev 09) is Broadwell F0 PCH: device id 9cc3 (rev 03) is Broadwell U Premium IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W) CPU: frequency set to 2200 MHz SPD: index 0 (GPIO65=0 GPIO67=0 GPIO68=0 GPIO69=0) CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 54700 size 1000 SPD: module type is DDR3 SPD: module part is 99U5469-011.A01LF SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b ERROR: ME failed to respond FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = ffc00000 size = 400000 #areas = 3 MRC: no data in 'RW_MRC_CACHE' No MRC cache found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 36998 Starting Memory Reference Code Initializing Policy Installing common PPI MRC: Starting... Initializing Memory MRC: Done. MRC Version 2.6.0 Build 0 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank CBMEM: IMD: root @ 7cfff000 254 entries. IMD: root @ 7cffec00 62 entries. External stage cache: IMD: root @ 7d3ff000 254 entries. IMD: root @ 7d3fec00 62 entries. MRC data at ff7d0d9c 6246 bytes create cbmem for dimm information Missing Chromium EC memory map. Google Chrome set keyboard backlight: 0 status (23) Missing Chromium EC memory map. MLB: board version EVT4 CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 1c4c0 size 1417f Decompressing stage fallback/ramstage @ 0x7cf98fc0 (253008 bytes) Loading module at 7cf99000 with entry 7cf99000. filesize: 0x2bdc0 memsize: 0x3dc10 Processing 2798 relocs. Offset value of 0x7ce99000 coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 ramstage starting... Normal boot. BS: BS_PRE_DEVICE times (us): entry 5 run 7 exit 5 BS: BS_DEV_INIT_CHIPS times (us): entry 5 run 63 exit 5 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: 00:1f.6: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: 00:1f.6: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1604] enabled PCI: 00:02.0 [8086/0000] ops PCI: 00:02.0 [8086/1626] enabled PCI: 00:03.0 [8086/0000] ops PCI: 00:03.0 [8086/160c] enabled PCI: 00:13.0 [8086/0000] ops PCI: 00:13.0 [8086/9cb6] enabled PCI: 00:14.0 [8086/0000] ops PCI: 00:14.0 [8086/9cb1] enabled PCI: 00:15.0 [8086/0000] ops PCI: 00:15.0 [8086/9ce0] enabled PCI: 00:15.1 [8086/0000] ops PCI: 00:15.1 [8086/9ce1] enabled PCI: 00:15.2 [8086/0000] ops PCI: 00:15.2 [8086/9ce2] enabled PCI: 00:15.3 [8086/0000] ops PCI: 00:15.3 [8086/9ce5] enabled PCI: 00:15.4: Disabling device PCI: 00:15.5: Disabling device PCI: 00:15.6: Disabling device PCI: 00:16.0 [8086/0000] ops PCI: 00:16.0 [8086/9cba] enabled PCI: 00:16.1: Disabling device PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:17.0: Disabling device PCI: 00:19.0: Disabling device PCI: 00:1b.0 [8086/0000] ops HDA disabled, I/O buffers routed to ADSP PCI: 00:1b.0 [8086/9ca0] disabled PCI: 00:1c.0 [8086/0000] bus ops PCI: 00:1c.0 [8086/9c90] disabled PCI: 00:1c.1 [8086/0000] bus ops PCI: 00:1c.1 [8086/9c92] disabled PCI: 00:1c.2 [8086/0000] bus ops PCIe Root Port 3 ASPM is enabled PCI: 00:1c.2 [8086/9c94] enabled PCI: 00:1c.3 [8086/0000] bus ops PCI: 00:1c.3 [8086/9c96] disabled PCI: 00:1c.4 [8086/0000] bus ops PCI: 00:1c.4 [8086/9c98] disabled PCI: 00:1c.5 [8086/0000] bus ops PCI: 00:1c.0: Disabling device PCI: 00:1c.1: Disabling device PCI: 00:1c.3: Disabling device PCI: 00:1c.4: Disabling device PCI: 00:1c.4: Timeout waiting for 328h PCI: 00:1c.5: Disabling device PCI: 00:1c.5: Timeout waiting for 328h PCH: PCIe map 1c.2 -> 1c.0 PCH: PCIe map 1c.0 -> 1c.1 PCH: PCIe map 1c.1 -> 1c.2 PCH: RPFN 0x00543210 -> 0x00dcb0a9 PCI: 00:1c.5 [8086/9c9a] disabled PCI: 00:1d.0 [8086/0000] ops PCI: 00:1d.0 [8086/9ca6] disabled PCI: 00:1e.0: Disabling device PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/9cc3] enabled PCI: 00:1f.2 [8086/0000] ops PCI: 00:1f.2 [8086/9c83] enabled PCI: 00:1f.3: Disabling device PCI: 00:1f.6 [8086/9ca4] enabled PCI: 00:1c.0 scanning... do_pci_scan_bridge for PCI: 00:1c.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:1c.0 took 8283 usecs PCI: 00:1f.0 scanning... scan_lpc_bus for PCI: 00:1f.0 PNP: 0c31.0 enabled scan_lpc_bus for PCI: 00:1f.0 done scan_bus: scanning of bus PCI: 00:1f.0 took 9899 usecs scan_bus: scanning of bus DOMAIN: 0000 took 226481 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 244252 usecs done BS: BS_DEV_ENUMERATE times (us): entry 4 run 419116 exit 5 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xf0000000-0xf3ffffff. mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff. mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff. mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff. mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff. MC MAP: TOM: 0x200000000 MC MAP: TOUUD: 0x280000000 MC MAP: MESEG_BASE: 0x7ffff00000 MC MAP: MESEG_LIMIT: 0xfffff MC MAP: REMAP_BASE: 0x200000000 MC MAP: REMAP_LIMIT: 0x27fffffff MC MAP: TOLUD: 0x80000000 MC MAP: BGSM: 0x7d800000 MC MAP: BDSM: 0x7e000000 MC MAP: TESGMB: 0x7d000000 MC MAP: GGC: 0x1c1 PCI: 00:1c.0 read_resources bus 1 link: 0 PCI: 00:1c.0 read_resources bus 1 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PNP: 0c31.0 missing read_resources PCI: 00:1f.0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48 PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68 PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 10 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.1 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.2 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.3 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.4 PCI: 00:15.5 PCI: 00:15.6 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 20 align 12 gran 5 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:17.0 PCI: 00:19.0 PCI: 00:1b.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.0 PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1f.0 child on link 0 PNP: 0c31.0 PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 PNP: 0c31.0 PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 8000 align 15 gran 15 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.6 PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 20 * [0x0 - 0x3f] io PCI: 00:1f.2 20 * [0x40 - 0x5f] io PCI: 00:1f.2 10 * [0x60 - 0x67] io PCI: 00:1f.2 18 * [0x68 - 0x6f] io PCI: 00:1f.2 14 * [0x70 - 0x73] io PCI: 00:1f.2 1c * [0x74 - 0x77] io DOMAIN: 0000 io: base: 78 size: 78 align: 6 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem PCI: 00:13.0 10 * [0x11000000 - 0x110fffff] mem PCI: 00:14.0 10 * [0x11100000 - 0x1110ffff] mem PCI: 00:1f.2 24 * [0x11110000 - 0x11117fff] mem PCI: 00:03.0 10 * [0x11118000 - 0x1111bfff] mem PCI: 00:13.0 14 * [0x1111c000 - 0x1111cfff] mem PCI: 00:15.0 10 * [0x1111d000 - 0x1111dfff] mem PCI: 00:15.0 14 * [0x1111e000 - 0x1111efff] mem PCI: 00:15.1 10 * [0x1111f000 - 0x1111ffff] mem PCI: 00:15.1 14 * [0x11120000 - 0x11120fff] mem PCI: 00:15.2 10 * [0x11121000 - 0x11121fff] mem PCI: 00:15.2 14 * [0x11122000 - 0x11122fff] mem PCI: 00:15.3 10 * [0x11123000 - 0x11123fff] mem PCI: 00:15.3 14 * [0x11124000 - 0x11124fff] mem PCI: 00:1f.6 10 * [0x11125000 - 0x11125fff] mem PCI: 00:16.0 10 * [0x11126000 - 0x1112601f] mem DOMAIN: 0000 mem: base: 11126020 size: 11126020 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) constrain_resources: PCI: 00:00.0 01 base 000c0000 limit 7cffffff mem (fixed) constrain_resources: PCI: 00:00.0 02 base 7d000000 limit 7d7fffff mem (fixed) constrain_resources: PCI: 00:00.0 03 base 7d800000 limit 7fffffff mem (fixed) constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:1f.0 48 base 00001400 limit 000017ff io (fixed) skipping PNP: 0c31.0@70 fixed resource, size=0! avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001800 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff Setting resources... DOMAIN: 0000 io: base:1800 size:78 align:6 gran:0 limit:ffff PCI: 00:02.0 20 * [0x1800 - 0x183f] io PCI: 00:1f.2 20 * [0x1840 - 0x185f] io PCI: 00:1f.2 10 * [0x1860 - 0x1867] io PCI: 00:1f.2 18 * [0x1868 - 0x186f] io PCI: 00:1f.2 14 * [0x1870 - 0x1873] io PCI: 00:1f.2 1c * [0x1874 - 0x1877] io DOMAIN: 0000 io: next_base: 1878 size: 78 align: 6 gran: 0 done PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:d0000000 size:11126020 align:28 gran:0 limit:efffffff PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:02.0 10 * [0xe0000000 - 0xe0ffffff] mem PCI: 00:13.0 10 * [0xe1000000 - 0xe10fffff] mem PCI: 00:14.0 10 * [0xe1100000 - 0xe110ffff] mem PCI: 00:1f.2 24 * [0xe1110000 - 0xe1117fff] mem PCI: 00:03.0 10 * [0xe1118000 - 0xe111bfff] mem PCI: 00:13.0 14 * [0xe111c000 - 0xe111cfff] mem PCI: 00:15.0 10 * [0xe111d000 - 0xe111dfff] mem PCI: 00:15.0 14 * [0xe111e000 - 0xe111efff] mem PCI: 00:15.1 10 * [0xe111f000 - 0xe111ffff] mem PCI: 00:15.1 14 * [0xe1120000 - 0xe1120fff] mem PCI: 00:15.2 10 * [0xe1121000 - 0xe1121fff] mem PCI: 00:15.2 14 * [0xe1122000 - 0xe1122fff] mem PCI: 00:15.3 10 * [0xe1123000 - 0xe1123fff] mem PCI: 00:15.3 14 * [0xe1124000 - 0xe1124fff] mem PCI: 00:1f.6 10 * [0xe1125000 - 0xe1125fff] mem PCI: 00:16.0 10 * [0xe1126000 - 0xe112601f] mem DOMAIN: 0000 mem: next_base: e1126020 size: 11126020 align: 28 gran: 0 done PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff PCI: 00:1c.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e0ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io PCI: 00:03.0 10 <- [0x00e1118000 - 0x00e111bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 10 <- [0x00e1000000 - 0x00e10fffff] size 0x00100000 gran 0x14 mem PCI: 00:13.0 14 <- [0x00e111c000 - 0x00e111cfff] size 0x00001000 gran 0x0c mem PCI: 00:14.0 10 <- [0x00e1100000 - 0x00e110ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:15.0 10 <- [0x00e111d000 - 0x00e111dfff] size 0x00001000 gran 0x0c mem PCI: 00:15.0 14 <- [0x00e111e000 - 0x00e111efff] size 0x00001000 gran 0x0c mem PCI: 00:15.1 10 <- [0x00e111f000 - 0x00e111ffff] size 0x00001000 gran 0x0c mem PCI: 00:15.1 14 <- [0x00e1120000 - 0x00e1120fff] size 0x00001000 gran 0x0c mem PCI: 00:15.2 10 <- [0x00e1121000 - 0x00e1121fff] size 0x00001000 gran 0x0c mem PCI: 00:15.2 14 <- [0x00e1122000 - 0x00e1122fff] size 0x00001000 gran 0x0c mem PCI: 00:15.3 10 <- [0x00e1123000 - 0x00e1123fff] size 0x00001000 gran 0x0c mem PCI: 00:15.3 14 <- [0x00e1124000 - 0x00e1124fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00e1126000 - 0x00e112601f] size 0x00000020 gran 0x05 mem64 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:1f.0 assign_resources, bus 0 link: 0 PNP: 0c31.0 missing set_resources PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.2 10 <- [0x0000001860 - 0x0000001867] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x0000001870 - 0x0000001873] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x0000001868 - 0x000000186f] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x0000001874 - 0x0000001877] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00e1110000 - 0x00e1117fff] size 0x00008000 gran 0x0f mem PCI: 00:1f.6 10 <- [0x00e1125000 - 0x00e1125fff] size 0x00001000 gran 0x0c mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1800 size 78 align 6 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base d0000000 size 11126020 align 28 gran 0 limit efffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48 PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68 PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:02.0 PCI: 00:02.0 resource base e0000000 size 1000000 align 24 gran 24 limit e0ffffff flags 60000201 index 10 PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit 183f flags 60000100 index 20 PCI: 00:03.0 PCI: 00:03.0 resource base e1118000 size 4000 align 14 gran 14 limit e111bfff flags 60000201 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base e1000000 size 100000 align 20 gran 20 limit e10fffff flags 60000200 index 10 PCI: 00:13.0 resource base e111c000 size 1000 align 12 gran 12 limit e111cfff flags 60000200 index 14 PCI: 00:14.0 PCI: 00:14.0 resource base e1100000 size 10000 align 16 gran 16 limit e110ffff flags 60000201 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base e111d000 size 1000 align 12 gran 12 limit e111dfff flags 60000200 index 10 PCI: 00:15.0 resource base e111e000 size 1000 align 12 gran 12 limit e111efff flags 60000200 index 14 PCI: 00:15.1 PCI: 00:15.1 resource base e111f000 size 1000 align 12 gran 12 limit e111ffff flags 60000200 index 10 PCI: 00:15.1 resource base e1120000 size 1000 align 12 gran 12 limit e1120fff flags 60000200 index 14 PCI: 00:15.2 PCI: 00:15.2 resource base e1121000 size 1000 align 12 gran 12 limit e1121fff flags 60000200 index 10 PCI: 00:15.2 resource base e1122000 size 1000 align 12 gran 12 limit e1122fff flags 60000200 index 14 PCI: 00:15.3 PCI: 00:15.3 resource base e1123000 size 1000 align 12 gran 12 limit e1123fff flags 60000200 index 10 PCI: 00:15.3 resource base e1124000 size 1000 align 12 gran 12 limit e1124fff flags 60000200 index 14 PCI: 00:15.4 PCI: 00:15.5 PCI: 00:15.6 PCI: 00:16.0 PCI: 00:16.0 resource base e1126000 size 20 align 12 gran 5 limit e112601f flags 60000201 index 10 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:17.0 PCI: 00:19.0 PCI: 00:1b.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.0 PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1f.0 child on link 0 PNP: 0c31.0 PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 PNP: 0c31.0 PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.2 PCI: 00:1f.2 resource base 1860 size 8 align 3 gran 3 limit 1867 flags 60000100 index 10 PCI: 00:1f.2 resource base 1870 size 4 align 2 gran 2 limit 1873 flags 60000100 index 14 PCI: 00:1f.2 resource base 1868 size 8 align 3 gran 3 limit 186f flags 60000100 index 18 PCI: 00:1f.2 resource base 1874 size 4 align 2 gran 2 limit 1877 flags 60000100 index 1c PCI: 00:1f.2 resource base 1840 size 20 align 5 gran 5 limit 185f flags 60000100 index 20 PCI: 00:1f.2 resource base e1110000 size 8000 align 15 gran 15 limit e1117fff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.6 PCI: 00:1f.6 resource base e1125000 size 1000 align 12 gran 12 limit e1125fff flags 60000201 index 10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 4 run 1651192 exit 4 Enabling resources... PCI: 00:00.0 subsystem <- 8086/1604 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/1626 PCI: 00:02.0 cmd <- 07 PCI: 00:03.0 subsystem <- 8086/160c PCI: 00:03.0 cmd <- 07 PCI: 00:13.0 subsystem <- 8086/9cb6 PCI: 00:13.0 cmd <- 107 PCI: 00:14.0 subsystem <- 8086/9cb1 PCI: 00:14.0 cmd <- 107 PCI: 00:15.0 subsystem <- 8086/9ce0 PCI: 00:15.0 cmd <- 107 PCI: 00:15.1 subsystem <- 8086/9ce1 PCI: 00:15.1 cmd <- 107 PCI: 00:15.2 subsystem <- 8086/9ce2 PCI: 00:15.2 cmd <- 107 PCI: 00:15.3 subsystem <- 8086/9ce5 PCI: 00:15.3 cmd <- 107 PCI: 00:16.0 subsystem <- 8086/9cba PCI: 00:16.0 cmd <- 07 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/9c94 PCI: 00:1c.0 cmd <- 05 PCI: 00:1f.0 subsystem <- 8086/9cc3 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 8086/9c83 PCI: 00:1f.2 cmd <- 107 PCI: 00:1f.6 subsystem <- 8086/9ca4 PCI: 00:1f.6 cmd <- 107 done. BS: BS_DEV_ENABLE times (us): entry 4 run 80531 exit 4 Initializing devices... Root Device init ... mainboard_init mainboard_ec_init Chrome EC: Set WAKE mask to 0x00000000 Missing Chromium EC memory map. Root Device init finished in 11325 usecs CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007d800000 size 0x7d740000 type 6 0x000000007d800000 - 0x00000000d0000000 size 0x52800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x0000000280000000 size 0x180000000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 call enable_fixed_mtrr() CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 6/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x000000007d800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000007ffe000000 type 0 MTRR: 3 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Initializing VR config. PCODE: 24MHz BLCK calibration response: 0 PCODE: 24MHz BLCK calibration value: 0x8506531c PCH Power: PCODE Levels 0x3f245102 0x0058f38a CPU has 2 cores, 4 threads enabled. Setting up SMI for CPU Will perform SMM setup. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset b000 size 11440 microcode: sig=0x306d4 pf=0x40 revision=0x1f CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz. Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 3 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 2 apic_id 2. AP: slot 3 apic_id 3. done. AP: slot 1 apic_id 1. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 12 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7cfaf73d(00000000) Installing SMM handler to 0x7d000000 Loading module at 7d010000 with entry 7d010070. filesize: 0xfc8 memsize: 0x4fe8 Processing 36 relocs. Offset value of 0x7d010000 Loading module at 7d008000 with entry 7d008000. filesize: 0x1a8 memsize: 0x1a8 Processing 12 relocs. Offset value of 0x7d008000 SMM Module: placing jmp sequence at 7d007c00 rel16 0x03fd SMM Module: placing jmp sequence at 7d007800 rel16 0x07fd SMM Module: placing jmp sequence at 7d007400 rel16 0x0bfd SMM Module: stub loaded at 7d008000. Will call 7d010070(00000000) Initializing Southbridge SMI... ... pmbase = 0x1000 SMI_STS: TCO PM1 PM1_STS: TMROF New SMBASE 0x7d000000 In relocation handler: CPU 0 New SMBASE=0x7d000000 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfffc00 In relocation handler: CPU 1 New SMBASE=0x7cfffc00 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfff800 In relocation handler: CPU 2 New SMBASE=0x7cfff800 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfff400 In relocation handler: CPU 3 New SMBASE=0x7cfff400 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC... apic_id: 0x00 done. VMX status: enabled, locked cpu: energy policy set to 6 Turbo is available but hidden Turbo has been enabled CPU #0 initialized Initializing CPU #1 Initializing CPU #3 Initializing CPU #2 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC...Setting up local APIC... apic_id: 0x03 done. apic_id: 0x02 done. VMX status: enabled, locked VMX status: enabled, locked cpu: energy policy set to 6 cpu: energy policy set to 6 CPU #2 initialized CPU #3 initialized CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC... apic_id: 0x01 done. VMX status: enabled, locked cpu: energy policy set to 6 CPU #1 initialized cpu: frequency set to 3200 Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 443170 usecs PCI: 00:00.0 init ... Set BIOS_RESET_CPL CPU TDP: 15 Watts PCI: 00:00.0 init finished in 6390 usecs PCI: 00:02.0 init ... igd_init,500 igd_init,506 igd_init,512 igd_init,523 addr=e000a000 igd_init,538 addr=e000a008 igd_init,543 igd_setup_panel,305 addr=e00c4030

1 0

Broadwell-U hangs at VGA init
by Zheng Bao 30 Jul '17

30 Jul '17

I have got the mrc.bin and mem init has got passed. Now the new problem is that it hangs at VGA init. static void igd_setup_panel(struct device *dev) { config_t *conf = dev->chip_info; u32 reg32; /* Setup Digital Port Hotplug */ reg32 = gtt_read(PCH_PORT_HOTPLUG); <------- It hangs here. if (!reg32) { reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; gtt_write(PCH_PORT_HOTPLUG, reg32); } It turns out as soon as i access VGA bar0+0xc4030, it hangs. while accessing bar0 + 0xa00a is ok. To be exact, accessing upper area of VGA bar0 is OK. Accessing lower area causes hanging. I don't know the exact divison line. Any Idea? Zheng coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage starting... PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 08fe08fc 12400f35 6005e200 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: 0200 2024 4206 Previous Sleep State: S5 CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f CPU: AES supported, TXT supported, VT supported MCH: device id 1604 (rev 09) is Broadwell F0 PCH: device id 9cc3 (rev 03) is Broadwell U Premium IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W) CPU: frequency set to 2200 MHz SPD: index 0 (GPIO65=0 GPIO67=0 GPIO68=0 GPIO69=0) CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 54740 size 1000 SPD: module type is DDR3 SPD: module part is 99U5469-011.A01LF SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b ERROR: ME failed to respond FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = ffc00000 size = 400000 #areas = 3 MRC: no data in 'RW_MRC_CACHE' No MRC cache found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 36998 Starting Memory Reference Code Initializing Policy Installing common PPI MRC: Starting... Initializing Memory MRC: Done. MRC Version 2.6.0 Build 0 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank CBMEM: IMD: root @ 7cfff000 254 entries. IMD: root @ 7cffec00 62 entries. External stage cache: IMD: root @ 7d3ff000 254 entries. IMD: root @ 7d3fec00 62 entries. MRC data at ff7d0d9c 6246 bytes create cbmem for dimm information Missing Chromium EC memory map. Google Chrome set keyboard backlight: 0 status (23) Missing Chromium EC memory map. MLB: board version EVT4 CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 1c4c0 size 14197 Decompressing stage fallback/ramstage @ 0x7cf98fc0 (253008 bytes) Loading module at 7cf99000 with entry 7cf99000. filesize: 0x2bdc0 memsize: 0x3dc10 Processing 2798 relocs. Offset value of 0x7ce99000 coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 ramstage starting... Normal boot. BS: BS_PRE_DEVICE times (us): entry 5 run 8 exit 4 BS: BS_DEV_INIT_CHIPS times (us): entry 5 run 11 exit 4 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage starting... PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 08fe08fc 10400f35 6005e200 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: 0200 2024 4206 Previous Sleep State: S5 CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f CPU: AES supported, TXT supported, VT supported MCH: device id 1604 (rev 09) is Broadwell F0 PCH: device id 9cc3 (rev 03) is Broadwell U Premium IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W) CPU: frequency set to 2200 MHz SPD: index 0 (GPIO65=0 GPIO67=0 GPIO68=0 GPIO69=0) CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 54700 size 1000 SPD: module type is DDR3 SPD: module part is 99U5469-011.A01LF SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b ERROR: ME failed to respond FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = ffc00000 size = 400000 #areas = 3 MRC: no data in 'RW_MRC_CACHE' No MRC cache found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 36998 Starting Memory Reference Code Initializing Policy Installing common PPI MRC: Starting... Initializing Memory MRC: Done. MRC Version 2.6.0 Build 0 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank CBMEM: IMD: root @ 7cfff000 254 entries. IMD: root @ 7cffec00 62 entries. External stage cache: IMD: root @ 7d3ff000 254 entries. IMD: root @ 7d3fec00 62 entries. MRC data at ff7d0d9c 6246 bytes create cbmem for dimm information Missing Chromium EC memory map. Google Chrome set keyboard backlight: 0 status (23) Missing Chromium EC memory map. MLB: board version EVT4 CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 1c4c0 size 1417f Decompressing stage fallback/ramstage @ 0x7cf98fc0 (253008 bytes) Loading module at 7cf99000 with entry 7cf99000. filesize: 0x2bdc0 memsize: 0x3dc10 Processing 2798 relocs. Offset value of 0x7ce99000 coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 ramstage starting... Normal boot. BS: BS_PRE_DEVICE times (us): entry 5 run 7 exit 5 BS: BS_DEV_INIT_CHIPS times (us): entry 5 run 63 exit 5 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: 00:1f.6: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: 00:1f.6: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1604] enabled PCI: 00:02.0 [8086/0000] ops PCI: 00:02.0 [8086/1626] enabled PCI: 00:03.0 [8086/0000] ops PCI: 00:03.0 [8086/160c] enabled PCI: 00:13.0 [8086/0000] ops PCI: 00:13.0 [8086/9cb6] enabled PCI: 00:14.0 [8086/0000] ops PCI: 00:14.0 [8086/9cb1] enabled PCI: 00:15.0 [8086/0000] ops PCI: 00:15.0 [8086/9ce0] enabled PCI: 00:15.1 [8086/0000] ops PCI: 00:15.1 [8086/9ce1] enabled PCI: 00:15.2 [8086/0000] ops PCI: 00:15.2 [8086/9ce2] enabled PCI: 00:15.3 [8086/0000] ops PCI: 00:15.3 [8086/9ce5] enabled PCI: 00:15.4: Disabling device PCI: 00:15.5: Disabling device PCI: 00:15.6: Disabling device PCI: 00:16.0 [8086/0000] ops PCI: 00:16.0 [8086/9cba] enabled PCI: 00:16.1: Disabling device PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:17.0: Disabling device PCI: 00:19.0: Disabling device PCI: 00:1b.0 [8086/0000] ops HDA disabled, I/O buffers routed to ADSP PCI: 00:1b.0 [8086/9ca0] disabled PCI: 00:1c.0 [8086/0000] bus ops PCI: 00:1c.0 [8086/9c90] disabled PCI: 00:1c.1 [8086/0000] bus ops PCI: 00:1c.1 [8086/9c92] disabled PCI: 00:1c.2 [8086/0000] bus ops PCIe Root Port 3 ASPM is enabled PCI: 00:1c.2 [8086/9c94] enabled PCI: 00:1c.3 [8086/0000] bus ops PCI: 00:1c.3 [8086/9c96] disabled PCI: 00:1c.4 [8086/0000] bus ops PCI: 00:1c.4 [8086/9c98] disabled PCI: 00:1c.5 [8086/0000] bus ops PCI: 00:1c.0: Disabling device PCI: 00:1c.1: Disabling device PCI: 00:1c.3: Disabling device PCI: 00:1c.4: Disabling device PCI: 00:1c.4: Timeout waiting for 328h PCI: 00:1c.5: Disabling device PCI: 00:1c.5: Timeout waiting for 328h PCH: PCIe map 1c.2 -> 1c.0 PCH: PCIe map 1c.0 -> 1c.1 PCH: PCIe map 1c.1 -> 1c.2 PCH: RPFN 0x00543210 -> 0x00dcb0a9 PCI: 00:1c.5 [8086/9c9a] disabled PCI: 00:1d.0 [8086/0000] ops PCI: 00:1d.0 [8086/9ca6] disabled PCI: 00:1e.0: Disabling device PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/9cc3] enabled PCI: 00:1f.2 [8086/0000] ops PCI: 00:1f.2 [8086/9c83] enabled PCI: 00:1f.3: Disabling device PCI: 00:1f.6 [8086/9ca4] enabled PCI: 00:1c.0 scanning... do_pci_scan_bridge for PCI: 00:1c.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:1c.0 took 8283 usecs PCI: 00:1f.0 scanning... scan_lpc_bus for PCI: 00:1f.0 PNP: 0c31.0 enabled scan_lpc_bus for PCI: 00:1f.0 done scan_bus: scanning of bus PCI: 00:1f.0 took 9899 usecs scan_bus: scanning of bus DOMAIN: 0000 took 226481 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 244252 usecs done BS: BS_DEV_ENUMERATE times (us): entry 4 run 419116 exit 5 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xf0000000-0xf3ffffff. mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff. mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff. mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff. mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff. MC MAP: TOM: 0x200000000 MC MAP: TOUUD: 0x280000000 MC MAP: MESEG_BASE: 0x7ffff00000 MC MAP: MESEG_LIMIT: 0xfffff MC MAP: REMAP_BASE: 0x200000000 MC MAP: REMAP_LIMIT: 0x27fffffff MC MAP: TOLUD: 0x80000000 MC MAP: BGSM: 0x7d800000 MC MAP: BDSM: 0x7e000000 MC MAP: TESGMB: 0x7d000000 MC MAP: GGC: 0x1c1 PCI: 00:1c.0 read_resources bus 1 link: 0 PCI: 00:1c.0 read_resources bus 1 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PNP: 0c31.0 missing read_resources PCI: 00:1f.0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48 PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68 PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 10 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.1 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.2 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.3 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.4 PCI: 00:15.5 PCI: 00:15.6 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 20 align 12 gran 5 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:17.0 PCI: 00:19.0 PCI: 00:1b.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.0 PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1f.0 child on link 0 PNP: 0c31.0 PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 PNP: 0c31.0 PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 8000 align 15 gran 15 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.6 PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 20 * [0x0 - 0x3f] io PCI: 00:1f.2 20 * [0x40 - 0x5f] io PCI: 00:1f.2 10 * [0x60 - 0x67] io PCI: 00:1f.2 18 * [0x68 - 0x6f] io PCI: 00:1f.2 14 * [0x70 - 0x73] io PCI: 00:1f.2 1c * [0x74 - 0x77] io DOMAIN: 0000 io: base: 78 size: 78 align: 6 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem PCI: 00:13.0 10 * [0x11000000 - 0x110fffff] mem PCI: 00:14.0 10 * [0x11100000 - 0x1110ffff] mem PCI: 00:1f.2 24 * [0x11110000 - 0x11117fff] mem PCI: 00:03.0 10 * [0x11118000 - 0x1111bfff] mem PCI: 00:13.0 14 * [0x1111c000 - 0x1111cfff] mem PCI: 00:15.0 10 * [0x1111d000 - 0x1111dfff] mem PCI: 00:15.0 14 * [0x1111e000 - 0x1111efff] mem PCI: 00:15.1 10 * [0x1111f000 - 0x1111ffff] mem PCI: 00:15.1 14 * [0x11120000 - 0x11120fff] mem PCI: 00:15.2 10 * [0x11121000 - 0x11121fff] mem PCI: 00:15.2 14 * [0x11122000 - 0x11122fff] mem PCI: 00:15.3 10 * [0x11123000 - 0x11123fff] mem PCI: 00:15.3 14 * [0x11124000 - 0x11124fff] mem PCI: 00:1f.6 10 * [0x11125000 - 0x11125fff] mem PCI: 00:16.0 10 * [0x11126000 - 0x1112601f] mem DOMAIN: 0000 mem: base: 11126020 size: 11126020 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) constrain_resources: PCI: 00:00.0 01 base 000c0000 limit 7cffffff mem (fixed) constrain_resources: PCI: 00:00.0 02 base 7d000000 limit 7d7fffff mem (fixed) constrain_resources: PCI: 00:00.0 03 base 7d800000 limit 7fffffff mem (fixed) constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:1f.0 48 base 00001400 limit 000017ff io (fixed) skipping PNP: 0c31.0@70 fixed resource, size=0! avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001800 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff Setting resources... DOMAIN: 0000 io: base:1800 size:78 align:6 gran:0 limit:ffff PCI: 00:02.0 20 * [0x1800 - 0x183f] io PCI: 00:1f.2 20 * [0x1840 - 0x185f] io PCI: 00:1f.2 10 * [0x1860 - 0x1867] io PCI: 00:1f.2 18 * [0x1868 - 0x186f] io PCI: 00:1f.2 14 * [0x1870 - 0x1873] io PCI: 00:1f.2 1c * [0x1874 - 0x1877] io DOMAIN: 0000 io: next_base: 1878 size: 78 align: 6 gran: 0 done PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:d0000000 size:11126020 align:28 gran:0 limit:efffffff PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:02.0 10 * [0xe0000000 - 0xe0ffffff] mem PCI: 00:13.0 10 * [0xe1000000 - 0xe10fffff] mem PCI: 00:14.0 10 * [0xe1100000 - 0xe110ffff] mem PCI: 00:1f.2 24 * [0xe1110000 - 0xe1117fff] mem PCI: 00:03.0 10 * [0xe1118000 - 0xe111bfff] mem PCI: 00:13.0 14 * [0xe111c000 - 0xe111cfff] mem PCI: 00:15.0 10 * [0xe111d000 - 0xe111dfff] mem PCI: 00:15.0 14 * [0xe111e000 - 0xe111efff] mem PCI: 00:15.1 10 * [0xe111f000 - 0xe111ffff] mem PCI: 00:15.1 14 * [0xe1120000 - 0xe1120fff] mem PCI: 00:15.2 10 * [0xe1121000 - 0xe1121fff] mem PCI: 00:15.2 14 * [0xe1122000 - 0xe1122fff] mem PCI: 00:15.3 10 * [0xe1123000 - 0xe1123fff] mem PCI: 00:15.3 14 * [0xe1124000 - 0xe1124fff] mem PCI: 00:1f.6 10 * [0xe1125000 - 0xe1125fff] mem PCI: 00:16.0 10 * [0xe1126000 - 0xe112601f] mem DOMAIN: 0000 mem: next_base: e1126020 size: 11126020 align: 28 gran: 0 done PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff PCI: 00:1c.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e0ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io PCI: 00:03.0 10 <- [0x00e1118000 - 0x00e111bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 10 <- [0x00e1000000 - 0x00e10fffff] size 0x00100000 gran 0x14 mem PCI: 00:13.0 14 <- [0x00e111c000 - 0x00e111cfff] size 0x00001000 gran 0x0c mem PCI: 00:14.0 10 <- [0x00e1100000 - 0x00e110ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:15.0 10 <- [0x00e111d000 - 0x00e111dfff] size 0x00001000 gran 0x0c mem PCI: 00:15.0 14 <- [0x00e111e000 - 0x00e111efff] size 0x00001000 gran 0x0c mem PCI: 00:15.1 10 <- [0x00e111f000 - 0x00e111ffff] size 0x00001000 gran 0x0c mem PCI: 00:15.1 14 <- [0x00e1120000 - 0x00e1120fff] size 0x00001000 gran 0x0c mem PCI: 00:15.2 10 <- [0x00e1121000 - 0x00e1121fff] size 0x00001000 gran 0x0c mem PCI: 00:15.2 14 <- [0x00e1122000 - 0x00e1122fff] size 0x00001000 gran 0x0c mem PCI: 00:15.3 10 <- [0x00e1123000 - 0x00e1123fff] size 0x00001000 gran 0x0c mem PCI: 00:15.3 14 <- [0x00e1124000 - 0x00e1124fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00e1126000 - 0x00e112601f] size 0x00000020 gran 0x05 mem64 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:1f.0 assign_resources, bus 0 link: 0 PNP: 0c31.0 missing set_resources PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.2 10 <- [0x0000001860 - 0x0000001867] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x0000001870 - 0x0000001873] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x0000001868 - 0x000000186f] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x0000001874 - 0x0000001877] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00e1110000 - 0x00e1117fff] size 0x00008000 gran 0x0f mem PCI: 00:1f.6 10 <- [0x00e1125000 - 0x00e1125fff] size 0x00001000 gran 0x0c mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1800 size 78 align 6 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base d0000000 size 11126020 align 28 gran 0 limit efffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48 PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68 PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:02.0 PCI: 00:02.0 resource base e0000000 size 1000000 align 24 gran 24 limit e0ffffff flags 60000201 index 10 PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit 183f flags 60000100 index 20 PCI: 00:03.0 PCI: 00:03.0 resource base e1118000 size 4000 align 14 gran 14 limit e111bfff flags 60000201 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base e1000000 size 100000 align 20 gran 20 limit e10fffff flags 60000200 index 10 PCI: 00:13.0 resource base e111c000 size 1000 align 12 gran 12 limit e111cfff flags 60000200 index 14 PCI: 00:14.0 PCI: 00:14.0 resource base e1100000 size 10000 align 16 gran 16 limit e110ffff flags 60000201 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base e111d000 size 1000 align 12 gran 12 limit e111dfff flags 60000200 index 10 PCI: 00:15.0 resource base e111e000 size 1000 align 12 gran 12 limit e111efff flags 60000200 index 14 PCI: 00:15.1 PCI: 00:15.1 resource base e111f000 size 1000 align 12 gran 12 limit e111ffff flags 60000200 index 10 PCI: 00:15.1 resource base e1120000 size 1000 align 12 gran 12 limit e1120fff flags 60000200 index 14 PCI: 00:15.2 PCI: 00:15.2 resource base e1121000 size 1000 align 12 gran 12 limit e1121fff flags 60000200 index 10 PCI: 00:15.2 resource base e1122000 size 1000 align 12 gran 12 limit e1122fff flags 60000200 index 14 PCI: 00:15.3 PCI: 00:15.3 resource base e1123000 size 1000 align 12 gran 12 limit e1123fff flags 60000200 index 10 PCI: 00:15.3 resource base e1124000 size 1000 align 12 gran 12 limit e1124fff flags 60000200 index 14 PCI: 00:15.4 PCI: 00:15.5 PCI: 00:15.6 PCI: 00:16.0 PCI: 00:16.0 resource base e1126000 size 20 align 12 gran 5 limit e112601f flags 60000201 index 10 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:17.0 PCI: 00:19.0 PCI: 00:1b.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.0 PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1f.0 child on link 0 PNP: 0c31.0 PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 PNP: 0c31.0 PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.2 PCI: 00:1f.2 resource base 1860 size 8 align 3 gran 3 limit 1867 flags 60000100 index 10 PCI: 00:1f.2 resource base 1870 size 4 align 2 gran 2 limit 1873 flags 60000100 index 14 PCI: 00:1f.2 resource base 1868 size 8 align 3 gran 3 limit 186f flags 60000100 index 18 PCI: 00:1f.2 resource base 1874 size 4 align 2 gran 2 limit 1877 flags 60000100 index 1c PCI: 00:1f.2 resource base 1840 size 20 align 5 gran 5 limit 185f flags 60000100 index 20 PCI: 00:1f.2 resource base e1110000 size 8000 align 15 gran 15 limit e1117fff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.6 PCI: 00:1f.6 resource base e1125000 size 1000 align 12 gran 12 limit e1125fff flags 60000201 index 10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 4 run 1651192 exit 4 Enabling resources... PCI: 00:00.0 subsystem <- 8086/1604 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/1626 PCI: 00:02.0 cmd <- 07 PCI: 00:03.0 subsystem <- 8086/160c PCI: 00:03.0 cmd <- 07 PCI: 00:13.0 subsystem <- 8086/9cb6 PCI: 00:13.0 cmd <- 107 PCI: 00:14.0 subsystem <- 8086/9cb1 PCI: 00:14.0 cmd <- 107 PCI: 00:15.0 subsystem <- 8086/9ce0 PCI: 00:15.0 cmd <- 107 PCI: 00:15.1 subsystem <- 8086/9ce1 PCI: 00:15.1 cmd <- 107 PCI: 00:15.2 subsystem <- 8086/9ce2 PCI: 00:15.2 cmd <- 107 PCI: 00:15.3 subsystem <- 8086/9ce5 PCI: 00:15.3 cmd <- 107 PCI: 00:16.0 subsystem <- 8086/9cba PCI: 00:16.0 cmd <- 07 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/9c94 PCI: 00:1c.0 cmd <- 05 PCI: 00:1f.0 subsystem <- 8086/9cc3 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 8086/9c83 PCI: 00:1f.2 cmd <- 107 PCI: 00:1f.6 subsystem <- 8086/9ca4 PCI: 00:1f.6 cmd <- 107 done. BS: BS_DEV_ENABLE times (us): entry 4 run 80531 exit 4 Initializing devices... Root Device init ... mainboard_init mainboard_ec_init Chrome EC: Set WAKE mask to 0x00000000 Missing Chromium EC memory map. Root Device init finished in 11325 usecs CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007d800000 size 0x7d740000 type 6 0x000000007d800000 - 0x00000000d0000000 size 0x52800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x0000000280000000 size 0x180000000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 call enable_fixed_mtrr() CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 6/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x000000007d800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000007ffe000000 type 0 MTRR: 3 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Initializing VR config. PCODE: 24MHz BLCK calibration response: 0 PCODE: 24MHz BLCK calibration value: 0x8506531c PCH Power: PCODE Levels 0x3f245102 0x0058f38a CPU has 2 cores, 4 threads enabled. Setting up SMI for CPU Will perform SMM setup. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset b000 size 11440 microcode: sig=0x306d4 pf=0x40 revision=0x1f CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz. Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 3 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 2 apic_id 2. AP: slot 3 apic_id 3. done. AP: slot 1 apic_id 1. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 12 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7cfaf73d(00000000) Installing SMM handler to 0x7d000000 Loading module at 7d010000 with entry 7d010070. filesize: 0xfc8 memsize: 0x4fe8 Processing 36 relocs. Offset value of 0x7d010000 Loading module at 7d008000 with entry 7d008000. filesize: 0x1a8 memsize: 0x1a8 Processing 12 relocs. Offset value of 0x7d008000 SMM Module: placing jmp sequence at 7d007c00 rel16 0x03fd SMM Module: placing jmp sequence at 7d007800 rel16 0x07fd SMM Module: placing jmp sequence at 7d007400 rel16 0x0bfd SMM Module: stub loaded at 7d008000. Will call 7d010070(00000000) Initializing Southbridge SMI... ... pmbase = 0x1000 SMI_STS: TCO PM1 PM1_STS: TMROF New SMBASE 0x7d000000 In relocation handler: CPU 0 New SMBASE=0x7d000000 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfffc00 In relocation handler: CPU 1 New SMBASE=0x7cfffc00 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfff800 In relocation handler: CPU 2 New SMBASE=0x7cfff800 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfff400 In relocation handler: CPU 3 New SMBASE=0x7cfff400 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC... apic_id: 0x00 done. VMX status: enabled, locked cpu: energy policy set to 6 Turbo is available but hidden Turbo has been enabled CPU #0 initialized Initializing CPU #1 Initializing CPU #3 Initializing CPU #2 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC...Setting up local APIC... apic_id: 0x03 done. apic_id: 0x02 done. VMX status: enabled, locked VMX status: enabled, locked cpu: energy policy set to 6 cpu: energy policy set to 6 CPU #2 initialized CPU #3 initialized CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC... apic_id: 0x01 done. VMX status: enabled, locked cpu: energy policy set to 6 CPU #1 initialized cpu: frequency set to 3200 Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 443170 usecs PCI: 00:00.0 init ... Set BIOS_RESET_CPL CPU TDP: 15 Watts PCI: 00:00.0 init finished in 6390 usecs PCI: 00:02.0 init ... igd_init,500 igd_init,506 igd_init,512 igd_init,523 addr=e000a000 igd_init,538 addr=e000a008 igd_init,543 igd_setup_panel,305 addr=e00c4030

1 0

[FWD: Request for Chromebook Authentication Module Development]
by victor 30 Jul '17

30 Jul '17

Hi We are looking for developers to develop an authentication module in the standard Chromebook OS/firmware. 1) The purpose of this authentication module is to ‘lock' the device at factory during manufacturing. A lock PIN consist of 10-12 numeric is written to the device memory. 2) During first boot up, the device will prompt for a login pin. 3) If there is a matched between the login pin and the lock pin stored in the device memory, the Chromebook will be ‘unlocked’ and normal operation can proceed. If the PIN numbers are not matched, the Chromebook will remain lock. (see attached flow-chart) 4) The development needs not be confined to only firmware. We are open to all options (example thru apps) so long the authentication process can be achieved. We are writing to request whether if any Chromebook expert/specialist can provide Non-recurring engineering (NRE) services for the development. Please do contact the undersign should you require more info. Hope to hear from you. Regards, Victor -- Best Regards Victor Chng Send from my iphone -- Best Regards Victor Chng Send from my iphone

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Re: [coreboot] Haswell port
by Nico Huber 29 Jul '17

29 Jul '17

Hi Konstantin, On 29.07.2017 06:57, Konstantin Novikov wrote: > Hello again, coreboot community! > > Thanks a lot Zoran Stojsavljevic and Nico Huber for their help and answers. > You're lead us in "GFX-way", so it was a right direction. > At first, we're added our PCI id in two structures (map_oprom_vendev and > pci_device_ids) in northbridge/intel/haswell/gma.c. But after this we're > see only black screen on display, no any BIOS/Linux output. > gma_setup_panel(dev) > - this function was critical for us. > > gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | > DDI_INIT_DISPLAY_DETECTED); good catch! I suppose you are using an analog VGA port then? Are you going to submit a patch? We might want to add a devicetree setting for this in `haswell/chip.h`. I could have a look at it too if you want. Nico > Without DDI_A_4_LANES in this row we saw the Linux Ubuntu output (without > any errors) and logging screen. After trying to use some VGA BIOS we're see > BIOS output and bootsplash too. Linux Ubuntu works correct, fully > reinstalled and loaded. > > Again, thanks Nico and Zoran (от всей души) for help. Coreboot community > are awesome. > > Konstantin Novikov. >

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Re: [coreboot] Haswell port
by Peter Stuge 29 Jul '17

29 Jul '17

Konstantin Novikov wrote: > gma_setup_panel(dev) > - this function was critical for us. > > gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | > DDI_INIT_DISPLAY_DETECTED); > Without DDI_A_4_LANES in this row we saw the Linux Ubuntu output Should this perhaps become a Kconfig option to be selected (or not) by mainboards? //Peter

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Re: [coreboot] How can we get MRC.bin for Intel platform.
by Matt DeVillier 29 Jul '17

29 Jul '17

Since your board is a Broadwell-U, easiest way will be to extract it (along with the required refcode blob) from the generic/shellball image firmware for a Broadwell-U Chromebook (using cbfstool), which itself can be extracted from a ChromeOS recovery image. John Lewis wrote up some helpful instructions here: https://johnlewis.ie/extracting-the-shell-ball-rom-using-a-chromeos-image/ I'd recommend using the image for 'SAMUS', the Google Chromebook Pixel2. On Sat, Jul 29, 2017 at 3:31 AM, Zheng Bao <fishbaoz(a)hotmail.com> wrote: > Hi, All, > I am debugging a i7-5650 board. I use IBV's BIOS to wrap the coreboot, > i.e, replace the BIOS Region with coreboot.rom. > So I assume the ME blob can work. > I wonder if it is the right way. > > Is it fully supported by Coreboot? > How can we get MRC.bin and other blobs? > > Thanks. > > Zheng > > coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage > starting... > PM1_STS: 0000 > PM1_EN: 0000 > PM1_CNT: 00000000 > TCO_STS: 0000 0000 > GPE0_STS: 08fe08fc 12400f35 6005e200 00000000 > GPE0_EN: 00000000 00000000 00000000 00000000 > GEN_PMCON: 0200 2024 4206 > Previous Sleep State: S5 > CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz > CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f > CPU: AES supported, TXT supported, VT supported > MCH: device id 1604 (rev 09) is Broadwell F0 > PCH: device id 9cc3 (rev 03) is Broadwell U Premium > IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W) > CPU: frequency set to 2200 MHz > SPD: index 0 (GPIO47=0 GPIO9=0 GPIO13=0) > CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) > CBFS: Locating 'spd.bin' > CBFS: Found @ offset 43f00 size 1000 > SPD: module type is DDR3 > SPD: module part is 99U5469-011.A01LF > SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb > SPD: device width 16 bits, bus width 64 bits > SPD: module size is 4096 MB (per channel) > ME: FW Partition Table : OK > ME: Bringup Loader Failure : NO > ME: Firmware Init Complete : NO > ME: Manufacturing Mode : YES > ME: Boot Options Present : NO > ME: Update In Progress : NO > ME: Current Working State : Initializing > ME: Current Operation State : Bring up > ME: Current Operation Mode : Security Override via Jumper > ME: Error Code : Debug Failure > ME: Progress Phase : BUP Phase > ME: Power Management Event : Pseudo-global reset > ME: Progress Phase State : 0x7b > ERROR: ME failed to respond > FMAP: Found "FLASH" version 1.1 at 300000. > FMAP: base = ffc00000 size = 400000 #areas = 3 > MRC: no data in 'RW_MRC_CACHE' > No MRC cache found. > CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) > CBFS: Locating 'mrc.bin' > CBFS: 'mrc.bin' not found. > Couldn't find mrc.bin > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Haswell port
by Zoran Stojsavljevic 29 Jul '17

29 Jul '17

Dobro Pozalovat6 na Coreboot.. Esli voproci vozniknut/est6, prosto posilaite ssilki. :-) Gde bi mne konec bil kogda/esli bi ja Nemeckij boltal hotja na pol-Russkogo ?! :-(( Udaci! Zoran On Sat, Jul 29, 2017 at 6:57 AM, Konstantin Novikov <theshtabel(a)gmail.com> wrote: > Hello again, coreboot community! > > Thanks a lot Zoran Stojsavljevic and Nico Huber for their help and > answers. You're lead us in "GFX-way", so it was a right direction. > At first, we're added our PCI id in two structures (map_oprom_vendev and > pci_device_ids) in northbridge/intel/haswell/gma.c. But after this we're > see only black screen on display, no any BIOS/Linux output. > gma_setup_panel(dev) - this function was critical for us. > > gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | > DDI_INIT_DISPLAY_DETECTED); > Without DDI_A_4_LANES in this row we saw the Linux Ubuntu output (without > any errors) and logging screen. After trying to use some VGA BIOS we're see > BIOS output and bootsplash too. Linux Ubuntu works correct, fully > reinstalled and loaded. > > Again, thanks Nico and Zoran (от всей души) for help. Coreboot community > are awesome. > > Konstantin Novikov. >

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How can we get MRC.bin for Intel platform.
by Zheng Bao 29 Jul '17

29 Jul '17

Hi, All, I am debugging a i7-5650 board. I use IBV's BIOS to wrap the coreboot, i.e, replace the BIOS Region with coreboot.rom. So I assume the ME blob can work. I wonder if it is the right way. Is it fully supported by Coreboot? How can we get MRC.bin and other blobs? Thanks. Zheng coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage starting... PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 08fe08fc 12400f35 6005e200 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: 0200 2024 4206 Previous Sleep State: S5 CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f CPU: AES supported, TXT supported, VT supported MCH: device id 1604 (rev 09) is Broadwell F0 PCH: device id 9cc3 (rev 03) is Broadwell U Premium IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W) CPU: frequency set to 2200 MHz SPD: index 0 (GPIO47=0 GPIO9=0 GPIO13=0) CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 43f00 size 1000 SPD: module type is DDR3 SPD: module part is 99U5469-011.A01LF SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b ERROR: ME failed to respond FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = ffc00000 size = 400000 #areas = 3 MRC: no data in 'RW_MRC_CACHE' No MRC cache found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'mrc.bin' CBFS: 'mrc.bin' not found. Couldn't find mrc.bin

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coreboot July 2017