coreboot October 2017

coreboot@coreboot.org

66 participants
140 discussions

Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7
by Iru Cai 03 Oct '17

03 Oct '17

Hi all, I found that ACPICA released version 20170929 yesterday, and it's more strict than previous versions. I can't even use it to build qemu-i440fx because many dsdt files have methods that are not used, which will make iasl warn about this. Iru On Tue, Oct 3, 2017 at 11:50 AM, Matt DeVillier <matt.devillier(a)gmail.com> wrote: > hi Paul, > > I took a look at this, and the error appears to be the result of a change > in IASL 20170531: > > "Improved the behavior of the iASL compiler and disassembler to detect > improper use of external declarations" > > According to the ACPI 6.2 spec, "The External directive informs the ASL > compiler that the object is declared external to this table.." This reads > to me that if an object is declared External in one table (eg, the DSDT), > then its declaration must be in another table, not in the table in which > contains the External reference. As _SB.DPTF.TEVT is declared in the DSDT > (in SoC .asl code), then the External declaration in the > chromeec/acpi/ec.asl is invalid. > > To test this, I removed the External declaration in ec.asl, and the > previously failing boards now build properly with iASL 20170831. I also > retested using the current iASL version (20161222), and the aforementioned > boards still build correctly. > > If someone wants to corroborate my analysis, then I'm happy to submit a > patch to correct the issue > > cheers, > Matt > > On Mon, Oct 2, 2017 at 1:56 AM, Paul Menzel <paulepanter@users. > sourceforge.net> wrote: > >> Dear coreboot folks, >> >> >> Am Mittwoch, den 20.09.2017, 08:17 +0200 schrieb Paul Menzel: >> >> > I’d like to propose the following goal for the upcoming coreboot 4.7 >> > release. >> > >> > All boards have to build with GCC 7.2 [1] and IASL 20170831 [2]. >> > >> > For the latter, several Intel boards fail to build [3]. It’d be great >> > if the maintainers looked into it. >> >> Unfortunately, there was no reply yet. Patrick already blocked the >> change-set, and commented that it’ll only go in after the coreboot 4.7 >> release, which is fine. But the boards should still build in my >> opinion. >> >> The boards below are affected by the IASL update. >> >> ``` >> $ git grep TEVT >> src/ec/google/chromeec/acpi/ec.asl:External (\_SB.DPTF.TEVT, MethodObj) >> src/ec/google/chromeec/acpi/ec.asl: If (CondRefOf >> (\_SB.DPTF.TEVT)) { >> src/ec/google/chromeec/acpi/ec.asl: >> \_SB.DPTF.TEVT (Local0) >> src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl:Method >> (TEVT, 1, NotSerialized) >> src/soc/intel/baytrail/acpi/dptf/thermal.asl:Method (TEVT, 1, >> NotSerialized) >> src/soc/intel/braswell/acpi/dptf/thermal.asl:Method (TEVT, 1, >> NotSerialized) >> src/soc/intel/common/acpi/dptf/thermal.asl:Method (TEVT, 1, >> NotSerialized) >> src/soc/intel/skylake/acpi/dptf/thermal.asl:Method (TEVT, 1, >> NotSerialized) >> ``` >> >> What is the process for this? Are the maintainers of the board that >> fail to build subscribed on this mailing list? >> >> >> Kind regards, >> >> Paul >> >> >> > [1] https://review.coreboot.org/20809/ >> > [2] https://review.coreboot.org/21156/ >> > [3] https://ticket.coreboot.org/issues/138 >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > -- Please do not send me Microsoft Office/Apple iWork documents. Send OpenDocument instead! http://fsf.org/campaigns/opendocument/

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Broadwell-DE NS FSP not support
by Hilbert Tu(杜睿哲_Pegatron) 03 Oct '17

03 Oct '17

Hi, I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if Intel FSP not available for my platform? If not, does anyone know how to do that? Please help. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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Re: [coreboot] Suggestions for efficient development setup for Google Chromebooks
by Trammell Hudson 03 Oct '17

03 Oct '17

On Mon, Oct 02, 2017 at 05:02:40PM -0700, Vadim Bendebury wrote: > note that this debug header is going away in new Chrome OS designs. Its > functionality is going to be provided by the closed case debugging (aka > CCD) facility, where authorized user using a special debug cable can gain > access to the AP and EC consoles, reprogram AP and EC firmware, etc. Will the closed chassis debugging require user authorization of some sort and perhaps only be effective in developer mode? One of the major concerns with the Intel SVT adapter is that it claims to work "where USB3-hosted DCI is unavailable", including cold-boot: https://designintools.intel.com/product_p/itpxdpsvt.htm There were talks about it at CCC and HITB: https://conference.hitb.org/hitbsecconf2017ams/materials/D2T4%20-%20Maxim%2… Hopefully the Chromebook CCD doesn't turn into an evil-maid toolkit... -- Trammell

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Re: [coreboot] Suggestions for efficient development setup for Google Chromebooks
by Vadim Bendebury 03 Oct '17

03 Oct '17

note that this debug header is going away in new Chrome OS designs. Its functionality is going to be provided by the closed case debugging (aka CCD) facility, where authorized user using a special debug cable can gain access to the AP and EC consoles, reprogram AP and EC firmware, etc. -vb On Mon, Oct 2, 2017 at 2:57 PM, Julius Werner <jwerner(a)chromium.org> wrote: > The only special thing about Chromebooks is that they have a > standardized debug header, specified here: > https://www.chromium.org/chromium-os/servo > > The header is not populated on consumer devices, but the footprint > should still be there so you can solder it yourself. You can also just > solder to the UART pins directly which are probably the most > interesting ones to you. There are SPI lines on it too and it's even > possible to hook up an EM100 over it, although I'm not 100% sure of > the details for that (I usually find that the ROM itself flashes fast > enough so I don't need an emulator). > > Feel free to ask if you have any questions about how coreboot works on > your Jaq or Elm, happy to help! > > On Sun, Oct 1, 2017 at 11:31 PM, Paul Menzel > <paulepanter(a)users.sourceforge.net> wrote: > > Dear coreboot folks, > > > > > > Do you have any suggestions on how to get an efficient development > > setup for Google Chromebooks, which I’d describe as laptops with > > soldered flash ROM chip. In my case, it’s a Medion AKOYA S2013 > > (google/veyron_jaq), and an Acer Chromebook R 13 (google/elm). > > > > I have access to a BeagleBone Black, a compatible clip and a Dediprog > > EM100-Pro. As the flash ROM chip is not soldered, I guess only the > > first two are of interest, as the chip is soldered and I am unable to > > remove the chip, and solder a socket on it. > > > > I ask, because maybe I miss some unknown “feature” of the Google > > Chromebooks, or there could be an emulator, like AMD SimNow, or > > something similar. > > > > > > Thanks, > > > > Paul > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Suggestions for efficient development setup for Google Chromebooks
by Paul Menzel 02 Oct '17

02 Oct '17

Dear coreboot folks, Do you have any suggestions on how to get an efficient development setup for Google Chromebooks, which I’d describe as laptops with soldered flash ROM chip. In my case, it’s a Medion AKOYA S2013 (google/veyron_jaq), and an Acer Chromebook R 13 (google/elm). I have access to a BeagleBone Black, a compatible clip and a Dediprog EM100-Pro. As the flash ROM chip is not soldered, I guess only the first two are of interest, as the chip is soldered and I am unable to remove the chip, and solder a socket on it. I ask, because maybe I miss some unknown “feature” of the Google Chromebooks, or there could be an emulator, like AMD SimNow, or something similar. Thanks, Paul

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Re: [coreboot] PC Engines apu2 booting broken
by Piotr Król 02 Oct '17

02 Oct '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 On 10/02/2017 03:39 PM, Kyösti Mälkki wrote: Hi Kyösti, > > My fault, see: https://review.coreboot.org/21840 This fix booting issue. Thank you for quick reaction. Added +2 to review hope this not issue. (...) > Once you have bisected to an offending commit, you can do builds > that strips away all the revision hashes: > > abuild --timeless -at pcengines/apu2 diff -qr build-ok/ > build-fail/ > > The list of just the .o files is still a long one, but two further > things you can do here: Strip debug symbols from .o files, and > define ASSERT() without __FILE__ or __LINE__. If you know the > commit was supposed to create a binary identical image, this is one > way to pinpoint where the difference is. > > This approach has saved the day before when AGESA includes have > gone crazy. Sounds like great approach. Any easy way to strip debug and redefine ASSERT in coreboot ? Or you just doing it manually ? Would be great to note exact steps in case anyone would need that in future. Maybe even script. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE0Fuj+LRuV2IlvAeVmPZBsjmwRrQFAlnSqzQACgkQmPZBsjmw RrRCnw/+LHM8ZVfefHII4euhk/+espqEcoMGv4BeS82r+xB/yTumVxCz7uIptLca bizl9v++B3cX92S22LGyIGaH7xjQIhJd3tYqn6DgWJ+9278jcjliDBxpH1b2cYjx w50abEvK5ssD7laRPj21DnnldDKHSaZ/AnM3le7MXIyBeFgRLp0Fqlvotou08l4H OfXl2c+eGmwdGMRjrVOMHqWz+CAQv17wXNyKYYwxAD0sTAYD6Xj8A0rSKgWTnxWd ORANofU/Cx/lK/oBhWotPhT0n0Wp6vgQ4k84r1KHuadJyB6lO/2hgS7fk48rV3Y7 yIqAKPd4tKj33rFtjXGVyG2RHvsTXP90GRE4bjDvi5JVTCUnABF7jQ1ORJHEe7SM qDGZx1o3g3BifXK/34SgsuPkGDJwQy/xNQFhK4P7KLji9OkRk8btpsOxBXx7MWmu 3oVfcZManM6payPpW52JUzJz5N2iUf+WjbPlZS6oOkYpnHdo5y2gZdOOf5PfIbCQ KYGyb8qjNFeeOez1mpFUufnFDumDY9Dbf1CDC//rSUSYEIacsf/6PLQJxifkm+xD mL2FTMNOf13yu0gjqO5zh2UiojpgvoA3vUO7fJ6/WMO6HFE0AGwCP4P7ASGUZ6qm PW5n2nunC3vsGtKhcPsIb0l4VTUNm6UVRxINBUC2x37DpGLlUIk= =owYc -----END PGP SIGNATURE-----

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Re: [coreboot] Owner-controlled POWER9 Talos II [was: Disabling Intel ME 11 via undocumented mode]
by Timothy Pearson 02 Oct '17

02 Oct '17

On 09/06/2017 01:05 PM, Rene Shuster wrote: > Thanks for sharing this info. > > So the 4x SATA ports are optional and powered by PM8069, and they will > only be present if you checkbox the "Integrated Microsemi SAS Controller > (Proprietary)" on the purchase page, correct? Or in other words: if you > don't checkbox "Integrated Microsemi SAS Controller (Proprietary)" you > will receive a board with no SATA ports? Correct. Given the advantages of NVMe especially for a high-power development system like the Talos™ II this was considered an acceptable tradeoff. > How is the Samsung NVMe drive physically connected (M.2/U.2 or PCIe > slot)? What model# is it? PCIe. We'll be selecting an active model closer to machine ship; Samsung part numbers can change over time so we don't necessarily want to commit to a given part # at this point. > So BCM it is. They have a pretty thorough Diagnostic for their NICs. I'm > using it on some of our servers when it's time to run diagnostics. It's > DOS based (but they have an UEFI version as well) and it does check > quite a few things ("Register Tests, Memory Tests, Miscellaneous Tests, > Data Tests, Cable Tests, APE Register Tests and APE Diagnostics > Tests"). For the BCM5719 the diag is located here: > https://docs.broadcom.com/docs-and-downloads/docs/eula_download/570x/B57udi… > It includes the B57Diag.pdf which might be of interest for anyone who > wants to reverse engineer the fw. Sounds good. This is the only device on the board that requires firmware, but it is behind the IOMMU and the FSF has indicated that we can still obtain RYF with this limitation. That being said, we'd love to see a libre firmware created for this controller as it would allow not only this system, but future systems, to be blob-free while using a modern non-Intel GbE NIC... -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com

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PC Engines apu2 booting broken
by Piotr Król 02 Oct '17

02 Oct '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 Hi all, PC Engines apu2 (and probably apu1) not booting on recent master. I bisected problem to: d4955f0ade18cafde4a3ea20885eb9fbdc5b4514 AGESA: Move API interface under drivers/ I'm not sure if some config options are missing. I tried to select DRIVERS_AMD_PI and CPU_AMD_PI in Kconfig, but those not help. Platform behave like it would not proceed with booting - no serial output, Ethernet led on and blinks after regular cycles (reset ?). Previous commit works fine. Any idea what I'm missing ? Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE0Fuj+LRuV2IlvAeVmPZBsjmwRrQFAlnRIdgACgkQmPZBsjmw RrQ1phAAy994/PLg1AbUOoPzOvpN/1GT4rFLojaCG38AwevJRfPac8MBtfLUBrWN Vprm8D4jXLideyphHPeY6pjWFoT4BddvySsztEWAao1K3kWHyB/Qc1EvoAxtEfXJ l4HP1FWjLFunDaXbiCp6gpJ0m0VhMewDDFcR6UudY/5CEPPmhJ/XpCVlsg0D/3vG MjR9/pFz9PmHmTPANfa6+BlvYta53uYo0535CVQGSQCD5o7Q64EE4+MJA0tZDZDj VpTUUxRrMXOC6/ci9CF1XBDNpo+IUKW25Kdw+EbCYlhh91BHVlmfDDrJqkorAVpR GyKCarXbsD2G99hJGnCQVYouu7fsc6mO8BvoW/5Ioe+DtDXsn2rGphDbD5Wz/n39 7p8J7nmACQFTtu+VdyikjScLaV1F2O5Z9EBri49aCuSApBz/Ek4kq+xPF6JeJxxu ItQnm2YCIOhmJFUxgwVKC8fYbTdXzQzqPIOzPSXOu3SWfCazrDJygE5kd3GWA4fl 2ux8YLg/eCLcKy3J8Sm2ykthjED+ALG25Hu0W5+7+L1fmBG7Z5RpObziwgF5/Jj/ NrUdvDW7klvqrIitKaqAvwEc3T2YUDBVSf1gSbCW4FL+9xUc5eTtRiHmv1Zgfxg8 WB8OqELVi2oebV/jK79DqrC1svnlCaLTDKBL4mNo2FlqmAk4iv4= =wPuF -----END PGP SIGNATURE-----

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Re: [coreboot] Intel Leaf Hill Coreboot Trouble
by Cameron Craig 02 Oct '17

02 Oct '17

Hi Paul, Those changes to the IFWI blob worked great, thanks! I have attached the serial console log. It looks like we are in similar situations now. I got a hang of around 45s at “MRC: region file invalid in 'RW_VAR_MRC_CACHE”, and then it hangs indefinitely at the end of the log. I tracked the MRC cache message down to this line: https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/mrc_c… I’m stuck again for the moment. Thanks again Paul for getting me one step closer. Cheers, Cameron Cameron Craig | Graduate Software Engineer | Exterity Limited tel: +44 1383 828 250 | fax: e: Cameron.Craig(a)exterity.com | w: www.exterity.com From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Cameron Craig Sent: 28 September 2017 16:51 To: 'Paul Penz'; coreboot(a)coreboot.org Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble Hi Paul, Great to hear I’m not the only one in this situation ☺ I’ve just been using the IWFI file from Intel with no modifications, so I’ll look out the FIT tool and give that a go. Thanks, Cameron Cameron Craig | Graduate Software Engineer | Exterity Limited tel: +44 1383 828 250 | fax: e: Cameron.Craig(a)exterity.com<mailto:Cameron.Craig@exterity.com> | w: www.exterity.com<http://www.exterity.com> From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Paul Penz Sent: 28 September 2017 15:35 To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble Hi Cameron, I had the same problem. Had you modified the intel IFWI file ? If not, I had done this additional: Download 522538_apl txe hf 3.0.11.1131 (th2 & rs1).zip from intel Start fit.exe Load the IFWI file Change at Platform Protection/Platform Integrity OOEM Public Key Hash => 00..00 Change at Platform Protection/Boot Guard Configuration/ Boot profile 2 => 0 Save Now I get output on the console and postcodes, but during FSP_M a long pause of ca. 45s exists and it hangs later during FSP_P initialization. Good luck Paul Paul Penz Dipl.-Ing. (FH) Senior Hardware Engineer ELTEC Elektronik AG, Mainz _________________________ Fon +49 6131 918 335 Fax +49 6131 918 195 Email ppenz(a)eltec.de<mailto:ppenz@eltec.de> Web www.eltec.de<http://www.eltec.de/> ________________________________ ********************************************************* ELTEC Elektronik AG Galileo-Galilei-Straße 11 D-55129 Mainz Vorstand: Peter Albert Aufsichtsratsvorsitzender: Andreas Kochhäuser Registergericht: Amtsgericht Mainz Registernummer: HRB 7038 Ust-ID: DE 149 049 790 ********************************************************* Wichtiger Hinweis: Diese E-Mail kann Betriebs- oder Geschäftsgeheimnisse oder sonstige vertrauliche Informationen enthalten. Sollten Sie diese E-Mail irrtümlich erhalten haben, ist Ihnen eine Kenntnisnahme des Inhalts, eine Vervielfältigung oder Weitergabe der E-Mail ausdrücklich untersagt. Bitte benachrichtigen Sie uns und vernichten Sie die empfangene E-Mail. Evtl. Anhänge dieser Nachricht wurden auf Viren überprüft! Jede Form von Vervielfältigung, Abänderung, Verbreitung oder Veröffentlichung dieser E-Mail Nachricht ist untersagt! Das Verwenden von Informationen aus dieser Nachricht für irgendwelche Zwecke ist strengstens untersagt. Es gelten unsere Allgemeinen Geschäftsbedingungen, zu finden unter www.eltec.de<http://www.eltec.de>. ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________

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Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?
by Piotr Król 02 Oct '17

02 Oct '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 On 09/21/2017 04:52 PM, Kyösti Mälkki wrote: Hi Kyösti, > > I can help you to get these to EARLY_CBMEM_INIT. That's the first > obstacle with Geode. It's recommended that coreboot would store > the timebase / TSC information so that cpufreq support is not > needed in kernel. I have some on-going work on AMD timestamps > anyways. Please let me know what I can do to help you implement that. We have all hardware at hand and would be glad to fix that till ECC2017 if possible. I also would like to work on upstreaming other alix and apu platform, but first want to clean things with cbmem. BTW will you attend ? It would be great to meet you. (...) > > Do you mean supported boards table, and the 3rd column from left > for ALIX 2C or ALIX 6 has invalid links? That would not be your > fault. When alix.2d was pushed to board_status, it also refreshes > .2c and .6 entries even when they don't exist as individual updates > on the wiki. Yes, this is what I meant. We get access to wiki and fixed that issue. Now correct logs were uploaded to supported boards site. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE0Fuj+LRuV2IlvAeVmPZBsjmwRrQFAlnRdE4ACgkQmPZBsjmw RrRsdw/8Ckke8GJ70BxY8WVjAHZDx6lDdXiSviCGnobJoD6+JQ80nEt4wRou+IX5 iRah1ETmpfVRAfWot5pNzjIksPpDlTZ8QKNyfQp+mXtM3mYtl8lDW/4nl+fr1dR2 ImWBW9vw8y3vytlNa7LEdUS0YSf5uxwFyuUUjEfjfAiNrB9KK8FtgIVkMaUeIs7m toyaPbSiS+RASY53kr1OM/eg4CTqQgWnz70MvNH7Y+JdtI4KaavnAWMZZmyxO8Kz GMNkLD310fgHy2vn5AN+qW8s26TmPz0E0iKQZQvfB4lKelFkL0+4yOfe3usY6MDD CBiIAsheL69cOZ9BcPPe01nUHIGygTwf1x87BERBbGatSVyHSyqSoQOnuEr2s70u AbY7d4ePBsPVKI9keXj9y9y3LTyQXI2a3JE1R3BrU2uXkAiajlhunlkr8tWUpA6D SOG5Cj0yP+XgFt1jJBZroESfoardVOOfCFZz+Kc8Eg9qHiG7ECLKKc9SD+FDnBUb winJoNMBemxY+DC5eaoWt2YVqJ9lNK9aD2oWGq7fnfRrLC6vhChRwHqcKZUAlXMv g8dOoND0Zq7hdyloOjqdv/5ZjpuA6sJBzlwxIuRBrxfKQ0B2wgLfFfYWdcTC18vI HRBkmpJC1hSSWg8GWKP4mTtCT3LC2k5UmjqwYvkhmIVho8H500E= =WmYc -----END PGP SIGNATURE-----

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coreboot October 2017