coreboot October 2017

coreboot@coreboot.org

66 participants
140 discussions

Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure
by Anshuman Aggarwal 05 Oct '17

05 Oct '17

@Taiidan, as much as I love all things libre, my budget doesn't come close to buying those motherboards :(. I like the idea of using another machine to view the grub serial. Maybe using a Raspberry Pi etc. @ron, I assume you mean a livecd like alternative which I can connect to and use to debug the issue? The only problem I see with that is that I cannot see the issue with the machine as it boots so in the off chance that something in the distro is corrupted I won't be able to figure it out with interacting with a live boot session. Out of curiosity, is this a limitation to what is possible in the BIOS or that nobody has found the need to do this sort of remote control using the BIOS yet? On 4 October 2017 at 20:59, ron minnich <rminnich(a)gmail.com> wrote: > as always, your other other choice is to use linux in flash as a bootstrap, > and then have the full spectrum of x-over-network solutions that you get > from that. That's my new (old) approach nowadays. > >

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Re: [coreboot] Broadwell-DE NS FSP not support
by Hilbert Tu(杜睿哲_Pegatron) 05 Oct '17

05 Oct '17

Hi Zoran, Thanks for your suggestion. I’ll try. -Hilbert From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: Thursday, October 05, 2017 11:27 AM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Broadwell-DE NS FSP not support Hello Hilbert, You might want to log in case in IPS (INTEL Premier Support) and ask there for INTEL IoT support to help you. https://supporttickets.intel.com/?lang=en-US My best bet, your best path to solution. Zoran On Thu, Oct 5, 2017 at 3:40 AM, Hilbert Tu(杜睿哲_Pegatron) <Hilbert_Tu(a)pegatroncorp.com<mailto:Hilbert_Tu@pegatroncorp.com>> wrote: Hi Zoran/Piotr, Yes, the current available FSP does not support BDX-DE NS. I got same information from local Intel FAE. So I don’t know the next step to evaluate my CRB. @Taiidan, Thanks for your information, “6 months for skilled person” ☺ Maybe I should try BIOS/UEFI first. -Hilbert From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com<mailto:zoran.stojsavljevic@gmail.com>] Sent: Wednesday, October 04, 2017 7:57 PM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Broadwell-DE NS FSP not support Hello Hilbert, There is none FSP for BDW-DE? Are you sure?? And how did you conclude that??? Here is the answer: https://github.com/IntelFsp/FSP Intel® Xeon® Processor D Product Family (formerly Broadwell-DE, Compliant with FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> git clone -b Broadwell-DE <https://github.com/IntelFsp/FSP.git> https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> Zoran _______ On Tue, Oct 3, 2017 at 4:39 AM, Hilbert Tu(杜睿哲_Pegatron) <Hilbert_Tu(a)pegatroncorp.com<mailto:Hilbert_Tu@pegatroncorp.com>> wrote: Hi, I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if Intel FSP not available for my platform? If not, does anyone know how to do that? Please help. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Broadwell-DE NS FSP not support
by Zoran Stojsavljevic 05 Oct '17

05 Oct '17

Hello Hilbert, You might want to log in case in IPS (INTEL Premier Support) and ask there for INTEL IoT support to help you. https://supporttickets.intel.com/?lang=en-US My best bet, your best path to solution. Zoran On Thu, Oct 5, 2017 at 3:40 AM, Hilbert Tu(杜睿哲_Pegatron) < Hilbert_Tu(a)pegatroncorp.com> wrote: > Hi Zoran/Piotr, > > > > Yes, the current available FSP does not support BDX-DE NS. I got same > information from local Intel FAE. So I don’t know the next step to > evaluate my CRB. > > > > @Taiidan, > > Thanks for your information, “6 months for skilled person” J Maybe I > should try BIOS/UEFI first. > > > > -Hilbert > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* Wednesday, October 04, 2017 7:57 PM > *To:* Hilbert Tu(杜睿哲_Pegatron) > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] Broadwell-DE NS FSP not support > > > > Hello Hilbert, > > > > There is none FSP for BDW-DE? Are you sure?? And how did you conclude > that??? > > > > Here is the answer: https://github.com/IntelFsp/FSP > > > > Intel® Xeon® Processor D Product Family (formerly Broadwell-DE, Compliant > with FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE > https://github.com/IntelFsp/FSP.git > > > <https://github.com/IntelFsp/FSP.git> > > git clone -b Broadwell-DE <https://github.com/IntelFsp/FSP.git> > https://github.com/IntelFsp/FSP.git > > > <https://github.com/IntelFsp/FSP.git> > > Zoran > > _______ > > > > On Tue, Oct 3, 2017 at 4:39 AM, Hilbert Tu(杜睿哲_Pegatron) < > Hilbert_Tu(a)pegatroncorp.com> wrote: > > Hi, > > I have an Intel Broadwell-DE NS CRB and I want to evaluate it with > coreboot. But from Intel FSP git, there is no corresponding FSP for > Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if > Intel FSP not available for my platform? If not, does anyone know how to do > that? Please help. Thanks. > > -Hilbert > > This e-mail and its attachment may contain information that is > confidential or privileged, and are solely for the use of the individual to > whom this e-mail is addressed. If you are not the intended recipient or > have received it accidentally, please immediately notify the sender by > reply e-mail and destroy all copies of this email and its attachment. > Please be advised that any unauthorized use, disclosure, distribution or > copying of this email or its attachment is strictly prohibited. > 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件， > 請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > > >

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Re: [coreboot] Broadwell-DE NS FSP not support
by Hilbert Tu(杜睿哲_Pegatron) 05 Oct '17

05 Oct '17

Hi Zoran/Piotr, Yes, the current available FSP does not support BDX-DE NS. I got same information from local Intel FAE. So I don’t know the next step to evaluate my CRB. @Taiidan, Thanks for your information, “6 months for skilled person” ☺ Maybe I should try BIOS/UEFI first. -Hilbert From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: Wednesday, October 04, 2017 7:57 PM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Broadwell-DE NS FSP not support Hello Hilbert, There is none FSP for BDW-DE? Are you sure?? And how did you conclude that??? Here is the answer: https://github.com/IntelFsp/FSP Intel® Xeon® Processor D Product Family (formerly Broadwell-DE, Compliant with FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> git clone -b Broadwell-DE <https://github.com/IntelFsp/FSP.git> https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> Zoran _______ On Tue, Oct 3, 2017 at 4:39 AM, Hilbert Tu(杜睿哲_Pegatron) <Hilbert_Tu(a)pegatroncorp.com<mailto:Hilbert_Tu@pegatroncorp.com>> wrote: Hi, I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if Intel FSP not available for my platform? If not, does anyone know how to do that? Please help. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure
by Taiidan＠gmx.com 04 Oct '17

04 Oct '17

On 10/03/2017 07:27 AM, Anshuman Aggarwal wrote: > Hi, > If a coreboot compatible motherboard is used and the right > coreboot+plugins flashed, is there a way that can be used to view the > linux terminal console during boot time in order to remotely > debug/troubleshoot any grub level bootup issues (before the SSH or any > other such daemon can load)? > > All the solutions I see so far seem to be proprietary to Intel and > require Server motherboards. > > Since coreboot has a network debug log sending option, it stands to > reason that it could theoretically connecting a terminal console over > a compatible ethernet card? > > Thoughts anyone? Apologies if this has been asked but mailman does not > make it easy to search archives. > > Regards > Anshuman > I would get a KGPE-D16 or KCMA-D8, install raptor's OpenBMC port and use grub's serial output connected to the BMC's serial port - all entirely libre. Your other choice is using another computer to view the grub serial output if you don't want to use the two above boards (although I recommenced getting one as they are the best last owner controlled x86 motherboards)

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What’s the release plan for coreboot 4.7?
by Paul Menzel 04 Oct '17

04 Oct '17

Dear coreboot folks, It’s October and coreboot 4.7 is supposed to be tagged in this month. Are there more specific plans already, when the release will happen? Thanks, Paul

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Re: [coreboot] Broadwell-DE NS FSP not support
by Piotr Król 04 Oct '17

04 Oct '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 On 10/04/2017 01:56 PM, Zoran Stojsavljevic wrote: > Hello Hilbert, Hi Zoran, > > There is none FSP for BDW-DE? Are you sure?? And how did you > conclude that??? He meant DE NS, not pure DE - this is different SKU IIUC. From my knowledge Intel has separate BWG and other specific documents for that, so I assume FSP also may be different. @Hilbert, did you tried DE FSP, is there anything what not work as you want ? Best Regards, - -- Piotr Król Embedded Systems Consultant http://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlnU1IEACgkQsu5x6Weq nkyFlA//XYrMD7E1bBa+OqECrodLhzeb2FpdXxk3YDhXqDBOBXdLNZNvuNobAYHj aN0zf9xqNc7PQFVt5/f3tg/ygE+RCbCirC7M1jYpREH91vHJ4EVS1bmzEUbNs3A0 8up6v26iTw6ZYmcO+Aq1tJa2Ir7ToMv9qlEPrctpaktrME48oAz9HLd9+6+i9w18 BP9A1JCE/NgM0ADEcI7ITsXlHry2BI8LEP5iiUbth6Jz3noT+30yIvhtZdZmALTw pBC/IkH36fObCJ3nGJEgt79KFPpnVsWwIAalwaBKNrh7zulhMoaGTQzzG/dQRCRM MY9EGSBvl1xKcW0cFuuWbOqQ6QJ5TO3VSw2IBm4L8VLk9Qg6KdbV3+mb2Oo8AlGJ OX8iKj6PWcVjzKG/8rml+7zyhDyhaG9pBxqnJid0DnK8ryP8I2Wh+MGaLKwUgq0w WoltWzLcOso0LubJzAF8n3wyyXnFX9YUiBE5QreR9ZqNYsSmWQr4mh1qJf2AN/vV cCbhguChIRPbi4yOllouA4xmwLVwS0cpauIUAFZEfpSrGvUyfM/8GQUXRCUGuvVf keFN1h6qJZ8x5ubdOBzLYTJdemyFaILGt7gvNZPQV1bkUKC0/TxBmb2pN1GiqHpF B672FtY8EtY+njqAHcK9jWf8psofLN+KFhgrwZk+L2dZTFNQbdg= =ulWW -----END PGP SIGNATURE-----

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Re: [coreboot] Broadwell-DE NS FSP not support
by Zoran Stojsavljevic 04 Oct '17

04 Oct '17

Hello Hilbert, There is none FSP for BDW-DE? Are you sure?? And how did you conclude that??? Here is the answer: https://github.com/IntelFsp/FSP Intel® Xeon® Processor D Product Family (formerly Broadwell-DE, Compliant with FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> git clone -b Broadwell-DE <https://github.com/IntelFsp/FSP.git> https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> Zoran _______ On Tue, Oct 3, 2017 at 4:39 AM, Hilbert Tu(杜睿哲_Pegatron) < Hilbert_Tu(a)pegatroncorp.com> wrote: > Hi, > > I have an Intel Broadwell-DE NS CRB and I want to evaluate it with > coreboot. But from Intel FSP git, there is no corresponding FSP for > Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if > Intel FSP not available for my platform? If not, does anyone know how to do > that? Please help. Thanks. > > -Hilbert > This e-mail and its attachment may contain information that is > confidential or privileged, and are solely for the use of the individual to > whom this e-mail is addressed. If you are not the intended recipient or > have received it accidentally, please immediately notify the sender by > reply e-mail and destroy all copies of this email and its attachment. > Please be advised that any unauthorized use, disclosure, distribution or > copying of this email or its attachment is strictly prohibited. > 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件， > 請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Broadwell-DE NS FSP not support
by Taiidan＠gmx.com 04 Oct '17

04 Oct '17

On 10/02/2017 10:39 PM, Hilbert Tu(杜睿哲_Pegatron) wrote: > Hi, > I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if Intel FSP not available for my platform? If not, does anyone know how to do that? Please help. Thanks. > -Hilbert You would have to create init code (northbridge, southbridge, superio, cpu etc) for that platform if a FSP blob isn't available, this is how it was done before intel started releasing the FSP binary blobs - it is much more work to do this (probably 6 months for one skilled person if you can obtain enough documentation) but you would have more flexibility as the result would be open source. The most recent intel platform with open source coreboot init code is ivy bridge, so many generations behind unfortunately.

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Re: [coreboot] Intel Leaf Hill Coreboot Trouble
by Paul Penz 04 Oct '17

04 Oct '17

Hi Cameron, I don’t think that the „boot performance“ is our issues. I understand section 3.5.4 that it would be very slow, but does not hang. My console log is very similar to yours, but I have additional a post code logger and see after the 0x93 some postcodes from the FSP: 34 92 00 02 7F 10 00 50 7F 30s pause (FSP_M) 00 2F 98 13 79 39 80 70 71 93 FSP_S: 00 0F 31 36 61 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 7F 30 31 36 0E 12 37 I opened an intel support case and hope they could help. Regards, Paul Von: Cameron Craig [mailto:Cameron.Craig@exterity.com] Gesendet: Dienstag, 3. Oktober 2017 17:52 An: Paul Penz; 'coreboot(a)coreboot.org' Betreff: RE: Re: [coreboot] Intel Leaf Hill Coreboot Trouble Hi all, I have enabled post codes and all the debug config options in coreboot that looked useful. As Paul has already done, I have narrowed down the latest issue to the FspSiliconInit() stage (FSP-S). The 0x93 post code is the last message I get on the serial console, and signifies that FspSiliconInit() has started but not completed. See (https://github.com/coreboot/coreboot/blob/master/src/include/console/post_c…). I have attached the full serial log. I can’t see how the actual FSP blob could be at fault here. I don’t know if this is of help, but I came across this document: https://github.com/IntelFsp/FSP/raw/ApolloLake/ApolloLakeFspBinPkg/Docs/Apo… Specifically section 3.5.4: “It is expected that boot loader will program MTRRs for SBSP as needed after TempRamExit but before entering FspSiliconInit. If MTRRs are not programmed properly, the boot performance might be impacted.” This “boot performance” may be part of the issue? Any thoughts would be appreciated, this mailing list has been helpful so far! Cheers, Cameron Cameron Craig | Graduate Software Engineer | Exterity Limited tel: +44 1383 828 250 | fax: e: Cameron.Craig(a)exterity.com<mailto:Cameron.Craig@exterity.com> | w: www.exterity.com<http://www.exterity.com> From: Cameron Craig Sent: 02 October 2017 11:19 To: Cameron Craig; 'Paul Penz'; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: Re: [coreboot] Intel Leaf Hill Coreboot Trouble Hi Paul, Those changes to the IFWI blob worked great, thanks! I have attached the serial console log. It looks like we are in similar situations now. I got a hang of around 45s at “MRC: region file invalid in 'RW_VAR_MRC_CACHE”, and then it hangs indefinitely at the end of the log. I tracked the MRC cache message down to this line: https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/mrc_c… I’m stuck again for the moment. Thanks again Paul for getting me one step closer. Cheers, Cameron From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Cameron Craig Sent: 28 September 2017 16:51 To: 'Paul Penz'; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble Hi Paul, Great to hear I’m not the only one in this situation ☺ I’ve just been using the IWFI file from Intel with no modifications, so I’ll look out the FIT tool and give that a go. Thanks, Cameron Cameron Craig | Graduate Software Engineer | Exterity Limited tel: +44 1383 828 250 | fax: e: Cameron.Craig(a)exterity.com<mailto:Cameron.Craig@exterity.com> | w: www.exterity.com<http://www.exterity.com> From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Paul Penz Sent: 28 September 2017 15:35 To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble Hi Cameron, I had the same problem. Had you modified the intel IFWI file ? If not, I had done this additional: Download 522538_apl txe hf 3.0.11.1131 (th2 & rs1).zip from intel Start fit.exe Load the IFWI file Change at Platform Protection/Platform Integrity OOEM Public Key Hash => 00..00 Change at Platform Protection/Boot Guard Configuration/ Boot profile 2 => 0 Save Now I get output on the console and postcodes, but during FSP_M a long pause of ca. 45s exists and it hangs later during FSP_P initialization. Good luck Paul Paul Penz Dipl.-Ing. (FH) Senior Hardware Engineer ELTEC Elektronik AG, Mainz _________________________ Fon +49 6131 918 335 Fax +49 6131 918 195 Email ppenz(a)eltec.de<mailto:ppenz@eltec.de> Web www.eltec.de<http://www.eltec.de/> ________________________________ ********************************************************* ELTEC Elektronik AG Galileo-Galilei-Straße 11 D-55129 Mainz Vorstand: Peter Albert Aufsichtsratsvorsitzender: Andreas Kochhäuser Registergericht: Amtsgericht Mainz Registernummer: HRB 7038 Ust-ID: DE 149 049 790 ********************************************************* Wichtiger Hinweis: Diese E-Mail kann Betriebs- oder Geschäftsgeheimnisse oder sonstige vertrauliche Informationen enthalten. Sollten Sie diese E-Mail irrtümlich erhalten haben, ist Ihnen eine Kenntnisnahme des Inhalts, eine Vervielfältigung oder Weitergabe der E-Mail ausdrücklich untersagt. Bitte benachrichtigen Sie uns und vernichten Sie die empfangene E-Mail. Evtl. Anhänge dieser Nachricht wurden auf Viren überprüft! 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coreboot October 2017