coreboot October 2017

coreboot@coreboot.org

66 participants
140 discussions

Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure
by Peter Stuge 06 Oct '17

06 Oct '17

Anshuman Aggarwal wrote: > Out of curiosity, is this a limitation to what is possible in the BIOS > or that nobody has found the need to do this sort of remote control > using the BIOS yet? There are a few things that you would need to consider. For legacy compatibility you require a VGA BIOS with a network backend. For a better solution, do what Ron suggested and put Linux in flash. For the legacy solution, there exists a VGA BIOS with a serial port backend called SGABIOS, which you could build upon. SGABIOS is open source. You would have to develop packet drivers for the network adapters which you want to work. You also need an IP stack. And you would have to make it all work in a BIOS environment, without any OS. It is doable, but it is no small task. //Peter

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Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure
by Anshuman Aggarwal 06 Oct '17

06 Oct '17

Ron, Do you have any link to point me towards developing this solution. I get at a high level what you are suggesting but would like to reuse whatever work has already been done towards this. If the technique is widely used, what do I google or look around for? Thanks On 5 October 2017 at 19:40, ron minnich <rminnich(a)gmail.com> wrote: > > > On Thu, Oct 5, 2017 at 2:55 AM Anshuman Aggarwal > <anshuman.aggarwal(a)gmail.com> wrote: >> >> >> >> @ron, I assume you mean a livecd like alternative which I can connect >> to and use to debug the issue? > > > no, I mean putting the kernel in firmware and using the network as the > equivalent of a serial port. It's a widely used technique since around 2000. > >

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Re: [coreboot] AGESA fam15 code removals
by Taiidan＠gmx.com 05 Oct '17

05 Oct '17

I have an H8SCM, but have never successfully booted it with coreboot due to being lazy. I have a test clip and would be willing to test any changes.

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Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
by Nico Huber 05 Oct '17

05 Oct '17

Hi 799, On 29.09.2017 13:34, One7two99 wrote: > Hello Nico, > >> I suspect some misconfiguration or that something confuses the libpay- >> load VGA driver (which these two secondary payload rely on). > > This might be true, but I don't understand why I can see the SeaBios > Menu (Press ESC) and can also use graphical boot (Windows and Qubes OS) > but the secondary payloads don't work. Can you check my .config > especially the setting for the VGA device? you might have to accept that adding VGA compatibility for Windows may break compatibility with the secondary payloads. That's not generally the case but about the last thing that gets tested. If you don't get this setup with SeaBIOS running, there are alterna- tives. One that comes to mind: Do native GFX init in coreboot, add the VGA blob (so far your config below) but use GRUB as primary payload and run SeaBIOS as secondary. You'd have to hand-craft your grub.cfg, some- thing like four choices: 1. Run your favorite open source OS 2. SeaBIOS for legacy compatibility 3. coreinfo 4. nvramcui > >>> If you thing I"ve missed out important steps, I am happy to hear your comments. >> Don"t think you missed anything [...] But you might do too much already. >> Especially flashing anything but the BIOS region when you want to track >> down coreboot issues makes things harder to reason about. > > I had the seconday payloads booting when lynxis did the coreboot > flashing. But we flashed without adding a vga-rom so that I couldn't > boot into windows. I've extracted the vga rom and then tried to rebuild > coreboot, but I seem to miss some configuration to get graphical boot > (vga rom) and secondary payload boot running. > > I've seen the following option in make nconfig for coreboot under > "General Setup": │ [*] Include the coreboot .config file into the ROM > image │ > > QUESTION: How can I extract this .config file? I could then extract this > from my first flashing together with lynxis to see which settings have > been applied there. You can do that with cbfstool, e.g. $ build/cbfstool build/coreboot.rom extract -n config -f config.txt where your replace `build/coreboot.rom` with the path of your image and `config.txt` with the path to the output file. Another question about your setup, do you configure anything in SeaBIOS that is not visible from your coreboot .config? Anything GFX related? splashscreen? VESA mode? Nico (Some comments on your config below.) > >> Please attach your .config file. Nobody can say anything for sure >> with-out knowing what you chose. > > I've attached the config file and will also list the activated options here: > (only enabled options are shown): > > [General Setup] > │ [*] Use CMOS for configuration values > │ [*] Compress ramstage with LZMA > │ [*] Include the coreboot .config file into the ROM image > │ [*] Create a table of timestamps collected during boot > │ -*- Build the ramstage to be relocatable in 32-bit address space > > [Mainboard] > │ Mainboard vendor (Lenovo) > │ Mainboard model (ThinkPad X230) > │ ROM chip size (12288 KB (12 MB)) > │ (0x400000) Size of CBFS filesystem in ROM > > [Chipset] > │ *** CPU *** > │ [*] Enable VMX for virtualization > │ [*] Set lock bit after configuring VMX > │ Include CPU microcode in CBFS (Generate from tree) > │ *** Northbridge *** > │ -*- Use native raminit > │ *** Southbridge *** > │ Flash locking during chipset lockdown (Don't lock flash sections) > │ [*] Lock down chipset in coreboot > │ *** Embedded Controllers *** > │ [*] Beep on fatal error > │ [*] Flash LEDs on fatal error > │ *** Intel Firmware *** > │ [*] Add Intel descriptor.bin file > │ (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin) > │ [*] Add Intel ME/TXE firmware > │ (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin) > │ [*] Verify the integrity of the supplied ME/TXE firmware > │ [*] Add gigabit ethernet firmware > │ (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin) > │ [*] Lock ME/TXE section > │ Verified Boot (vboot) > │ Bootblock behaviour (Always load fallback) > > [Devices] > │ Graphics initialization (Use native graphics init) With this option you let coreboot initialize GFX. But you also let Sea- BIOS run the VGA BIOS. The former will be completely overrun. I doubt that it causes your secondary payload trouble, though. > | --> Framebuffer mode (Legacy VGA text mode) > │ Display > │ -*- Enable PCIe Common Clock │ > │ -*- Enable PCIe ASPM > [*] Add a VGA BIOS image > │ (./3rdparty/blobs/mainboard/lenovo/x230/pci8086,0166.rom) VGA BIOS > │ (8086,0166) VGA device PCI IDs > > [Generic Drivers] > │ [*] Serial port on SuperIO WTF? > │ [*] Support Intel PCI-e WiFi adapters > │ [*] PS/2 keyboard init Is this required? It's odd to set it when using SeaBIOS. > │ [*] Enable TPM support > > [Console] > │ [*] Squelch AP CPUs from early console. > │ [*] Send console output to a CBMEM buffer > │ (0x20000) Room allocated for console output in CBMEM > │ [*] Send POST codes to an external device > │ Device to send POST codes to (None) > │ [*] Send POST codes to an IO port > │ (0x80) IO port for POST codes > > [System tables] > │ [*] Generate SMBIOS tables > > [Payload] > │ Add a payload (SeaBIOS) ---> │ > │ SeaBIOS version (1.10.2) ---> │ > │ (0) PS/2 keyboard controller initialization timeout (milliseconds) │ Why override the default? If it works that's just fine. I'm just wondering if we should have different defaults then. > │ [*] Hardware init during option ROM execution │ > │ () SeaBIOS config file │ > │ () SeaBIOS bootorder file │ > │ (-1) SeaBIOS debug level (verbosity) │ > │ *** Using default SeaBIOS log level *** │ > │ [*] Use LZMA compression for payloads │ > │ Secondary Payloads ---> > │ [*] Load coreinfo as a secondary payload > │ [*] Load nvramcui as a secondary payload > > [Debugging] > all deactivated > > kind regards > > [788] huh?

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Re: [coreboot] AGESA fam15 code removals
by Martin Roth 05 Oct '17

05 Oct '17

I've got a supermicro H8SCM board, although I don't think I've ever tried to boot it, so I don't know its state. I also suspect that it's got a family 10h processor, not a fam15. I can try to get it set up this weekend, and I can bring it to the conference with me if that would help. Here's the list of boards I've got for future reference: https://www.coreboot.org/User:MartinRoth#Platforms_supported_by_coreboot I've got very mixed feelings about pushing the changes that we know aren't going to work, especially right before we abandon the boards to a branch. The idea is that the branch should be in a working state, though as mentioned, we have no idea if these boards are currently working. On the other hand, I don't want to get in the way of the progress on the AGESA changes. I guess if we do go ahead and push the changes, document them as well as we can and list what would need to be done to get the boards to a working state (for these changes). Martin

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AGESA fam15 code removals
by Kyösti Mälkki 05 Oct '17

05 Oct '17

Hi I can remember exactly one user of AGESA fam15 code from the past 5 years or so. He has informed me of having no possibility to test with the H8QGI he once had access to and as the little discussion on this list about H8SCM also appears seized now, I have to inform none of the AGESA fam15 boards in the tree have reached EARLY_CBMEM_INIT and nobody is actively working on the topic. So after release of 4.7, I would place the following boards on the immediate LATE_CBMEM_INIT kill-list: amd/dinar, supermicro/h8scm, supermicro/h8qgi, tyan/s8226. After removal of the boards, related platform code and vendorcode subtree will be removed as well. Actually, I would like to commit the incomplete work on these fam15 boards (that do pass abuild) even before 4.7 release to proceed with other related cleanups on AGESA. Work on the boards has been available for review/improvement since Aug 01 but there has been no takers, and really nobody with hardware to even ask for testing. Here's the top-of-tree cleanup commit, with fam15 as dependency, that I'd like to get in before 4.7 release: https://review.coreboot.org/c/21695/3 Now this would be against our normal no-regressions policy, but we really do not have any feedback for these fam15 boards for so long time now... So would it matter? If I just tagged them with [INCOMPLETE] or something like that? Kyösti

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Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure
by ron minnich 05 Oct '17

05 Oct '17

On Thu, Oct 5, 2017 at 2:55 AM Anshuman Aggarwal < anshuman.aggarwal(a)gmail.com> wrote: > > > @ron, I assume you mean a livecd like alternative which I can connect > to and use to debug the issue? > no, I mean putting the kernel in firmware and using the network as the equivalent of a serial port. It's a widely used technique since around 2000.

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Fwd: [U-Boot] Broadwell-DE bare metal
by Zoran Stojsavljevic 05 Oct '17

05 Oct '17

Well. well, well... We have here major architectural break?! It seems that IFWI is after all replacing FSP (as clean cut first stage boot-loader)??? FSP is going to slip to oblivion, don't you all think? It seems that we have here new, two stage boot-loader approach, with MBR sector, containing booting U-Boot data in-between! ;-) Very interesting observation, I should say. Waiting for unwinding the ball. Zoran ---------- Forwarded message ---------- From: Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> Date: Thu, Oct 5, 2017 at 1:27 PM Subject: Re: [U-Boot] Broadwell-DE bare metal To: Bin Meng <bmeng.cn(a)gmail.com> Cc: vnktux <vnktux(a)protonmail.com>, "u-boot(a)lists.denx.de" < u-boot(a)lists.denx.de> > So far Broadwell-DE is not supported in U-Boot. However it is on my todo list. Excellent thread! Just what I needed, and was thinking to enter! ;-) What will be the architecture of this porting effort? The same question as I have asked an hour ago for ATOM E3900/APL-I. Thank you in advance, Zoran Stojsavljevic _______ On Thu, Oct 5, 2017 at 1:21 PM, Bin Meng <bmeng.cn(a)gmail.com> wrote: > Hi, > > On Thu, Oct 5, 2017 at 5:43 PM, vnktux <vnktux(a)protonmail.com> wrote: > > Hi Bin, > > > > Thanks a lot for the reply. Is there something I can do to help you? I > mean > > that's my graduation project and I will have to work on it either I > succed > > or not, and here I have available hardware aswell. > > > > If you can't wait, you can start trying to port U-Boot on your > Broadwell-DE board, and I can help review. Thanks! > > Regards, > Bin > _______________________________________________ > U-Boot mailing list > U-Boot(a)lists.denx.de > https://lists.denx.de/listinfo/u-boot >

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Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure
by Taiidan＠gmx.com 05 Oct '17

05 Oct '17

On 10/05/2017 05:54 AM, Anshuman Aggarwal wrote: > @Taiidan, as much as I love all things libre, my budget doesn't come > close to buying those motherboards :(. I like the idea of using > another machine to view the grub serial. Maybe using a Raspberry Pi RPI isn't free hardware and the RPI foundation only likes open source when it saves them money/is convenient so I wouldn't get one (maybe get a beagleboard?) You can get a KCMA-D8 for $250 and a compatible C32 decent cpu (to play video games in a VM like me) for $20 FYI, then all you need is DDR3 RAM and you can swap the internals of whatever you have now.

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Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure
by Piotr Kubaj 05 Oct '17

05 Oct '17

You might want to check what PCengines guys did, their APU doesn't have video (only serial), and the keyboard works in SeaBIOS. On 17-10-05 12:00:01, coreboot-request(a)coreboot.org wrote: >Send coreboot mailing list submissions to > coreboot(a)coreboot.org > >To subscribe or unsubscribe via the World Wide Web, visit > https://mail.coreboot.org/mailman/listinfo/coreboot >or, via email, send a message with subject or body 'help' to > coreboot-request(a)coreboot.org > >You can reach the person managing the list at > coreboot-owner(a)coreboot.org > >When replying, please edit your Subject line so it is more specific >than "Re: Contents of coreboot digest..." > > >Today's Topics: > > 1. Re: Broadwell-DE NS FSP not support (Hilbert Tu (???_Pegatron)) > 2. Re: Ability to remotely debug the grub menu in case of boot > failure (Anshuman Aggarwal) > > >---------------------------------------------------------------------- > >Message: 1 >Date: Thu, 5 Oct 2017 01:40:04 +0000 >From: Hilbert Tu(???_Pegatron) <Hilbert_Tu(a)pegatroncorp.com> >To: Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> >Cc: "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> >Subject: Re: [coreboot] Broadwell-DE NS FSP not support >Message-ID: > <9EFDF862436D5041AD8D822C06211F15014913EF(a)PTW-EX-36.PEGA.CORP.PEGATRON> > >Content-Type: text/plain; charset="utf-8" > >Hi Zoran/Piotr, > >Yes, the current available FSP does not support BDX-DE NS. I got same information from local Intel FAE. So I don?t know the next step to evaluate my CRB. > >@Taiidan, >Thanks for your information, ?6 months for skilled person? ? Maybe I should try BIOS/UEFI first. > >-Hilbert > >From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] >Sent: Wednesday, October 04, 2017 7:57 PM >To: Hilbert Tu(???_Pegatron) >Cc: coreboot(a)coreboot.org >Subject: Re: [coreboot] Broadwell-DE NS FSP not support > >Hello Hilbert, > >There is none FSP for BDW-DE? Are you sure?? And how did you conclude that??? > >Here is the answer: https://github.com/IntelFsp/FSP > >Intel? Xeon? Processor D Product Family (formerly Broadwell-DE, Compliant with FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE https://github.com/IntelFsp/FSP.git > ><https://github.com/IntelFsp/FSP.git> >git clone -b Broadwell-DE <https://github.com/IntelFsp/FSP.git> https://github.com/IntelFsp/FSP.git > ><https://github.com/IntelFsp/FSP.git> >Zoran >_______ > >On Tue, Oct 3, 2017 at 4:39 AM, Hilbert Tu(???_Pegatron) <Hilbert_Tu(a)pegatroncorp.com<mailto:Hilbert_Tu@pegatroncorp.com>> wrote: >Hi, >I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does that mean I can?t use coreboot as boot loader if Intel FSP not available for my platform? If not, does anyone know how to do that? Please help. Thanks. >-Hilbert >This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. >?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? > >-- >coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> >https://mail.coreboot.org/mailman/listinfo/coreboot > >

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coreboot October 2017