coreboot June 2016

coreboot@coreboot.org

43 participants
86 discussions

Re: [coreboot] The GbE is not activated on my Board.
by 김유석 30 Jun '16

30 Jun '16

Dear Sir. This issue was resolved. Cause is *"size of coreboot.bin"* My work history is see below. 1. Replace the flash memory on my EVB My SG-2440 is have a 8MByte flash memory, But I'll use the 16MByte flash. So, I was replace the flash memory 8MByte to 16MByte. original flash : WINBOND W25Q64 (8MByte) new flash : WINBOND W25Q128(16MByte) 2. Change value of "ROM chip size" 8 MB to 16 MB 3. run make I was successfully build the coreboot. and got a "coreboot.bin". It is 16MByte size. *But this image is boot fail on my EVB* =>*I don't understand* 4. revert "ROM chip size" I was revert value of "ROM chip size" to 8MByte. And write to start address 0x800000 on 16MByte flash memory. => *booting is success*, *But GbE is not running.* 5. replace the flash memory chip 16MByte to 8MByte. I'm try to replace the flash memoy 16MByte to 8MByte. And write to start address 0x00 on 8MByte flash memory. => *booting is success*, *GbE is running.* *Anyway*, I was success "enable the GbE". But I don't understand this sistuation. Have a any idea? Thank you. 2016-06-25 오후 11:46에 Guckian, David 이(가) 쓴 글: > > Hi, > > You are using the Intel Rangeley FSP 4.0 release. > > I assume that you downloaded this from > http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-s… > > > With this download you should have received the supporting > documentation, including the FSP Integration Guide. > > Also included in the download you should have received the > RangeleyFsp.bsf file. > > This BSF file can be used with the Intel BCT, also available on > http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-s… > , to configure settings in the Intel FSP binary. > > Review the FSP Integration Guide for more info regarding the FSP > binary configuration settings. > > Maybe you have configured the Rangeley FSP binary to disable the GbE > devices. > > Use the BCT to enable the GbE devices, look for the “Enable LAN” option. > > Also, coreboot has the ability to overwrite these settings via the > UPD_DATA_REGION structure. > > Please search your coreboot for PcdEnableLan, if found make sure this > is set to “1”. > > Regards, > > David > > *From:*coreboot [mailto:coreboot-bounces@coreboot.org] *On Behalf Of > *WANG FEI > *Sent:* Thursday, June 23, 2016 10:16 PM > *To:* 김유석<poplinux0(a)gmail.com> > *Cc:* coreboot <coreboot(a)coreboot.org> > *Subject:* Re: [coreboot] The GbE is not activated on my Board. > > Can you send me the descriptor.bin and your coreboot image? I can > review it. > > BTW, your image is running on Mohon Peak platform, right? I just have > one Mohon Peak platform to test. > > On Wed, Jun 22, 2016 at 7:37 AM, 김유석 <poplinux0(a)gmail.com > <mailto:poplinux0@gmail.com>> wrote: > > Dear Sir. > > I have already defined the "CONFIG_IFD_BIN_PATH" > > *131 CONFIG_HAVE_IFD_BIN=y* > 308 # > 309 # Southbridge > 310 # > 311 # CONFIG_AMD_SB_CIMX is not set > 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set > 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set > 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y > 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set > 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set > * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y > 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* > > And successfully add to coreboot.bin > > > poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin > File src/oem_dumped.bin is 8388608 bytes > > FLMAP0: 0x01040003 > NR: 1 > FRBA: 0x40 > NC: 1 > FCBA: 0x30 > FLMAP1: 0x09100206 > ISL: 0x09 > FPSBA: 0x100 > NM: 2 > FMBA: 0x60 > FLMAP2: 0x00210020 > PSL: 0x2100 > FMSBA: 0x200 > FLUMAP1: 0x000002e0 > Intel ME VSCC Table Length (VTL): 2 > Intel ME VSCC Table Base Address (VTBA): 0x000e00 > > ME VSCC table: > JID0: 0x001740ef > SPI Componend Device ID 1: 0x17 > SPI Componend Device ID 0: 0x40 > SPI Componend Vendor ID: 0xef > VSCC0: 0x20052005 > Lower Erase Opcode: 0x20 > Lower Write Enable on Write Status: 0x50 > Lower Write Status Required: No > Lower Write Granularity: 64 bytes > Lower Block / Sector Erase Size: 4KB > Upper Erase Opcode: 0x20 > Upper Write Enable on Write Status: 0x50 > Upper Write Status Required: No > Upper Write Granularity: 64 bytes > Upper Block / Sector Erase Size: 4KB > > OEM Section: > 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > Found Region Section > FLREG0: 0x000f0000 > Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff > FLREG1: 0x07ff0010 > Flash Region 1 (BIOS): 00010000 - 007fffff > FLREG2: 0x00000fff > Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) > FLREG3: 0x00000fff > Flash Region 3 (GbE): 00fff000 - 00000fff (unused) > FLREG4: 0x00000fff > Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) > > Found Component Section > FLCOMP 0x09200024 > Dual Output Fast Read Support: not supported > Read ID/Read Status Clock Frequency: 33MHz > Write/Erase Clock Frequency: 33MHz > Fast Read Clock Frequency: 33MHz > Fast Read Support: not supported > Read Clock Frequency: 20MHz > Component 2 Density: 8MB > Component 1 Density: 8MB > FLILL 0x00000000 > Invalid Instruction 3: 0x00 > Invalid Instruction 2: 0x00 > Invalid Instruction 1: 0x00 > Invalid Instruction 0: 0x00 > FLPB 0x00000000 > Flash Partition Boundary Address: 0x000000 > > Found PCH Strap Section > PCHSTRP0: 0x00080002 > PCHSTRP1: 0x00000000 > PCHSTRP2: 0x00000000 > PCHSTRP3: 0x00000003 > PCHSTRP4: 0x0000007f > PCHSTRP5: 0x007fffc0 > PCHSTRP6: 0x0001c7c0 > PCHSTRP7: 0x00000624 > PCHSTRP8: 0x00000000 > PCHSTRP9: 0xffffffff > PCHSTRP10: 0xffffffff > PCHSTRP11: 0xffffffff > PCHSTRP12: 0xffffffff > PCHSTRP13: 0xffffffff > PCHSTRP14: 0xffffffff > PCHSTRP15: 0xffffffff > PCHSTRP16: 0xffffffff > PCHSTRP17: 0xffffffff > > Found Master Section > FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) > Platform Data Region Write Access: enabled > GbE Region Write Access: enabled > Intel ME Region Write Access: enabled > Host CPU/BIOS Region Write Access: enabled > Flash Descriptor Write Access: enabled > Platform Data Region Read Access: enabled > GbE Region Read Access: enabled > Intel ME Region Read Access: enabled > Host CPU/BIOS Region Read Access: enabled > Flash Descriptor Read Access: enabled > Requester ID: 0x0000 > > FLMSTR2: 0x08090118 (Intel ME) > Platform Data Region Write Access: disabled > GbE Region Write Access: enabled > Intel ME Region Write Access: disabled > Host CPU/BIOS Region Write Access: disabled > Flash Descriptor Write Access: disabled > Platform Data Region Read Access: disabled > GbE Region Read Access: enabled > Intel ME Region Read Access: disabled > Host CPU/BIOS Region Read Access: disabled > Flash Descriptor Read Access: enabled > Requester ID: 0x0118 > > FLMSTR3: 0xffffffff (GbE) > Platform Data Region Write Access: enabled > GbE Region Write Access: enabled > Intel ME Region Write Access: enabled > Host CPU/BIOS Region Write Access: enabled > Flash Descriptor Write Access: enabled > Platform Data Region Read Access: enabled > GbE Region Read Access: enabled > Intel ME Region Read Access: enabled > Host CPU/BIOS Region Read Access: enabled > Flash Descriptor Read Access: enabled > Requester ID: 0xffff > > Found Processor Strap Section > ????: 0xffffffff > ????: 0xffffffff > ????: 0xffffffff > ????: 0xffffffff > > > But, GbE still not running. > > Please advise to me. > > Thank you. > > > > > > > > 2016-06-22 오전 12:54에 WANG FEI 이(가) 쓴 글: > > INCLUDE_ME & ME_PATH was used before, but it has changed to > IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with > path/descriptor.bin? It should work! > > On Tue, Jun 21, 2016 at 2:16 AM, 김유석 <poplinux0(a)gmail.com > <mailto:poplinux0@gmail.com>> wrote: > > Dear Sir. > > Thank's your prompt reply. > > My coreboot source code download from coreboot GIT and > ADI's coreboot GIT. both. > > This time, I work on official coreboot GIT(not ADI's GIT, > but i can do ADI's GIT) > > > > *- attach the descriptor.bin > > * I was select the "CONFIG_HAVE_IFD_BIN", > "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the > "CONFIG_IFD_BIN_PATH". > And descriptor.bin is extract from ADI's EVB. > > *131 CONFIG_HAVE_IFD_BIN=y* > 308 # > 309 # Southbridge > 310 # > 311 # CONFIG_AMD_SB_CIMX is not set > 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set > 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set > 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y > 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set > 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set > * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y > 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* > > > > > > > *- Not exist "INCLUDE_ME" and "ME_PATH"* > > I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because > thie keyword is not exist coreboot's source tree. > > I was try to find the "INCLUDE_ME" and "ME_PATH" from > coreboot source, But not exist this keyword. > > *poplinux@raw coreboot $ > ls* > 3rdparty Documentation Makefile README cscope.out > src toolchain.inc > COPYING MAINTAINERS Makefile.inc build payloads > tags util > > *poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn* > > *poplinux@raw coreboot $ > grep "ME_PATH" * -Rn* > cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT > cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT > cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT > src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT > src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT > src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT > src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: > if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) > src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: > if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && > src/drivers/intel/fsp1_1/romstage.c:181: > !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && > src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT > > > Please advise to me. > > Thank you. > > > > > 2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글: > > Here is a sample, > > Please select INCLUDE_ME to y and set ME_PATH to point > to your descriptor.bin (Path/descriptor.bin, refer to > FSP_FILE as a sample). > > On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI > <wangfei.jimei(a)gmail.com > <mailto:wangfei.jimei@gmail.com>> wrote: > > YuSeok, how did you attach the descriptor.bin to > your coreboot? Did you follow the previous mail to > include descriptor.bin with INCLUDE_ME and ME_PATH > in .config? > > On Mon, Jun 20, 2016 at 6:46 AM, 김유석 > <poplinux0(a)gmail.com <mailto:poplinux0@gmail.com>> > wrote: > > Dear Sir. > > > My ENV > > EVB : ADI SG-2440 > > source : official coreboot > > FSP : intel FSP 4.0 > > I was successfully build-up the coreboot and > successfully boot-up my EVB. > > But My EVB's GbE is not activated(not running.) > > So, I was try to boot using the original OEM > bios(from ADI). *This image is actvate the GbE*. > > Another developer was same quetion to Coreboot > communite. And He is resolved this issue. > > https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html > > This guy's said that "Must add the > descriptor.bin to coreboot.bin". > > So, I was extract the descriptor.bin from > ADI's coreboot.bin > > And successfully attached the descriptor.bin > to my coreboot.bin. > > *oem_dumped.bin => ADI's default coreboot.bin, > This image are activated the GbE.* > > *poplinux@raw bins $ >* ./ifdtool -x > src/oem_dumped.bin > File src/oem_dumped.bin is 8388608 bytes > Flash Region 0 (Flash Descriptor): > 00000000 - 0000ffff > Flash Region 1 (BIOS): 00010000 - 007fffff > Flash Region 2 (Intel ME): 00fff000 - > 00000fff (unused) > Flash Region 3 (GbE): 00fff000 - 00000fff > (unused) > Flash Region 4 (Platform Data): 00fff000 - > 00000fff (unused) > > *poplinux@raw bins $ >* ln -s > ./flashregion_0_flashdescriptor.bin descriptor.bin > *poplinux@raw bins $ >* ./ifdtool -d > ./descriptor.bin > File ./descriptor.bin is 65536 bytes > FLMAP0: 0x01040003 > NR: 1 > FRBA: 0x40 > NC: 1 > FCBA: 0x30 > FLMAP1: 0x09100206 > ISL: 0x09 > FPSBA: 0x100 > NM: 2 > FMBA: 0x60 > FLMAP2: 0x00210020 > PSL: 0x2100 > FMSBA: 0x200 > FLUMAP1: 0x000002e0 > Intel ME VSCC Table Length (VTL): 2 > Intel ME VSCC Table Base Address (VTBA): > 0x000e00 > > ME VSCC table: > JID0: 0x001740ef > SPI Componend Device ID 1: 0x17 > SPI Componend Device ID 0: 0x40 > SPI Componend Vendor ID: 0xef > VSCC0: 0x20052005 > Lower Erase Opcode: 0x20 > Lower Write Enable on Write Status: 0x50 > Lower Write Status Required: No > Lower Write Granularity: 64 bytes > Lower Block / Sector Erase Size: 4KB > Upper Erase Opcode: 0x20 > Upper Write Enable on Write Status: 0x50 > Upper Write Status Required: No > Upper Write Granularity: 64 bytes > Upper Block / Sector Erase Size: 4KB > > OEM Section: > 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 > 00 00 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 > > Found Region Section > FLREG0: 0x000f0000 > Flash Region 0 (Flash Descriptor): > 00000000 - 0000ffff > FLREG1: 0x07ff0010 > Flash Region 1 (BIOS): 00010000 - 007fffff > FLREG2: 0x00000fff > Flash Region 2 (Intel ME): 00fff000 - > 00000fff (unused) > FLREG3: 0x00000fff > Flash Region 3 (GbE): 00fff000 - 00000fff > (unused) > FLREG4: 0x00000fff > Flash Region 4 (Platform Data): 00fff000 - > 00000fff (unused) > > Found Component Section > FLCOMP 0x09200024 > Dual Output Fast Read Support: not supported > Read ID/Read Status Clock Frequency: 33MHz > Write/Erase Clock Frequency: 33MHz > Fast Read Clock Frequency: 33MHz > Fast Read Support: not > supported > Read Clock Frequency: 20MHz > Component 2 Density: 8MB > Component 1 Density: 8MB > FLILL 0x00000000 > Invalid Instruction 3: 0x00 > Invalid Instruction 2: 0x00 > Invalid Instruction 1: 0x00 > Invalid Instruction 0: 0x00 > FLPB 0x00000000 > Flash Partition Boundary Address: 0x000000 > > Found PCH Strap Section > PCHSTRP0: 0x00080002 > PCHSTRP1: 0x00000000 > PCHSTRP2: 0x00000000 > PCHSTRP3: 0x00000003 > PCHSTRP4: 0x0000007f > PCHSTRP5: 0x007fffc0 > PCHSTRP6: 0x0001c7c0 > PCHSTRP7: 0x00000624 > PCHSTRP8: 0x00000000 > PCHSTRP9: 0xffffffff > PCHSTRP10: 0xffffffff > PCHSTRP11: 0xffffffff > PCHSTRP12: 0xffffffff > PCHSTRP13: 0xffffffff > PCHSTRP14: 0xffffffff > PCHSTRP15: 0xffffffff > PCHSTRP16: 0xffffffff > PCHSTRP17: 0xffffffff > > Found Master Section > FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) > Platform Data Region Write Access: enabled > GbE Region Write Access: enabled > Intel ME Region Write Access: enabled > Host CPU/BIOS Region Write Access: enabled > Flash Descriptor Write Access: enabled > Platform Data Region Read Access: enabled > GbE Region Read Access: enabled > Intel ME Region Read Access: enabled > Host CPU/BIOS Region Read Access: enabled > Flash Descriptor Read Access: enabled > Requester ID: 0x0000 > > FLMSTR2: 0x08090118 (Intel ME) > Platform Data Region Write Access: disabled > GbE Region Write Access: enabled > Intel ME Region Write Access: disabled > Host CPU/BIOS Region Write Access: disabled > Flash Descriptor Write Access: disabled > Platform Data Region Read Access: disabled > GbE Region Read Access: enabled > Intel ME Region Read Access: disabled > Host CPU/BIOS Region Read Access: disabled > Flash Descriptor Read Access: enabled > Requester ID: 0x0118 > > FLMSTR3: 0xffffffff (GbE) > Platform Data Region Write Access: enabled > GbE Region Write Access: enabled > Intel ME Region Write Access: enabled > Host CPU/BIOS Region Write Access: enabled > Flash Descriptor Write Access: enabled > Platform Data Region Read Access: enabled > GbE Region Read Access: enabled > Intel ME Region Read Access: enabled > Host CPU/BIOS Region Read Access: enabled > Flash Descriptor Read Access: enabled > Requester ID: 0xffff > > Found Processor Strap Section > ????: 0xffffffff > ????: 0xffffffff > ????: 0xffffffff > ????: 0xffffffff > > But GbE is still de-activated. boot log is see > below. > > PCI: pci_scan_bus for bus 00 > PCI: 00:00.0 [8086/0000] ops > PCI: 00:00.0 [8086/1f0e] enabled > Capability: type 0x10 @ 0x40 > Capability: type 0x01 @ 0x80 > Capability: type 0x0d @ 0x88 > Capability: type 0x05 @ 0x90 > Capability: type 0x10 @ 0x40 > PCI: 00:01.0 subordinate bus PCI Express > PCI: 00:01.0 [8086/1f10] enabled > PCI: Static device PCI: 00:02.0 not found, > disabling it. > Capability: type 0x10 @ 0x40 > Capability: type 0x01 @ 0x80 > Capability: type 0x0d @ 0x88 > Capability: type 0x05 @ 0x90 > Capability: type 0x10 @ 0x40 > PCI: 00:03.0 subordinate bus PCI Express > PCI: 00:03.0 [8086/1f12] enabled > PCI: Static device PCI: 00:04.0 not found, > disabling it. > PCI: 00:0b.0 [8086/1f18] enabled > PCI: 00:0e.0 [8086/1f14] enabled > PCI: 00:0f.0 [8086/1f16] enabled > PCI: 00:13.0 [8086/1f15] enabled > *PCI: Static device PCI: 00:14.0 not found, > disabling it. > PCI: Static device PCI: 00:14.1 not found, > disabling it. > PCI: Static device PCI: 00:14.2 not found, > disabling it. > PCI: Static device PCI: 00:14.3 not found, > disabling it*. > > I don't have a any idea for activate the GbE. > > Please advise to me. > > Thank you. > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot > > -------------------------------------------------------------- > Intel Research and Development Ireland Limited > Registered in Ireland > Registered Office: Collinstown Industrial Park, Leixlip, County Kildare > Registered Number: 308263 > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. >

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ASUS KFSN4-DRE (K8) Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 29 Jun '16

29 Jun '16

The ASUS KFSN4-DRE (K8) fails verification for branch master as of commit 78461a9d55de07f3187b48dfd6abca48db90e906 The following tests failed: BOOT_FAILURE Commits since last successful test: 78461a9 soc/intel/apollolake: Change PCI macros to match Skylake 9d8b2ff nvramcui: Update Makefile See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE (K8) test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

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F2A-85M: Different VGA BIOS needed after CPU Upgrade?
by Daniel Kulesz 28 Jun '16

28 Jun '16

Hi folks, I upgraded the CPU in my F2A-85M from a A4-5300 (Trinity) to a A10-6700 (Richland). The board had Coreboot installed before with the VGA BIOS extracted from the A4-5300. However, I did not get any video output when trying to boot after the upgrade, so I replaced the flash chip with a backup with the vendor BIOS that works. Is it likely that the A10-6700 needs a different VGA BIOS or does this this rather look like a different issue? I don't want to experiment too much because the BIOS chips are hardware-wise pretty fragile (even when using the extractor tool). Cheers, Daniel

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Project for thesis
by Sergio Valverde 28 Jun '16

28 Jun '16

Hello: My name is Sergio Valverde and I'm a student at Universidad de Costa Rica. I came across Google Summer of Code and I'm very interested in collaborating with you if any project of those is still available. I'm eager to participate in an open source project, especially one that involves Linux device drivers and Kernel hacking. I'm currently finishing my licentiate ("licenciatura") degree, which would be a degree between bachelor and master here in Costa Rica. For graduation, it requires a bachelor-level thesis, so I wanted to know if you have a project that has that kind of scope (or if I can propose one) and if it would be available for a student like me to collaborate. My background is in electronic engineering and I'm currently working as an embedded software developer in Hewlett Packard Enterprise in Costa Rica. I'm working in a SDK team for a networking ASIC and my main duties have involved building firmware images with Yocto, writing Linux device drivers for PCIe and coding software to interface high-level functions with hardware registers. I'm really looking forward for whatever information you can give me in this matter. I attached my resume to this mail and my Linkedin profile URL is https://cr.linkedin.com/in/sergio-valverde-9058b971. Hopefully we can work together. Sergio Valverde

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New on blogs.coreboot.org: [GSoC] Better RISC-V support, week #4/5
by WordPress 27 Jun '16

27 Jun '16

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Re: [coreboot] How to get support for amd southbridge rs780l
by Alexey Borovikov 27 Jun '16

27 Jun '16

Thanks, but this document not consists information about RS780L. I tried to register on the AMD Emdedded Devsite. I was able to start up the internal graphics core, but unfortunately only in text mode. I think the problem in the initialization in funcution - internal_gfx_pci_dev_init and rs780_internal_gfx_enable (src\southbridge\amd\rs780\gfx.c). The lack of documentation does not give me the opportunity to properly install the necessary bits for gfx. From: Zoran Stojsavljevic Sent: Monday, June 27, 2016 7:08 AM To: Alexey Borovikov Cc: coreboot Subject: Re: [coreboot] How to get support for amd southbridge rs780l Privet Alex. Maybe this might help you/mozet eto pomozet vam (I googled it it from Germany)? 43734 AMD 780G Family BIOS Developer’s Guide 1.01 - © 2009 Advanced Micro Devices, Inc. http://support.amd.com/TechDocs/43734.pdf Document also attached. Zoran On Sun, Jun 26, 2016 at 7:55 PM, Alexey Borovikov via coreboot <coreboot(a)coreboot.org> wrote: Hi, I porting Coreboot on the motherboard Asus m5a78l-m lx3 (AMD Fam10h + 760G (RS780L). I cant set the correct memory map and launch the internal graphics core. I think the problem is an incorrect initialization Southbridge RS780L and gfx. The lack of documentation on the chipset RS780L and the source code to initialize it makes it impossible to complete the porting. How can I get support from AMD, get documentation or source code for initialize Southbridge RS780L and gfx? All thanks! -- coreboot mailing list: coreboot(a)coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot -------------------------------------------------------------------------------- -- coreboot mailing list: coreboot(a)coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] T420 Optimus/NVIDIA GPU support
by Patrick Rudolph 27 Jun '16

27 Jun '16

On 2016-06-26 07:25 AM, Intel Miner wrote: > Hi everyone, > > Apologies if this is the wrong place to ask about this, but > > I'm eyeing off buying a Lenovo T420 ThinkPad, specifically one with the > NVIDIA GPU, with "Optimus" support > > The information I can dig up on the initial support says that the NVIDIA > GPU models are NOT supported by Coreboot > > However I see in the hybrid_graphics.c file that there's a listing for the > "T420/T520" (the T520 seemingly /does/ support the NVIDIA GPU?) > > I can't seem to find any up-to-date information either way regarding the > GPU status in the T420 however. Any information regarding this would be > appreciated :) > > (Alternatively I could just purchase one, build Coreboot and try, of > course!) Hi ! Latest coreboot does support Nvidia GPUs on all Txx models, but it doesn't support Optimus. The hybrid_graphics is for switching display panel to the selected GPU on Optimus muxed laptops. At the moment you can choose to use one of the GPUs at boot time! The other one will be disabled. In theory you could use both GPU at the same time using DRI_PRIME (with latest HEAD), but it will use much more power, as Optimus isn't supported, and the Nvidia GPU is always active. What's missing to implement Nvidia Optimus: * ACPI for panel switching on "muxed" devices * ACPI for power switching on all devices Regards, Patrick

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How to get support for amd southbridge rs780l
by Alexey Borovikov 27 Jun '16

27 Jun '16

Hi, I porting Coreboot on the motherboard Asus m5a78l-m lx3 (AMD Fam10h + 760G (RS780L). I cant set the correct memory map and launch the internal graphics core. I think the problem is an incorrect initialization Southbridge RS780L and gfx. The lack of documentation on the chipset RS780L and the source code to initialize it makes it impossible to complete the porting. How can I get support from AMD, get documentation or source code for initialize Southbridge RS780L and gfx? All thanks!

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T420 Optimus/NVIDIA GPU support
by Intel Miner 26 Jun '16

26 Jun '16

Hi everyone, Apologies if this is the wrong place to ask about this, but I'm eyeing off buying a Lenovo T420 ThinkPad, specifically one with the NVIDIA GPU, with "Optimus" support The information I can dig up on the initial support says that the NVIDIA GPU models are NOT supported by Coreboot However I see in the hybrid_graphics.c file that there's a listing for the "T420/T520" (the T520 seemingly /does/ support the NVIDIA GPU?) I can't seem to find any up-to-date information either way regarding the GPU status in the T420 however. Any information regarding this would be appreciated :) (Alternatively I could just purchase one, build Coreboot and try, of course!)

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Re: [coreboot] The GbE is not activated on my Board.
by Guckian, David 25 Jun '16

25 Jun '16

Hi, You are using the Intel Rangeley FSP 4.0 release. I assume that you downloaded this from http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-s… With this download you should have received the supporting documentation, including the FSP Integration Guide. Also included in the download you should have received the RangeleyFsp.bsf file. This BSF file can be used with the Intel BCT, also available on http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-s… , to configure settings in the Intel FSP binary. Review the FSP Integration Guide for more info regarding the FSP binary configuration settings. Maybe you have configured the Rangeley FSP binary to disable the GbE devices. Use the BCT to enable the GbE devices, look for the “Enable LAN” option. Also, coreboot has the ability to overwrite these settings via the UPD_DATA_REGION structure. Please search your coreboot for PcdEnableLan, if found make sure this is set to “1”. Regards, David From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of WANG FEI Sent: Thursday, June 23, 2016 10:16 PM To: 김유석 <poplinux0(a)gmail.com> Cc: coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] The GbE is not activated on my Board. Can you send me the descriptor.bin and your coreboot image? I can review it. BTW, your image is running on Mohon Peak platform, right? I just have one Mohon Peak platform to test. On Wed, Jun 22, 2016 at 7:37 AM, 김유석 <poplinux0(a)gmail.com<mailto:poplinux0@gmail.com>> wrote: Dear Sir. I have already defined the "CONFIG_IFD_BIN_PATH" 131 CONFIG_HAVE_IFD_BIN=y 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin" And successfully add to coreboot.bin poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin File src/oem_dumped.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But, GbE still not running. Please advise to me. Thank you. 2016-06-22 오전 12:54에 WANG FEI 이(가) 쓴 글: INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work! On Tue, Jun 21, 2016 at 2:16 AM, 김유석 <poplinux0(a)gmail.com<mailto:poplinux0@gmail.com>> wrote: Dear Sir. Thank's your prompt reply. My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both. This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT) - attach the descriptor.bin I was select the "CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the "CONFIG_IFD_BIN_PATH". And descriptor.bin is extract from ADI's EVB. 131 CONFIG_HAVE_IFD_BIN=y 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin" [cid:image001.jpg@01D1CEED.67E8B510] - Not exist "INCLUDE_ME" and "ME_PATH" I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree. I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword. poplinux@raw coreboot $ > ls 3rdparty Documentation Makefile README cscope.out src toolchain.inc COPYING MAINTAINERS Makefile.inc build payloads tags util poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn poplinux@raw coreboot $ > grep "ME_PATH" * -Rn cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT Please advise to me. Thank you. 2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글: Here is a sample, Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample). On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <wangfei.jimei(a)gmail.com<mailto:wangfei.jimei@gmail.com>> wrote: YuSeok, how did you attach the descriptor.bin to your coreboot? Did you follow the previous mail to include descriptor.bin with INCLUDE_ME and ME_PATH in .config? On Mon, Jun 20, 2016 at 6:46 AM, 김유석 <poplinux0(a)gmail.com<mailto:poplinux0@gmail.com>> wrote: Dear Sir. My ENV EVB : ADI SG-2440 source : official coreboot FSP : intel FSP 4.0 I was successfully build-up the coreboot and successfully boot-up my EVB. But My EVB's GbE is not activated(not running.) So, I was try to boot using the original OEM bios(from ADI). This image is actvate the GbE. Another developer was same quetion to Coreboot communite. And He is resolved this issue. https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html This guy's said that "Must add the descriptor.bin to coreboot.bin". So, I was extract the descriptor.bin from ADI's coreboot.bin And successfully attached the descriptor.bin to my coreboot.bin. oem_dumped.bin => ADI's default coreboot.bin, This image are activated the GbE. poplinux@raw bins $ > ./ifdtool -x src/oem_dumped.bin File src/oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff Flash Region 1 (BIOS): 00010000 - 007fffff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) poplinux@raw bins $ > ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin poplinux@raw bins $ > ./ifdtool -d ./descriptor.bin File ./descriptor.bin is 65536 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But GbE is still de-activated. boot log is see below. PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f0e] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it. I don't have a any idea for activate the GbE. Please advise to me. Thank you. -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.

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coreboot June 2016