coreboot June 2016

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86 discussions

Re: [coreboot] fmaptool: fmap_config.h: Base offset missing
by Rolf Evers-Fischer 21 Jun '16

21 Jun '16

On Mon, 20 Jun 2016, Aaron Durbin wrote: > On Thu, Jun 16, 2016 at 8:55 AM, Rolf Evers-Fischer > <embedded24(a)evers-fischer.de> wrote: > > Hello, > > my ApolloLake board was not able to find the "romstage" in the SPI memory, > > because it searched in the wrong part of the memory. > > > > ___FMAP__COREBOOT_BASE was set to the relative offset within the parent > > section, but rdev_readat needs the *absolute* address: There was a > > mismatch. > > However, I was able to fix this problem locally by adding an additional > > fixed offset to fmap_top, like > > Could you please provide an example fmd and the generated header file? > This is the content of the fmd file: FLASH 8M { WP_RO@0x0 0x500000 { SI_DESC@0x0 0x1000 IFWI@0x100000 0x1ff000 RO_SECTION@0x300000 0x200000 { RO_VPD@0x0 0x4000 FMAP@0x4000 0x800 RO_FRID@0x4800 0x40 RO_FRID_PAD@0x4840 0x7c0 COREBOOT(CBFS)@0x5000 0x17b000 GBB@0x180000 0x40000 # logical boot partition 2. Remove with updated CSE SIGN_CSE@0x1c0000 0x10000 } } MISC_RW@0x500000 0x1a000 { RW_MRC_CACHE@0x0 0x10000 RW_ELOG@0x10000 0x4000 RW_SHARED@0x14000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD@0x18000 0x2000 } RW_SECTION_A 0xf0000 { VBLOCK_A 64K FW_MAIN_A(CBFS) 768K RW_FWID_A 64 } RW_SECTION_B 0xf0000 { VBLOCK_B 64K FW_MAIN_B(CBFS) 768K RW_FWID_B 64 } DEVICE_EXTENSION@0x77f000 0x80000 } And this is the content of the generated fmap_config.h: #ifndef FMAPTOOL_GENERATED_HEADER_H_ #define FMAPTOOL_GENERATED_HEADER_H_ #define FMAP_OFFSET 0x304000 #define ___FMAP__COREBOOT_BASE 0x5000 #define ___FMAP__COREBOOT_SIZE 0x17b000 #define ___FMAP__FW_MAIN_A_BASE 0x10000 #define ___FMAP__FW_MAIN_A_SIZE 0xc0000 #define ___FMAP__FW_MAIN_B_BASE 0x10000 #define ___FMAP__FW_MAIN_B_SIZE 0xc0000 #endif There is a new commit, which may fix this problem. I'll test this commit right now: https://review.coreboot.org/15273 > > > > diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c > > index aa652c2..f36a499 100644 > > --- a/src/lib/cbfs.c > > +++ b/src/lib/cbfs.c > > @@ -230,7 +230,7 @@ static int cbfs_master_header_props(struct cbfs_props *props > > if (bdev == NULL) > > return -1; > > > > - size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; > > + size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE + 0x300000; > > > > /* Find location of header using signed 32-bit offset from > > * end of CBFS region. */ > > > > > > But imho this shouldn't be a permanent solution! > > > > Therefore I suggest to modify the 'fmaptool' in such way that it outputs > > the absolute address for (at least) ___FMAP__COREBOOT_BASE, because the > > 'rdev_readat()' function of the 'boot_device_ro()' needs it in this form. > > > > What is your opinion? > > > > Kind regards, > > Rolf > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://www.coreboot.org/mailman/listinfo/coreboot >

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How to change config of SDRAM of intel mohonpeak EVB on coreboot?
by 김유석 21 Jun '16

21 Jun '16

Dear Sir. My own product must need a change the value(config) of sdram. Such as size, speed, and etc. So, I'm try to search and study the coreboot source code, and found out the "vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h" This header are contained the some structure for setup the sdram. such as "MEM_DOWN_DIMM_SPD_DATA;" > 50 typedef struct { > 51 UINT8 DRAMDeviceType; // 2 DRAM Device Type > 52 UINT8 ModuleType; // 3 Module Type > 53 UINT8 SDRAMDensityAndBanks; // 4 SDRAM Density and > Banks > 54 UINT8 SDRAMAddressing; // 5 SDRAM Addressing > 55 UINT8 VDD; // 6 Module Nominal Voltage > 56 UINT8 ModuleOrganization; // 7 Module Organization > 57 UINT8 ModuleMemoryBusWidth; > 94 UINT8 DramManufacturerIdLsb; // 148 DRAM Manufacturer > ID Code, LSB > 95 UINT8 DramManufacturerIdMsb; // 149 DRAM Manufacturer > ID Code, MSB > 96 } MEM_DOWN_DIMM_SPD_DATA; So, I'm try to found **.c* source codes for check configuration point. But, coreboot are not setup the argument of sdram. I don't understand this sisution, Because sdram is must need a some configuration for use. *Why? do not setup the argument of sd**ram ??? *** Please advise to me. Thank you.

2 1

Re: [coreboot] The GbE is not activated on my Board.
by WANG FEI 20 Jun '16

20 Jun '16

Here is a sample, Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample). On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: > YuSeok, how did you attach the descriptor.bin to your coreboot? Did you > follow the previous mail to include descriptor.bin with INCLUDE_ME and > ME_PATH in .config? > > On Mon, Jun 20, 2016 at 6:46 AM, 김유석 <poplinux0(a)gmail.com> wrote: > >> Dear Sir. >> >> >> My ENV >> >> EVB : ADI SG-2440 >> >> source : official coreboot >> >> FSP : intel FSP 4.0 >> >> >> >> I was successfully build-up the coreboot and successfully boot-up my EVB. >> >> >> But My EVB's GbE is not activated(not running.) >> >> >> So, I was try to boot using the original OEM bios(from ADI). *This image >> is **act**vate the GbE*. >> >> >> Another developer was same quetion to Coreboot communite. And He is >> resolved this issue. >> >> <https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html> >> https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html >> >> >> This guy's said that "Must add the descriptor.bin to coreboot.bin". >> >> >> So, I was extract the descriptor.bin from ADI's coreboot.bin >> >> And successfully attached the descriptor.bin to my coreboot.bin. >> >> *oem_dumped.bin => ADI's default **coreboot.bin, This image are >> activated the GbE.* >> >> *poplinux@raw bins $ >* ./ifdtool -x src/oem_dumped.bin >> File src/oem_dumped.bin is 8388608 bytes >> Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff >> Flash Region 1 (BIOS): 00010000 - 007fffff >> Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) >> Flash Region 3 (GbE): 00fff000 - 00000fff (unused) >> Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) >> >> *poplinux@raw bins $ >* ln -s ./flashregion_0_flashdescriptor.bin >> descriptor.bin >> *poplinux@raw bins $ >* ./ifdtool -d ./descriptor.bin >> File ./descriptor.bin is 65536 bytes >> FLMAP0: 0x01040003 >> NR: 1 >> FRBA: 0x40 >> NC: 1 >> FCBA: 0x30 >> FLMAP1: 0x09100206 >> ISL: 0x09 >> FPSBA: 0x100 >> NM: 2 >> FMBA: 0x60 >> FLMAP2: 0x00210020 >> PSL: 0x2100 >> FMSBA: 0x200 >> FLUMAP1: 0x000002e0 >> Intel ME VSCC Table Length (VTL): 2 >> Intel ME VSCC Table Base Address (VTBA): 0x000e00 >> >> ME VSCC table: >> JID0: 0x001740ef >> SPI Componend Device ID 1: 0x17 >> SPI Componend Device ID 0: 0x40 >> SPI Componend Vendor ID: 0xef >> VSCC0: 0x20052005 >> Lower Erase Opcode: 0x20 >> Lower Write Enable on Write Status: 0x50 >> Lower Write Status Required: No >> Lower Write Granularity: 64 bytes >> Lower Block / Sector Erase Size: 4KB >> Upper Erase Opcode: 0x20 >> Upper Write Enable on Write Status: 0x50 >> Upper Write Status Required: No >> Upper Write Granularity: 64 bytes >> Upper Block / Sector Erase Size: 4KB >> >> OEM Section: >> 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 >> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> >> Found Region Section >> FLREG0: 0x000f0000 >> Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff >> FLREG1: 0x07ff0010 >> Flash Region 1 (BIOS): 00010000 - 007fffff >> FLREG2: 0x00000fff >> Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) >> FLREG3: 0x00000fff >> Flash Region 3 (GbE): 00fff000 - 00000fff (unused) >> FLREG4: 0x00000fff >> Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) >> >> Found Component Section >> FLCOMP 0x09200024 >> Dual Output Fast Read Support: not supported >> Read ID/Read Status Clock Frequency: 33MHz >> Write/Erase Clock Frequency: 33MHz >> Fast Read Clock Frequency: 33MHz >> Fast Read Support: not supported >> Read Clock Frequency: 20MHz >> Component 2 Density: 8MB >> Component 1 Density: 8MB >> FLILL 0x00000000 >> Invalid Instruction 3: 0x00 >> Invalid Instruction 2: 0x00 >> Invalid Instruction 1: 0x00 >> Invalid Instruction 0: 0x00 >> FLPB 0x00000000 >> Flash Partition Boundary Address: 0x000000 >> >> Found PCH Strap Section >> PCHSTRP0: 0x00080002 >> PCHSTRP1: 0x00000000 >> PCHSTRP2: 0x00000000 >> PCHSTRP3: 0x00000003 >> PCHSTRP4: 0x0000007f >> PCHSTRP5: 0x007fffc0 >> PCHSTRP6: 0x0001c7c0 >> PCHSTRP7: 0x00000624 >> PCHSTRP8: 0x00000000 >> PCHSTRP9: 0xffffffff >> PCHSTRP10: 0xffffffff >> PCHSTRP11: 0xffffffff >> PCHSTRP12: 0xffffffff >> PCHSTRP13: 0xffffffff >> PCHSTRP14: 0xffffffff >> PCHSTRP15: 0xffffffff >> PCHSTRP16: 0xffffffff >> PCHSTRP17: 0xffffffff >> >> Found Master Section >> FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) >> Platform Data Region Write Access: enabled >> GbE Region Write Access: enabled >> Intel ME Region Write Access: enabled >> Host CPU/BIOS Region Write Access: enabled >> Flash Descriptor Write Access: enabled >> Platform Data Region Read Access: enabled >> GbE Region Read Access: enabled >> Intel ME Region Read Access: enabled >> Host CPU/BIOS Region Read Access: enabled >> Flash Descriptor Read Access: enabled >> Requester ID: 0x0000 >> >> FLMSTR2: 0x08090118 (Intel ME) >> Platform Data Region Write Access: disabled >> GbE Region Write Access: enabled >> Intel ME Region Write Access: disabled >> Host CPU/BIOS Region Write Access: disabled >> Flash Descriptor Write Access: disabled >> Platform Data Region Read Access: disabled >> GbE Region Read Access: enabled >> Intel ME Region Read Access: disabled >> Host CPU/BIOS Region Read Access: disabled >> Flash Descriptor Read Access: enabled >> Requester ID: 0x0118 >> >> FLMSTR3: 0xffffffff (GbE) >> Platform Data Region Write Access: enabled >> GbE Region Write Access: enabled >> Intel ME Region Write Access: enabled >> Host CPU/BIOS Region Write Access: enabled >> Flash Descriptor Write Access: enabled >> Platform Data Region Read Access: enabled >> GbE Region Read Access: enabled >> Intel ME Region Read Access: enabled >> Host CPU/BIOS Region Read Access: enabled >> Flash Descriptor Read Access: enabled >> Requester ID: 0xffff >> >> Found Processor Strap Section >> ????: 0xffffffff >> ????: 0xffffffff >> ????: 0xffffffff >> ????: 0xffffffff >> >> >> But GbE is still de-activated. boot log is see below. >> >> >> PCI: pci_scan_bus for bus 00 >> PCI: 00:00.0 [8086/0000] ops >> PCI: 00:00.0 [8086/1f0e] enabled >> Capability: type 0x10 @ 0x40 >> Capability: type 0x01 @ 0x80 >> Capability: type 0x0d @ 0x88 >> Capability: type 0x05 @ 0x90 >> Capability: type 0x10 @ 0x40 >> PCI: 00:01.0 subordinate bus PCI Express >> PCI: 00:01.0 [8086/1f10] enabled >> PCI: Static device PCI: 00:02.0 not found, disabling it. >> Capability: type 0x10 @ 0x40 >> Capability: type 0x01 @ 0x80 >> Capability: type 0x0d @ 0x88 >> Capability: type 0x05 @ 0x90 >> Capability: type 0x10 @ 0x40 >> PCI: 00:03.0 subordinate bus PCI Express >> PCI: 00:03.0 [8086/1f12] enabled >> PCI: Static device PCI: 00:04.0 not found, disabling it. >> PCI: 00:0b.0 [8086/1f18] enabled >> PCI: 00:0e.0 [8086/1f14] enabled >> PCI: 00:0f.0 [8086/1f16] enabled >> PCI: 00:13.0 [8086/1f15] enabled >> * PCI: Static device PCI: 00:14.0 not found, disabling it.* >> * PCI: Static device PCI: 00:14.1 not found, disabling it.* >> * PCI: Static device PCI: 00:14.2 not found, disabling it.* >> * PCI: Static device PCI: 00:14.3 not found, disabling it*. >> >> >> I don't have a any idea for activate the GbE. >> >> >> Please advise to me. >> >> Thank you. >> >> >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > >

1 0

How can extract descriptor.bin from bios image?
by 김유석 20 Jun '16

20 Jun '16

Dear Sir. My EVB is ADI SG-2440 and mohon peak CRB. This time, My coreboot image are not running GbE. Another guy are said to me that "Must add a descriptor.bin to coreboot.img". And I was found the descriptor.bin from original bios image. See below. * poplinux@raw rangeley $ > ./tools/ifdtool ~/data/project/sdk/intel_rangeley/crb/BIOS/BIOS1_org.bin -d File /home/poplinux/data/project/sdk/intel_rangeley/crb/BIOS/BIOS1_org.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000008e0 Intel ME VSCC Table Length (VTL): 8 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB JID1: 0x00167120 SPI Componend Device ID 1: 0x16 SPI Componend Device ID 0: 0x71 SPI Componend Vendor ID: 0x20 VSCC1: 0xd817d817 Lower Erase Opcode: 0xd8 Lower Write Enable on Write Status: 0x06 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 64KB Upper Erase Opcode: 0xd8 Upper Write Enable on Write Status: 0x06 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 64KB JID2: 0x00177120 SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x71 SPI Componend Vendor ID: 0x20 VSCC2: 0xd817d817 Lower Erase Opcode: 0xd8 Lower Write Enable on Write Status: 0x06 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 64KB Upper Erase Opcode: 0xd8 Upper Write Enable on Write Status: 0x06 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 64KB JID3: 0x00172020 SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x20 SPI Componend Vendor ID: 0x20 VSCC3: 0xd817d817 Lower Erase Opcode: 0xd8 Lower Write Enable on Write Status: 0x06 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 64KB Upper Erase Opcode: 0xd8 Upper Write Enable on Write Status: 0x06 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 64KB OEM Section: 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Found Region Section FLREG0: 0x01ff0000 Flash Region 0 (Flash Descriptor): 00000000 - 001fffff FLREG1: 0x07ff0200 Flash Region 1 (BIOS): 00200000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09300024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x081a0002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0xffff0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0xffff0118 (Intel ME) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff* But I don't have a solution that extract descriptor.bin from bios.image, Because I don't have a offset and size. Please show to me the solution. Thank you.

3 3

The GbE is not activated on my Board.
by 김유석 20 Jun '16

20 Jun '16

Dear Sir. My ENV EVB : ADI SG-2440 source : official coreboot FSP : intel FSP 4.0 I was successfully build-up the coreboot and successfully boot-up my EVB. But My EVB's GbE is not activated(not running.) So, I was try to boot using the original OEM bios(from ADI). *This image is **act**vate the GbE*. Another developer was same quetion to Coreboot communite. And He is resolved this issue. https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html This guy's said that "Must add the descriptor.bin to coreboot.bin". So, I was extract the descriptor.bin from ADI's coreboot.bin And successfully attached the descriptor.bin to my coreboot.bin. *oem_dumped.bin => ADI's default **coreboot.bin, This image are activated the GbE.* *poplinux@raw bins $ >* ./ifdtool -x src/oem_dumped.bin File src/oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff Flash Region 1 (BIOS): 00010000 - 007fffff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) *poplinux@raw bins $ >* ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin *poplinux@raw bins $ >* ./ifdtool -d ./descriptor.bin File ./descriptor.bin is 65536 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But GbE is still de-activated. boot log is see below. PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f0e] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled * PCI: Static device PCI: 00:14.0 not found, disabling it.** ** PCI: Static device PCI: 00:14.1 not found, disabling it.** ** PCI: Static device PCI: 00:14.2 not found, disabling it.** ** PCI: Static device PCI: 00:14.3 not found, disabling it*. I don't have a any idea for activate the GbE. Please advise to me. Thank you.

2 1

kgpe-d16
by ron minnich 20 Jun '16

20 Jun '16

I have a kgpe-d16 with coreboot and it *was* working with linux. I now have a linux kernel that won't boot on fuctory bios or coreboot. I can't recall changing anything ... If somebody's got a known good .config for linux I could sure use it. I'm booting stock tinycore and it seems to hang a lot. thanks ron

1 0

fmaptool: fmap_config.h: Base offset missing
by Rolf Evers-Fischer 20 Jun '16

20 Jun '16

Hello, my ApolloLake board was not able to find the "romstage" in the SPI memory, because it searched in the wrong part of the memory. ___FMAP__COREBOOT_BASE was set to the relative offset within the parent section, but rdev_readat needs the *absolute* address: There was a mismatch. However, I was able to fix this problem locally by adding an additional fixed offset to fmap_top, like diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index aa652c2..f36a499 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -230,7 +230,7 @@ static int cbfs_master_header_props(struct cbfs_props *props if (bdev == NULL) return -1; - size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; + size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE + 0x300000; /* Find location of header using signed 32-bit offset from * end of CBFS region. */ But imho this shouldn't be a permanent solution! Therefore I suggest to modify the 'fmaptool' in such way that it outputs the absolute address for (at least) ___FMAP__COREBOOT_BASE, because the 'rdev_readat()' function of the 'boot_device_ro()' needs it in this form. What is your opinion? Kind regards, Rolf

3 2

ASUS KFSN4-DRE Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 20 Jun '16

20 Jun '16

The ASUS KFSN4-DRE fails verification for branch master as of commit 4b86314495b17f8d944e16cfb726cd665c7d22a1 The following tests failed: VIDEO_FAILURE Commits since last successful test: See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

2 1

Documentation on msr bits on intel cpuid 6ex and later
by Arthur Heymans 20 Jun '16

20 Jun '16

Hi In the code for intel model_6ex there is a comment "TODO Do we want Deep C4 and Dynamic L2 shrinking". On later targets (6fx and 1067) this is done setting some bits in IA32_MISC_ENABLE and MSR_PMG_CST_CONFIG_CONTROL msr. It tried setting the same bits, which should upgrade C2 to C2E and C4 to C4E. The results is that the C2 state consumes noticeably less power. (C4 remains similar in power consumption) Those msr bits are mentioned in intel datasheets on those cpus: http://download.intel.com/design/mobile/datashts/30922106.pdf I can't find documentation on those bits. In the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" those bits are marked as reserved... I would like to know more about this, so if someone can help me on this... -- Arthur Heymans

1 0

Help find datasheet on amd R780L
by Алексей Боровиков 18 Jun '16

18 Jun '16

I can not find any documentation on the northbridge amd R780L (760G). Is there any information on this subject? Help me please.

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