coreboot June 2016

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Re: [coreboot] The GbE is not activated on my Board.
by 김유석 23 Jun '16

23 Jun '16

Dear Sir. I have already defined the "CONFIG_IFD_BIN_PATH" *131 CONFIG_HAVE_IFD_BIN=y* 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y** ** 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* And successfully add to coreboot.bin poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin File src/oem_dumped.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But, GbE still not running. Please advise to me. Thank you. 2016-06-22 오전 12:54에 WANG FEI 이(가) 쓴 글: > INCLUDE_ME & ME_PATH was used before, but it has changed to > IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with > path/descriptor.bin? It should work! > > On Tue, Jun 21, 2016 at 2:16 AM, 김유석 <poplinux0(a)gmail.com > <mailto:poplinux0@gmail.com>> wrote: > > Dear Sir. > > Thank's your prompt reply. > > My coreboot source code download from coreboot GIT and ADI's > coreboot GIT. both. > > This time, I work on official coreboot GIT(not ADI's GIT, but i > can do ADI's GIT) > > > > *- attach the descriptor.bin > > * I was select the "CONFIG_HAVE_IFD_BIN", > "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the > "CONFIG_IFD_BIN_PATH". > And descriptor.bin is extract from ADI's EVB. > > *131 CONFIG_HAVE_IFD_BIN=y* > 308 # > 309 # Southbridge > 310 # > 311 # CONFIG_AMD_SB_CIMX is not set > 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set > 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set > 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y > 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set > 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set > * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y** > ** 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* > > > > > > > *- Not exist "INCLUDE_ME" and "ME_PATH"* > > I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie > keyword is not exist coreboot's source tree. > > I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot > source, But not exist this keyword. > > *poplinux@raw coreboot $ > ls* > 3rdparty Documentation Makefile README cscope.out src > toolchain.inc > COPYING MAINTAINERS Makefile.inc build payloads tags util > > *poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn* > > *poplinux@raw coreboot $ > grep "ME_PATH" * -Rn* > cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT > cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT > cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT > src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT > src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT > src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT > src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if > (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) > src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if > (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && > src/drivers/intel/fsp1_1/romstage.c:181: > !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && > src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT > > > Please advise to me. > > Thank you. > > > > > 2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글: >> Here is a sample, >> >> Please select INCLUDE_ME to y and set ME_PATH to point to your >> descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample). >> >> On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI >> <wangfei.jimei(a)gmail.com <mailto:wangfei.jimei@gmail.com>> wrote: >> >> YuSeok, how did you attach the descriptor.bin to your >> coreboot? Did you follow the previous mail to include >> descriptor.bin with INCLUDE_ME and ME_PATH in .config? >> >> On Mon, Jun 20, 2016 at 6:46 AM, 김유석 <poplinux0(a)gmail.com >> <mailto:poplinux0@gmail.com>> wrote: >> >> Dear Sir. >> >> >> My ENV >> >> EVB : ADI SG-2440 >> >> source : official coreboot >> >> FSP : intel FSP 4.0 >> >> >> I was successfully build-up the coreboot and successfully >> boot-up my EVB. >> >> >> But My EVB's GbE is not activated(not running.) >> >> >> So, I was try to boot using the original OEM bios(from >> ADI). *This image is **act**vate the GbE*. >> >> >> Another developer was same quetion to Coreboot communite. >> And He is resolved this issue. >> >> https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html >> >> >> This guy's said that "Must add the descriptor.bin to >> coreboot.bin". >> >> >> So, I was extract the descriptor.bin from ADI's coreboot.bin >> >> And successfully attached the descriptor.bin to my >> coreboot.bin. >> >> *oem_dumped.bin => ADI's default **coreboot.bin, This >> image are activated the GbE.* >> >> *poplinux@raw bins $ >* ./ifdtool -x src/oem_dumped.bin >> File src/oem_dumped.bin is 8388608 bytes >> Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff >> Flash Region 1 (BIOS): 00010000 - 007fffff >> Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) >> Flash Region 3 (GbE): 00fff000 - 00000fff (unused) >> Flash Region 4 (Platform Data): 00fff000 - 00000fff >> (unused) >> >> *poplinux@raw bins $ >* ln -s >> ./flashregion_0_flashdescriptor.bin descriptor.bin >> *poplinux@raw bins $ >* ./ifdtool -d ./descriptor.bin >> File ./descriptor.bin is 65536 bytes >> FLMAP0: 0x01040003 >> NR: 1 >> FRBA: 0x40 >> NC: 1 >> FCBA: 0x30 >> FLMAP1: 0x09100206 >> ISL: 0x09 >> FPSBA: 0x100 >> NM: 2 >> FMBA: 0x60 >> FLMAP2: 0x00210020 >> PSL: 0x2100 >> FMSBA: 0x200 >> FLUMAP1: 0x000002e0 >> Intel ME VSCC Table Length (VTL): 2 >> Intel ME VSCC Table Base Address (VTBA): 0x000e00 >> >> ME VSCC table: >> JID0: 0x001740ef >> SPI Componend Device ID 1: 0x17 >> SPI Componend Device ID 0: 0x40 >> SPI Componend Vendor ID: 0xef >> VSCC0: 0x20052005 >> Lower Erase Opcode: 0x20 >> Lower Write Enable on Write Status: 0x50 >> Lower Write Status Required: No >> Lower Write Granularity: 64 bytes >> Lower Block / Sector Erase Size: 4KB >> Upper Erase Opcode: 0x20 >> Upper Write Enable on Write Status: 0x50 >> Upper Write Status Required: No >> Upper Write Granularity: 64 bytes >> Upper Block / Sector Erase Size: 4KB >> >> OEM Section: >> 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 >> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> >> Found Region Section >> FLREG0: 0x000f0000 >> Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff >> FLREG1: 0x07ff0010 >> Flash Region 1 (BIOS): 00010000 - 007fffff >> FLREG2: 0x00000fff >> Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) >> FLREG3: 0x00000fff >> Flash Region 3 (GbE): 00fff000 - 00000fff (unused) >> FLREG4: 0x00000fff >> Flash Region 4 (Platform Data): 00fff000 - 00000fff >> (unused) >> >> Found Component Section >> FLCOMP 0x09200024 >> Dual Output Fast Read Support: not supported >> Read ID/Read Status Clock Frequency: 33MHz >> Write/Erase Clock Frequency: 33MHz >> Fast Read Clock Frequency: 33MHz >> Fast Read Support: not supported >> Read Clock Frequency: 20MHz >> Component 2 Density: 8MB >> Component 1 Density: 8MB >> FLILL 0x00000000 >> Invalid Instruction 3: 0x00 >> Invalid Instruction 2: 0x00 >> Invalid Instruction 1: 0x00 >> Invalid Instruction 0: 0x00 >> FLPB 0x00000000 >> Flash Partition Boundary Address: 0x000000 >> >> Found PCH Strap Section >> PCHSTRP0: 0x00080002 >> PCHSTRP1: 0x00000000 >> PCHSTRP2: 0x00000000 >> PCHSTRP3: 0x00000003 >> PCHSTRP4: 0x0000007f >> PCHSTRP5: 0x007fffc0 >> PCHSTRP6: 0x0001c7c0 >> PCHSTRP7: 0x00000624 >> PCHSTRP8: 0x00000000 >> PCHSTRP9: 0xffffffff >> PCHSTRP10: 0xffffffff >> PCHSTRP11: 0xffffffff >> PCHSTRP12: 0xffffffff >> PCHSTRP13: 0xffffffff >> PCHSTRP14: 0xffffffff >> PCHSTRP15: 0xffffffff >> PCHSTRP16: 0xffffffff >> PCHSTRP17: 0xffffffff >> >> Found Master Section >> FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) >> Platform Data Region Write Access: enabled >> GbE Region Write Access: enabled >> Intel ME Region Write Access: enabled >> Host CPU/BIOS Region Write Access: enabled >> Flash Descriptor Write Access: enabled >> Platform Data Region Read Access: enabled >> GbE Region Read Access: enabled >> Intel ME Region Read Access: enabled >> Host CPU/BIOS Region Read Access: enabled >> Flash Descriptor Read Access: enabled >> Requester ID: 0x0000 >> >> FLMSTR2: 0x08090118 (Intel ME) >> Platform Data Region Write Access: disabled >> GbE Region Write Access: enabled >> Intel ME Region Write Access: disabled >> Host CPU/BIOS Region Write Access: disabled >> Flash Descriptor Write Access: disabled >> Platform Data Region Read Access: disabled >> GbE Region Read Access: enabled >> Intel ME Region Read Access: disabled >> Host CPU/BIOS Region Read Access: disabled >> Flash Descriptor Read Access: enabled >> Requester ID: 0x0118 >> >> FLMSTR3: 0xffffffff (GbE) >> Platform Data Region Write Access: enabled >> GbE Region Write Access: enabled >> Intel ME Region Write Access: enabled >> Host CPU/BIOS Region Write Access: enabled >> Flash Descriptor Write Access: enabled >> Platform Data Region Read Access: enabled >> GbE Region Read Access: enabled >> Intel ME Region Read Access: enabled >> Host CPU/BIOS Region Read Access: enabled >> Flash Descriptor Read Access: enabled >> Requester ID: 0xffff >> >> Found Processor Strap Section >> ????: 0xffffffff >> ????: 0xffffffff >> ????: 0xffffffff >> ????: 0xffffffff >> >> >> But GbE is still de-activated. boot log is see below. >> >> >> PCI: pci_scan_bus for bus 00 >> PCI: 00:00.0 [8086/0000] ops >> PCI: 00:00.0 [8086/1f0e] enabled >> Capability: type 0x10 @ 0x40 >> Capability: type 0x01 @ 0x80 >> Capability: type 0x0d @ 0x88 >> Capability: type 0x05 @ 0x90 >> Capability: type 0x10 @ 0x40 >> PCI: 00:01.0 subordinate bus PCI Express >> PCI: 00:01.0 [8086/1f10] enabled >> PCI: Static device PCI: 00:02.0 not found, disabling it. >> Capability: type 0x10 @ 0x40 >> Capability: type 0x01 @ 0x80 >> Capability: type 0x0d @ 0x88 >> Capability: type 0x05 @ 0x90 >> Capability: type 0x10 @ 0x40 >> PCI: 00:03.0 subordinate bus PCI Express >> PCI: 00:03.0 [8086/1f12] enabled >> PCI: Static device PCI: 00:04.0 not found, disabling it. >> PCI: 00:0b.0 [8086/1f18] enabled >> PCI: 00:0e.0 [8086/1f14] enabled >> PCI: 00:0f.0 [8086/1f16] enabled >> PCI: 00:13.0 [8086/1f15] enabled >> *PCI: Static device PCI: 00:14.0 not found, disabling it.** >> ** PCI: Static device PCI: 00:14.1 not found, disabling >> it.** >> ** PCI: Static device PCI: 00:14.2 not found, disabling >> it.** >> ** PCI: Static device PCI: 00:14.3 not found, disabling it*. >> >> >> I don't have a any idea for activate the GbE. >> >> >> Please advise to me. >> >> Thank you. >> >> >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> <mailto:coreboot@coreboot.org> >> https://www.coreboot.org/mailman/listinfo/coreboot >> >> >> > >

2 1

some noise on gerrit by lava
by Alexander Couzens 23 Jun '16

23 Jun '16

hi, I'll do some testing with gerrit + jenkins integration related to the lava test framework. I'm using the user *lava* to do those tests. If you get an unrelated `Verified -1` by the user *lava* on your commit, please ping me on irc or by mail so I can fix that. Best, lynxis -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604

1 0

New on blogs.coreboot.org: [GSoC] Multiple status registers, block protection and OTP support, week #3 and #4
by WordPress 22 Jun '16

22 Jun '16

1 0

Re: [coreboot] How to obtain FSP v2.0 for ApolloLake?
by Andrey Petrov 21 Jun '16

21 Jun '16

Hi Rolf, I think blobs aren't uploaded yet because ApolloLake has not been officially announced. You should try contacting Intel to get the blobs. I know Intel does offer blobs to certain customers who use FSP-based solutions. Andrey On 06/21/2016 06:25 AM, Rolf Evers-Fischer wrote: > Coreboot for Intel ApolloLake needs FSP v2.0 blobs. Unfortunately FSP v2.0 is > not offered at www.intel.com/fsp. > Do you know, how or where I could get it? > > Kind regards, > Rolf

1 0

Re: [coreboot] The GbE is not activated on my Board.
by 김유석 21 Jun '16

21 Jun '16

Dear Sir. Thank's your prompt reply. My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both. This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT) *- attach the descriptor.bin * I was select the "CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the "CONFIG_IFD_BIN_PATH". And descriptor.bin is extract from ADI's EVB. *131 CONFIG_HAVE_IFD_BIN=y* 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y** ** 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* *- Not exist "INCLUDE_ME" and "ME_PATH"* I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree. I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword. *poplinux@raw coreboot $ > ls* 3rdparty Documentation Makefile README cscope.out src toolchain.inc COPYING MAINTAINERS Makefile.inc build payloads tags util *poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn* *poplinux@raw coreboot $ > grep "ME_PATH" * -Rn* cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT Please advise to me. Thank you. 2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글: > Here is a sample, > > Please select INCLUDE_ME to y and set ME_PATH to point to your > descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample). > > On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <wangfei.jimei(a)gmail.com > <mailto:wangfei.jimei@gmail.com>> wrote: > > YuSeok, how did you attach the descriptor.bin to your coreboot? > Did you follow the previous mail to include descriptor.bin with > INCLUDE_ME and ME_PATH in .config? > > On Mon, Jun 20, 2016 at 6:46 AM, 김유석 <poplinux0(a)gmail.com > <mailto:poplinux0@gmail.com>> wrote: > > Dear Sir. > > > My ENV > > EVB : ADI SG-2440 > > source : official coreboot > > FSP : intel FSP 4.0 > > > I was successfully build-up the coreboot and successfully > boot-up my EVB. > > > But My EVB's GbE is not activated(not running.) > > > So, I was try to boot using the original OEM bios(from ADI). > *This image is **act**vate the GbE*. > > > Another developer was same quetion to Coreboot communite. And > He is resolved this issue. > > https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html > > > This guy's said that "Must add the descriptor.bin to > coreboot.bin". > > > So, I was extract the descriptor.bin from ADI's coreboot.bin > > And successfully attached the descriptor.bin to my coreboot.bin. > > *oem_dumped.bin => ADI's default **coreboot.bin, This image > are activated the GbE.* > > *poplinux@raw bins $ >* ./ifdtool -x src/oem_dumped.bin > File src/oem_dumped.bin is 8388608 bytes > Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff > Flash Region 1 (BIOS): 00010000 - 007fffff > Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) > Flash Region 3 (GbE): 00fff000 - 00000fff (unused) > Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) > > *poplinux@raw bins $ >* ln -s > ./flashregion_0_flashdescriptor.bin descriptor.bin > *poplinux@raw bins $ >* ./ifdtool -d ./descriptor.bin > File ./descriptor.bin is 65536 bytes > FLMAP0: 0x01040003 > NR: 1 > FRBA: 0x40 > NC: 1 > FCBA: 0x30 > FLMAP1: 0x09100206 > ISL: 0x09 > FPSBA: 0x100 > NM: 2 > FMBA: 0x60 > FLMAP2: 0x00210020 > PSL: 0x2100 > FMSBA: 0x200 > FLUMAP1: 0x000002e0 > Intel ME VSCC Table Length (VTL): 2 > Intel ME VSCC Table Base Address (VTBA): 0x000e00 > > ME VSCC table: > JID0: 0x001740ef > SPI Componend Device ID 1: 0x17 > SPI Componend Device ID 0: 0x40 > SPI Componend Vendor ID: 0xef > VSCC0: 0x20052005 > Lower Erase Opcode: 0x20 > Lower Write Enable on Write Status: 0x50 > Lower Write Status Required: No > Lower Write Granularity: 64 bytes > Lower Block / Sector Erase Size: 4KB > Upper Erase Opcode: 0x20 > Upper Write Enable on Write Status: 0x50 > Upper Write Status Required: No > Upper Write Granularity: 64 bytes > Upper Block / Sector Erase Size: 4KB > > OEM Section: > 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > Found Region Section > FLREG0: 0x000f0000 > Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff > FLREG1: 0x07ff0010 > Flash Region 1 (BIOS): 00010000 - 007fffff > FLREG2: 0x00000fff > Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) > FLREG3: 0x00000fff > Flash Region 3 (GbE): 00fff000 - 00000fff (unused) > FLREG4: 0x00000fff > Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) > > Found Component Section > FLCOMP 0x09200024 > Dual Output Fast Read Support: not supported > Read ID/Read Status Clock Frequency: 33MHz > Write/Erase Clock Frequency: 33MHz > Fast Read Clock Frequency: 33MHz > Fast Read Support: not supported > Read Clock Frequency: 20MHz > Component 2 Density: 8MB > Component 1 Density: 8MB > FLILL 0x00000000 > Invalid Instruction 3: 0x00 > Invalid Instruction 2: 0x00 > Invalid Instruction 1: 0x00 > Invalid Instruction 0: 0x00 > FLPB 0x00000000 > Flash Partition Boundary Address: 0x000000 > > Found PCH Strap Section > PCHSTRP0: 0x00080002 > PCHSTRP1: 0x00000000 > PCHSTRP2: 0x00000000 > PCHSTRP3: 0x00000003 > PCHSTRP4: 0x0000007f > PCHSTRP5: 0x007fffc0 > PCHSTRP6: 0x0001c7c0 > PCHSTRP7: 0x00000624 > PCHSTRP8: 0x00000000 > PCHSTRP9: 0xffffffff > PCHSTRP10: 0xffffffff > PCHSTRP11: 0xffffffff > PCHSTRP12: 0xffffffff > PCHSTRP13: 0xffffffff > PCHSTRP14: 0xffffffff > PCHSTRP15: 0xffffffff > PCHSTRP16: 0xffffffff > PCHSTRP17: 0xffffffff > > Found Master Section > FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) > Platform Data Region Write Access: enabled > GbE Region Write Access: enabled > Intel ME Region Write Access: enabled > Host CPU/BIOS Region Write Access: enabled > Flash Descriptor Write Access: enabled > Platform Data Region Read Access: enabled > GbE Region Read Access: enabled > Intel ME Region Read Access: enabled > Host CPU/BIOS Region Read Access: enabled > Flash Descriptor Read Access: enabled > Requester ID: 0x0000 > > FLMSTR2: 0x08090118 (Intel ME) > Platform Data Region Write Access: disabled > GbE Region Write Access: enabled > Intel ME Region Write Access: disabled > Host CPU/BIOS Region Write Access: disabled > Flash Descriptor Write Access: disabled > Platform Data Region Read Access: disabled > GbE Region Read Access: enabled > Intel ME Region Read Access: disabled > Host CPU/BIOS Region Read Access: disabled > Flash Descriptor Read Access: enabled > Requester ID: 0x0118 > > FLMSTR3: 0xffffffff (GbE) > Platform Data Region Write Access: enabled > GbE Region Write Access: enabled > Intel ME Region Write Access: enabled > Host CPU/BIOS Region Write Access: enabled > Flash Descriptor Write Access: enabled > Platform Data Region Read Access: enabled > GbE Region Read Access: enabled > Intel ME Region Read Access: enabled > Host CPU/BIOS Region Read Access: enabled > Flash Descriptor Read Access: enabled > Requester ID: 0xffff > > Found Processor Strap Section > ????: 0xffffffff > ????: 0xffffffff > ????: 0xffffffff > ????: 0xffffffff > > > But GbE is still de-activated. boot log is see below. > > > PCI: pci_scan_bus for bus 00 > PCI: 00:00.0 [8086/0000] ops > PCI: 00:00.0 [8086/1f0e] enabled > Capability: type 0x10 @ 0x40 > Capability: type 0x01 @ 0x80 > Capability: type 0x0d @ 0x88 > Capability: type 0x05 @ 0x90 > Capability: type 0x10 @ 0x40 > PCI: 00:01.0 subordinate bus PCI Express > PCI: 00:01.0 [8086/1f10] enabled > PCI: Static device PCI: 00:02.0 not found, disabling it. > Capability: type 0x10 @ 0x40 > Capability: type 0x01 @ 0x80 > Capability: type 0x0d @ 0x88 > Capability: type 0x05 @ 0x90 > Capability: type 0x10 @ 0x40 > PCI: 00:03.0 subordinate bus PCI Express > PCI: 00:03.0 [8086/1f12] enabled > PCI: Static device PCI: 00:04.0 not found, disabling it. > PCI: 00:0b.0 [8086/1f18] enabled > PCI: 00:0e.0 [8086/1f14] enabled > PCI: 00:0f.0 [8086/1f16] enabled > PCI: 00:13.0 [8086/1f15] enabled > * PCI: Static device PCI: 00:14.0 not found, disabling it.** > ** PCI: Static device PCI: 00:14.1 not found, disabling it.** > ** PCI: Static device PCI: 00:14.2 not found, disabling it.** > ** PCI: Static device PCI: 00:14.3 not found, disabling it*. > > > I don't have a any idea for activate the GbE. > > > Please advise to me. > > Thank you. > > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot > > >

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New on blogs.coreboot.org: [GSOC] Panic Room, week #3
by WordPress 21 Jun '16

21 Jun '16

1 0

Re: [coreboot] Where to find the coreboot_extra_version value
by Agrain Patrick 21 Jun '16

21 Jun '16

Hi, I reply to myself: '241' is also git stuff. It's the number of commit in this branch. Found the info after a 'man git-describe'. So please ignore this request. Best regards, Patrick Agrain -----Message d'origine----- De : Agrain Patrick Envoyé : mardi 21 juin 2016 14:47 À : 'coreboot(a)coreboot.org' Objet : Where to find the coreboot_extra_version value Hello, I would be interested to find out where the coreboot extra version is computed. Banner example: coreboot-4.4-241-g451b1e0-dirty-ALE-CPU8 Tue May 17 04:18:17 UTC 2016 ramstage starting... |------- From inside config file |------------- From git describe --dirty command |------------------- This also comes from git. |-------------------------- And this ???? Thanks. Best regards, Patrick Agrain

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How to obtain FSP v2.0 for ApolloLake?
by Rolf Evers-Fischer 21 Jun '16

21 Jun '16

Coreboot for Intel ApolloLake needs FSP v2.0 blobs. Unfortunately FSP v2.0 is not offered at www.intel.com/fsp. Do you know, how or where I could get it? Kind regards, Rolf

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Where to find the coreboot_extra_version value
by Agrain Patrick 21 Jun '16

21 Jun '16

Hello, I would be interested to find out where the coreboot extra version is computed. Banner example: coreboot-4.4-241-g451b1e0-dirty-ALE-CPU8 Tue May 17 04:18:17 UTC 2016 ramstage starting... |------- From inside config file |------------- From git describe --dirty command |------------------- This also comes from git. |-------------------------- And this ???? Thanks. Best regards, Patrick Agrain

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Re: [coreboot] fmaptool: fmap_config.h: Base offset missing
by Rolf Evers-Fischer 21 Jun '16

21 Jun '16

On Mon, 20 Jun 2016, Julius Werner wrote: > Yes, this definitely looks like a bug... thanks a lot for reporting > it. The fix is simple and I've uploaded it here: > https://review.coreboot.org/15273 > Thank you for this commit. I've just tested it - and now it works correctly. > I'm curious why this hasn't been noticed anywhere before, though... > (on some boards this just happens to work out because the parent > section of COREBOOT starts at offset 0 anyway, but on others as you > found out it doesn't). > I don't know either. Let's hope that this commit doesn't break any of the other boards. But in my opinion the behaviour is now correct. > On Thu, Jun 16, 2016 at 6:55 AM, Rolf Evers-Fischer > <embedded24(a)evers-fischer.de> wrote: > > Hello, > > my ApolloLake board was not able to find the "romstage" in the SPI memory, > > because it searched in the wrong part of the memory. > > > > ___FMAP__COREBOOT_BASE was set to the relative offset within the parent > > section, but rdev_readat needs the *absolute* address: There was a > > mismatch. > > However, I was able to fix this problem locally by adding an additional > > fixed offset to fmap_top, like > > > > diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c > > index aa652c2..f36a499 100644 > > --- a/src/lib/cbfs.c > > +++ b/src/lib/cbfs.c > > @@ -230,7 +230,7 @@ static int cbfs_master_header_props(struct cbfs_props *props > > if (bdev == NULL) > > return -1; > > > > - size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; > > + size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE + 0x300000; > > > > /* Find location of header using signed 32-bit offset from > > * end of CBFS region. */ > > > > > > But imho this shouldn't be a permanent solution! > > > > Therefore I suggest to modify the 'fmaptool' in such way that it outputs > > the absolute address for (at least) ___FMAP__COREBOOT_BASE, because the > > 'rdev_readat()' function of the 'boot_device_ro()' needs it in this form. > > > > What is your opinion? > > > > Kind regards, > > Rolf > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://www.coreboot.org/mailman/listinfo/coreboot >

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