coreboot July 2015

coreboot@coreboot.org

46 participants
98 discussions

Fwd: build coreboot for Braswell soc
by Patrick Georgi 08 Jul '15

08 Jul '15

2015-07-08 15:00 GMT+02:00 philby john <philbyjohn(a)gmail.com>: > But looking at > src/Kconfig I realize none of the soc code (baytrail, braswell, broadwell) > can be compiled because the path to respective Kconfig soc's (source > "src/soc/*/*/Kconfig") have not been defined. I don't understand what you're saying here. Kconfig includes all src/soc/*/*/Kconfig in src/Kconfig, line 375. The build system includes all src/soc/*/*/Makefile.inc in Makefile.inc, line 57. What's missing? > Also the qa build environment at qa.coreboot.org does not seem to build for Braswell. That's because there is no board using Braswell in the repository. (git grep SOC_INTEL_BRASWELL src/mainboard doesn't return anything) Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores

1 0

Hudson-D4 (A88X): IRQ routing of XHCI seems incomplete?
by Idwer Vollering 08 Jul '15

08 Jul '15

Board: asus/f2a85-m In "AMD Bolton FCH Register Reference Guide" (51192), page 2-154, this register "Interrupt Line – RW – 32 bits - [PCI_Reg:3Ch]" is 0x12/0x11 while having booted the vendor binary and 0xff/0xff when having booted coreboot. Could the erratic value cause SeaBIOS boot issues? See http://www.coreboot.org/pipermail/seabios/2014-June/008148.html and http://www.coreboot.org/pipermail/seabios/2014-June/008150.html lspci -s 10.{0,1} -nnvvvxx output follows. vendor binary: 00:10.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8527] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at fef4a000 (64-bit, non-prefetchable) Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+ Address: 00000000fee13000 Data: 0031 Capabilities: [90] MSI-X: Enable- Count=8 Masked- Vector table: BAR=0 offset=00001000 PBA: BAR=0 offset=00001080 Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+, OBFF Not Supported DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled 00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 80 00 10: 04 a0 f4 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85 30: 00 00 00 00 50 00 00 00 00 00 00 00 12 01 00 00 40: 00 00 00 00 00 00 00 00 88 00 00 00 08 77 76 76 50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 05 90 87 00 00 30 e1 fe 00 00 00 00 31 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00 a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00:10.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8527] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at fef48000 (64-bit, non-prefetchable) Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+ Address: 00000000fee10000 Data: 0034 Capabilities: [90] MSI-X: Enable- Count=8 Masked- Vector table: BAR=0 offset=00001000 PBA: BAR=0 offset=00001080 Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+, OBFF Not Supported DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled 00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 00 00 10: 04 80 f4 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85 30: 00 00 00 00 50 00 00 00 00 00 00 00 11 02 00 00 40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 66 00 50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 05 90 87 00 00 00 e1 fe 00 00 00 00 34 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00 a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00 coreboot: 00:10.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller [1022:7812] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 255 Region 0: Memory at f0148000 (64-bit, non-prefetchable) Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+ Address: 00000000fee10000 Data: 0033 Capabilities: [90] MSI-X: Enable- Count=8 Masked- Vector table: BAR=0 offset=00001000 PBA: BAR=0 offset=00001080 Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+, OBFF Not Supported DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled 00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 80 00 10: 04 80 14 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 12 78 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 ff 00 50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 05 90 87 00 00 00 e1 fe 00 00 00 00 33 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00 a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00:10.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller [1022:7812] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 255 Region 0: Memory at f014a000 (64-bit, non-prefetchable) Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+ Address: 00000000fee11000 Data: 0032 Capabilities: [90] MSI-X: Enable- Count=8 Masked- Vector table: BAR=0 offset=00001000 PBA: BAR=0 offset=00001080 Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+, OBFF Not Supported DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled 00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 00 00 10: 04 a0 14 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 12 78 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 02 00 00 40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 ff 00 50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 05 90 87 00 00 10 e1 fe 00 00 00 00 32 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00 a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00

1 0

build coreboot for Braswell soc
by philby john 08 Jul '15

08 Jul '15

Hello, My intention is to build coreboot for the Braswell soc. But looking at src/Kconfig I realize none of the soc code (baytrail, braswell, broadwell) can be compiled because the path to respective Kconfig soc's (source "src/soc/*/*/Kconfig") have not been defined. Also the qa build environment at qa.coreboot.org does not seem to build for Braswell. Can someone please guide me on the procedure to compile the Braswell SoC platform? Thanks and regards, Philby

1 0

Kernel couldn't find proper MAC address with coreboot (gigabyte ma785gmt-ud2h)
by YongGon Kim 08 Jul '15

08 Jul '15

I have used coreboot and successfully boot ubuntu 14.04 (only console mode). But kernel couldn't find proper MAC address and only ff:ff:ff:ff:ff:ff is printed. When kernel is booted, r8169 module is successfully loaded but it failed to find proper MAC address with following messages. [ 1.165748] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded [ 1.165850] r8169 0000:04:00.0: can't disable ASPM; OS doesn't have ASPM control [ 1.166010] r8169 0000:04:00.0 (unregistered net_device): unknown MAC, using family default [ 1.176236] r8169 0000:04:00.0 (unregistered net_device): rtl_chipcmd_cond == 1 (loop: 100, delay: 100). [ 1.176448] r8169 0000:04:00.0: irq 43 for MSI/MSI-X [ 1.176609] r8169 0000:04:00.0 eth0: RTL8168b/8111b at 0xffffc900003ac000, ff:ff:ff:ff:ff:ff, XID 9cf0f8ff IRQ 43 [ 1.176732] r8169 0000:04:00.0 eth0: jumbo features [frames: 4080 bytes, tx checksumming: ko] I found that, with normal BIOS, MAC address are located within PCI I/O memory space pointed by 2nd base address register of ethernet PCI device. But with coreboot, memory space pointed by 2nd BAR of ethernet device only contains 0xff. I tried to figure out how PCI I/O memory space is initialized and allocated, but i'm stuck now and need some helps. I only found some hints in kernel log that following messages are only shown with coreboot booting for ethernet pci device. ... [ 0.120164] pci 0000:04:00.0: no compatible bridge window for [mem 0xc8010000-0xc8010fff 64bit pref] [ 0.120164] pci 0000:04:00.0: no compatible bridge window for [mem 0xc8000000-0xc800ffff 64bit pref] ... [ 0.271531] pci 0000:04:00.0: BAR 4: can't assign mem pref (size 0x10000) [ 0.271620] pci 0000:04:00.0: BAR 4: trying firmware assignment [mem 0xc8000000-0xc800ffff 64bit pref] [ 0.271724] pci 0000:04:00.0: BAR 4: assigned [mem 0xc8000000-0xc800ffff 64bit pref] ... Is there anyone who knows how to handle this situation? It's okay for me to update kernel source (e.g. r8169 module) instead of coreboot source code. I just want to know what the problem is and any possible way to resolve it. I'm using GIGABYTE GA-MA785GMT-UD2H (rev 1.1) with external graphic card (nvida GTS 250). I have uploaded detailed information using board_status.sh Following is link for the information. http://review.coreboot.org/gitweb?p=board-status.git;a=commit;h=dedf456d257… Thank you.

1 0

ASUS KFSN4-DRE Automated Test Failure
by Raptor Engineering Automated Coreboot Test Stand 08 Jul '15

08 Jul '15

The ASUS KFSN4-DRE fails verification as of commit 2941b28080fff82503484a99c3fa740a01bb30cc The following tests failed: BOOT_FAILURE Commits since last successful test: 2941b28 toolchain.inc: Don't overwrite architecture specific CFLAGS 8e39975 memlayout: Add timestamp regions for t210 and cygnus See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

1 0

minnowboardmax coreboot intel uefi payload :Failed to find the required acpi table
by DM365 07 Jul '15

07 Jul '15

Hello! I tested intel uefi payload instead of seabios in coreboot minnowboard max . It failed with "Failed to find the required acpi table ". If I use seabios payload ,the bios runs ok! I followed "http://www.elinux.org/Minnowboard:MinnowMaxCoreboot" to build coreboot. I used "https://firmware.intel.com/develop/" 2014-WW26-UEFI.coreboot.Payload.zip to builed uefi in coreboot. The whole terminal log is : POST: 0x4a POST: 0x4b POST: 0x4c POST: 0x4d POST: 0x4e POST: 0x4f POST: 0x39 POST: 0x80 POST: 0x70 POST: 0x71 POST: 0x72 POST: 0x24 POST: 0x25 POST: 0x24 POST: 0x25 POST: 0x55 POST: 0x24 POST: 0x25 POST: 0x55 POST: 0x55 POST: 0x73 APIC: 00 missing read_resources PCI: 00:00.0 missing set_resources POST: 0x74 POST: 0x75 POST: 0x75 POST: 0x93 POST: 0x9b POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Warning: PCI Device 2 does not have an IRQ entry, skipping it POST: 0x75 POST: 0x75 POST: 0x76 POST: 0x77 find_current_mrc_cache_local: No valid fast boot cache found. POST: 0x79 POST: 0x9c POST: 0x9e POST: 0x9d POST: 0x7a POST: 0x7b POST: 0xf8 PROGRESS CODE: V03020003 I0 Loading PEIM at 0x0000080EC20 EntryPoint=0x0000080EE80 CbSupportPeim.efi PROGRESS CODE: V03020002 I0 0. 0000000000000000 - 0000000000000FFF [10] 1. 0000000000001000 - 000000000009FFFF [01] 2. 00000000000A0000 - 00000000000FFFFF [02] 3. 0000000000100000 - 000000007ACBCFFF [01] 4. 000000007ACBD000 - 000000007ADFFFFF [10] 5. 000000007AE00000 - 000000007FFFFFFF [02] 6. 00000000E0000000 - 00000000EFFFFFFF [02] 7. 00000000FEB00000 - 00000000FEC00FFF [02] 8. 00000000FED01000 - 00000000FED01FFF [02] 9. 00000000FED03000 - 00000000FED03FFF [02] 10. 00000000FED05000 - 00000000FED05FFF [02] 11. 00000000FED08000 - 00000000FED08FFF [02] 12. 00000000FED0C000 - 00000000FED0FFFF [02] 13. 00000000FED1C000 - 00000000FED1CFFF [02] 14. 00000000FEE00000 - 00000000FEE00FFF [02] 15. 00000000FEF00000 - 00000000FEFFFFFF [02] 16. 00000000FF800000 - 00000000FFFFFFFF [02] Low memory 0x7ACBD000, High Memory 0x0 LowMemorySize: 0x7ACBD000. HighMemorySize: 0x0. PeiMemBase: 0x76CB0000. PeiMemSize: 0x4000000. PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000 Found one valid fv : 0x820000. Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 801BC0 The 1th FV start address is 0x00000820000, size is 0x003E0000, handle is 0x820000 Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410 Actual Coreboot header: 0x7ACBD000. Failed to find the required acpi table PEI_ASSERT!: d:\myworkspace\CorebootModulePkg\CbSupportPei\CbSupportPei.c (338): ((BOOLEAN)(0==1))

2 1

Re: [coreboot] ACPI resource problem
by WANG FEI 07 Jul '15

07 Jul '15

Siyuan, did you reserved 0xFEDC2000 - 0xFEDC2FFF in ASL file? what you've done in your code is to reserve this MMIO area in E820 table, OS will not take this area, but it's not enough for ACPI. Here is a sample to reserve MMIO area in asl file. // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, 0x00005000,,, TPMR) On Mon, Jul 6, 2015 at 12:31 PM, WANG Siyuan <wangsiyuanbuaa(a)gmail.com> wrote: > Hi, > I have a question about acpi resource. > > My device need the resource: > Name(_CRS, ResourceTemplate() { > IRQ(Edge, ActiveHigh, Exclusive) {3} > Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) > }) > In Win8's device manager, I got error "This device cannot find enough free > resources that it can use." > > I reserve resource (0xFEDC2000 - 0xFEDC2FFF) using flag resource->flags = > IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED > | IORESOURCE_ASSIGNED; I still got this error. > > I have 2 questions: > 1) Do I need to reserve MMIO for (0xFEDC2000 - 0xFEDC2FFF)? > 2) Do I need to do some thing for IRQ(Edge, ActiveHigh, Exclusive) {3}? > > Any replay is appreciated! > > Yours sincerely, > WANG Siyuan > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

1 0

Re: [coreboot] How to build SPI ROM 8MB image
by WANG FEI 07 Jul '15

07 Jul '15

Update BOARD_ROMSIZE_KB_2048 in src\mainboard\intel\bayleybay_fsp\Kconfig to BOARD_ROMSIZE_KB_8192, re-generate .config and make sure .config the ROM size is 8MB, now you can run make to generate 8MB ROM. On Tue, Jul 7, 2015 at 10:32 AM, Cao Duc Quan <caoducquan(a)gmail.com> wrote: > Dear all, > I am trying to make coreboot work on BayTrail-I SoC E3845. > I wonder if anyone could build the SPI ROM 8MB image with coreboot? I > found that I got 2MB image with normal building so I have to flash two > times SPI.rom first then flash coreboot.rom. > > Many Thanks, > -- > Quan Cao > 0976574864 > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

1 0

How to build SPI ROM 8MB image
by Cao Duc Quan 07 Jul '15

07 Jul '15

Dear all, I am trying to make coreboot work on BayTrail-I SoC E3845. I wonder if anyone could build the SPI ROM 8MB image with coreboot? I found that I got 2MB image with normal building so I have to flash two times SPI.rom first then flash coreboot.rom. Many Thanks, -- Quan Cao 0976574864

1 0

HEADS UP: Bug in automatic testing on gerrit/jenkins
by Patrick Georgi 06 Jul '15

06 Jul '15

Hi all, today I noticed that our test builders at http://qa.coreboot.org/ weren't actually testing the commits that are pending review on http://review.coreboot.org/ as they were asked to, but (most of the time) a commit from early-June. We fixed the issue (Jenkins, the tool that orchestrates qa.coreboot.org, dropped some configuration value during an update that we needed to set again), but unfortunately some commits sneaked in that broke the tree. Fixes for these bugs are in, but when pushing changes for code review, the builders may still report errors that are unrelated to your change. See http://qa.coreboot.org/job/coreboot-gerrit/27371/ for an example. That's because the builders use exactly the commit you pushed, without applying any new changes to it. If you run into that situation, please rebase your commits to the current master, since (as of a couple of minutes ago) it includes the bug fixes. $ git pull $ git rebase master $your_local_branch $ git push (as usual) Sorry for the inconvenience, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores

1 0

← Newer
1
2
3
4
5
6
7
8
9
10
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot July 2015