coreboot July 2015

coreboot@coreboot.org

46 participants
98 discussions

ACPI resource problem
by WANG Siyuan 06 Jul '15

06 Jul '15

Hi, I have a question about acpi resource. My device need the resource: Name(_CRS, ResourceTemplate() { IRQ(Edge, ActiveHigh, Exclusive) {3} Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) }) In Win8's device manager, I got error "This device cannot find enough free resources that it can use." I reserve resource (0xFEDC2000 - 0xFEDC2FFF) using flag resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; I still got this error. I have 2 questions: 1) Do I need to reserve MMIO for (0xFEDC2000 - 0xFEDC2FFF)? 2) Do I need to do some thing for IRQ(Edge, ActiveHigh, Exclusive) {3}? Any replay is appreciated! Yours sincerely, WANG Siyuan

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minnowboardmax coreboot intel uefi payload :Failed to find the required acpi table
by DM365 06 Jul '15

06 Jul '15

Hello! I tested intel uefi payload instead of seabios in coreboot minnowboard max . It failed with "Failed to find the required acpi table ". If I use seabios payload ,the bios runs ok! I followed "http://www.elinux.org/Minnowboard:MinnowMaxCoreboot" to build coreboot. I used "https://firmware.intel.com/develop/" 2014-WW26-UEFI.coreboot.Payload.zip to builed uefi in coreboot. The whole terminal log is : POST: 0x4a POST: 0x4b POST: 0x4c POST: 0x4d POST: 0x4e POST: 0x4f POST: 0x39 POST: 0x80 POST: 0x70 POST: 0x71 POST: 0x72 POST: 0x24 POST: 0x25 POST: 0x24 POST: 0x25 POST: 0x55 POST: 0x24 POST: 0x25 POST: 0x55 POST: 0x55 POST: 0x73 APIC: 00 missing read_resources PCI: 00:00.0 missing set_resources POST: 0x74 POST: 0x75 POST: 0x75 POST: 0x93 POST: 0x9b POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Warning: PCI Device 2 does not have an IRQ entry, skipping it POST: 0x75 POST: 0x75 POST: 0x76 POST: 0x77 find_current_mrc_cache_local: No valid fast boot cache found. POST: 0x79 POST: 0x9c POST: 0x9e POST: 0x9d POST: 0x7a POST: 0x7b POST: 0xf8 PROGRESS CODE: V03020003 I0 Loading PEIM at 0x0000080EC20 EntryPoint=0x0000080EE80 CbSupportPeim.efi PROGRESS CODE: V03020002 I0 0. 0000000000000000 - 0000000000000FFF [10] 1. 0000000000001000 - 000000000009FFFF [01] 2. 00000000000A0000 - 00000000000FFFFF [02] 3. 0000000000100000 - 000000007ACBCFFF [01] 4. 000000007ACBD000 - 000000007ADFFFFF [10] 5. 000000007AE00000 - 000000007FFFFFFF [02] 6. 00000000E0000000 - 00000000EFFFFFFF [02] 7. 00000000FEB00000 - 00000000FEC00FFF [02] 8. 00000000FED01000 - 00000000FED01FFF [02] 9. 00000000FED03000 - 00000000FED03FFF [02] 10. 00000000FED05000 - 00000000FED05FFF [02] 11. 00000000FED08000 - 00000000FED08FFF [02] 12. 00000000FED0C000 - 00000000FED0FFFF [02] 13. 00000000FED1C000 - 00000000FED1CFFF [02] 14. 00000000FEE00000 - 00000000FEE00FFF [02] 15. 00000000FEF00000 - 00000000FEFFFFFF [02] 16. 00000000FF800000 - 00000000FFFFFFFF [02] Low memory 0x7ACBD000, High Memory 0x0 LowMemorySize: 0x7ACBD000. HighMemorySize: 0x0. PeiMemBase: 0x76CB0000. PeiMemSize: 0x4000000. PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000 Found one valid fv : 0x820000. Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 801BC0 The 1th FV start address is 0x00000820000, size is 0x003E0000, handle is 0x820000 Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410 Actual Coreboot header: 0x7ACBD000. Failed to find the required acpi table PEI_ASSERT!: d:\myworkspace\CorebootModulePkg\CbSupportPei\CbSupportPei.c (338): ((BOOLEAN)(0==1))

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New on blogs.coreboot.org: [GSoC] EC/H8S firmware week #5
by WordPress 06 Jul '15

06 Jul '15

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Re: [coreboot] About coreboot
by ron minnich 03 Jul '15

03 Jul '15

Coreboot is written in C and assembly, with very little assembly. Your best bet is to build the QEMU target first and just learn how to build, boot, and change it. ron On Fri, Jul 3, 2015 at 12:36 PM francisco dominguez < francisco.dominguez.lerma2(a)gmail.com> wrote: > Hi, I'm new, I would like to help develop coreboot is C, I am interested to > collaborate because I like to learn more about C and take the chance to > help this fantastic community. > > What language is written coreboot? > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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About coreboot
by francisco dominguez 03 Jul '15

03 Jul '15

Hi, I'm new, I would like to help develop coreboot is C, I am interested to collaborate because I like to learn more about C and take the chance to help this fantastic community. What language is written coreboot?

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Looking for Broadwell board for coreboot build
by Adam Duncan 03 Jul '15

03 Jul '15

Hi, I'm looking for a board with an Intel broadwell on it that I can get a coreboot build going for. Do you have any recommendations? Are there any commercial boards with the broadwell that are currently supported? If not, do you know which boards would be the easiest to focus on?

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Recommended broadwell board w coreboot support
by Adam Duncan 03 Jul '15

03 Jul '15

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Question about making Qemu diskimg
by Yu-Cheng Liu 03 Jul '15

03 Jul '15

Hello I have some questions about making Qemu disk image. 1. In QEMU_Build_Tutorial ,one step is to copy root file system to the diskimg "* # cp -R /* /mnt/rootfs *",I what know what files are necessary ?(I don't want put all of it,it might be too large) 2. Is it necessary to put Debian in diskimg? 3. I can't figure out this situation : I can't successfully boot my disk image ,but can boot by QEMU download image,so I try to create a empty disk image , format it as (EXT2/EXT3/EXT4). mount QEMU download image and copy all of files into my image mount's directory.Boot my disk image again,and It does't work.What's wrong with my idea?I thought change my image contents to download's and it can be work.It seems not. thank for your help~

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rtc migrations / century byte used
by Alexander Couzens 03 Jul '15

03 Jul '15

Hi, I mentioned some problems while debugging windows on a x201. Also linux throw a warning with the RTC, but it could recover the correct time. coreboot multiple use of one nvram byte on lots of boards. On most board 0x32/b400 is used by some nvram settings as well as the OS interprets the time (century) from the same byte. The century byte saves the century in bcd format. The default location is 0x32 / b400. find src/mainboard/ -iname cmos.layout | xargs grep -h '^400' | sort | uniq -c 112 400 1 e 1 power_on_after_fail 33 400 1 e 2 hyper_threading 1 400 8 h 0 century 9 400 8 h 0 volume 1 400 8 r 0 stumpy_usb_reset_disable 2 400 8 h 0 volume # 37 boards can be removed from this list, because they disabled the century byte in facp. This leads to 3 topic: * how can we change cmos.layout in a way no or less settings gets lost? e.g. add a version field and a way to migrate these. or do we ignore the loss of data? * do we want to support the century byte? * how do we fix the multiusage, because it makes problems atm. best lynxis -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)jabber.ccc.de mobile: +4915123277221

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CBMEM console deactivated in coreboot and activated SeaBIOS
by Paul Menzel 02 Jul '15

02 Jul '15

Dear coreboot folks, if the CBMEM console is disabled in coreboot and only enabled in SeaBIOS, currently SeaBIOS does not write any messages to the CBMEM console (SeaBIOS commit f24eb2f85 (build: CONFIG_VGA_FIXUP_ASM should depend on CONFIG_BUILD_VGABIOS)). $ more src/fw/coreboot.c […] struct cb_cbmem_ref *cbref = find_cb_subtable(cbh, CB_TAG_CBMEM_CONSOLE); if (cbref) { cbcon = (void*)(u32)cbref->cbmem_addr; debug_banner(); dprintf(1, "Found coreboot cbmem console @ %llx\n", cbref->cbmem_addr); } […] Does the CBMEM specification(?) allow to add the CBMEM console section(?) – CB_TAG_CBMEM_CONSOLE 0x17 – after coreboot has run? If yes, I could try to adapt SeaBIOS to do just that in case coreboot does not set it up. Thanks, Paul

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coreboot July 2015