coreboot July 2015

coreboot@coreboot.org

46 participants
98 discussions

ANN: Test builder change
by Patrick Georgi 31 Jul '15

31 Jul '15

Hi all, I just changed the "coreboot" builder on http://qa.coreboot.org/ to use the just fixed "what-jenkins-does" build target (defined in $(top)/Makefile.inc), so all future builds will use that instead of the hard coded sequence of commands that used to be defined in our build environment. I plan to move the "coreboot-gerrit" builder over in about a week. This means that from that point on, contributions on gerrit that predate the inclusion of http://review.coreboot.org/#/c/11097/ will break. Therefore if you have long-running development branches, please remember to rebase them to a current upstream or you'll get a build error after pushing them. Thanks, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores

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Re: [coreboot] Suggestion about motherboard that implement coreboot ?
by Marc Jones 30 Jul '15

30 Jul '15

Hi, I recommend that you read the smi section of the datasheet for your specific cpu/chipset and learn how that works and how you can trigger an smi. Regards, Marc On Thu, Jul 30, 2015, 2:47 AM Yu-Cheng Liu <peter90609(a)gmail.com> wrote: > hello, > I want to trigger the SMI/SMM in the coreboot,and burn it on the > motherboard > what kind of motherboard is suggest to use? > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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coreboot conference in Europe, October 2015
by Carl-Daniel Hailfinger 30 Jul '15

30 Jul '15

Dear coreboot developers, users and interested parties, we are currently trying to organize a coreboot conference and developer meeting in October 2015 in Germany. This is not intended to be a pure developer meeting, we also hope to reach out to manufacturers of processors, chipsets, mainboards and servers/laptops/tablets/desktops with an interest in coreboot and the possibilities it offers. My plan (which is not final yet) is to have the Federal Office for Information Security (BSI) in Germany host the conference in Bonn, Germany. As a national cyber security authority, the goal of the BSI is to promote IT security in Germany. For this reason, the BSI has funded coreboot development in the past for security reasons. The preliminary plans are to coordinate the exact date of the conference to be before or after Embedded Linux Conference Europe, scheduled for October 5-7 in Dublin, Ireland. Planned duration is 3-4 days. This means we can either use the time window from Thursday Oct 1 to Sunday Oct 4, or from Thursday Oct 8 to Monday Oct 12. The former has the advantage of having cheaper hotel rooms available in Bonn, while the latter has the advantage of avoiding Oct 3, a national holiday in Germany (all shops closed). ATTENTION vendors/manufacturers: If your main interest is forging business relationships and/or strategic coordination and you want to skip the technical workshops and soldering, we'll try make sure there is one outreach day of talks, presentations and discussions on a regular business day. Please indicate that with "(strategic)" next to your name in the doodle linked below. If you wonder about how to reach Bonn, there are three options available by plane: The closest is Cologne Airport (CGN), 30 minutes by bus to Bonn main station. Next is Düsseldorf Airport (DUS), 1 hour by train to Bonn main station. The airport with most international destinations is Frankfurt Airport (FRA), 2.5 hours by train to Bonn main station. There's the option to travel by train as well. Bonn is reachable by high-speed train (ICE), and other high-speed train stations are reasonably close (30 minutes). What I'm looking for right now is a rough show of hands who'd like to attend so I can book a conference venue. I'd also like feedback on which weekend would be preferable for you. If you have any questions, please feel free to ask me directly <c-d.hailfinger.devel.2006(a)gmx.net> or our mailing list <coreboot(a)coreboot.org>. Please enter your participation abilities in the doodle below: http://doodle.com/bw52xs4fc7pxte6d Regards, Carl-Daniel Hailfinger

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Dead links - missing information?
by Karl Schmidt 29 Jul '15

29 Jul '15

This page has several dead links and I was unable to find a single coreboot server motherboard for sale after following the links. http://www.coreboot.org/Products I think I understand why this is happening. -- -------------------------------------------------------------------------------- Link to our website and get free US-48 shipping on your next order. Karl Schmidt EMail Karl(a)xtronics.com Transtronics, Inc. WEB https://secure.transtronics.com 3209 West 9th Street Ph (785) 841-3089 Lawrence, KS 66049 FAX (785) 841-3089 The men the American people admire most extravagantly are the greatest liars: the men they detest most violently are those who try to tell them the truth.” H.L. Mencken --------------------------------------------------------------------------------

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coreboot changelog - Week of 2015-07-20
by Patrick Georgi 29 Jul '15

29 Jul '15

(This covers commits 406effd5 up to commit ef0158ec) Apart from adding the google/glados board, this week’s activity concentrated on bug fixes in chipsets and mainboards, spanning AMD K8 and Hudson, Intel Sandy Bridge, Braswell and Skylake, Nvidia Tegra, Rockchip RK3288 and RISC-V. Most of the changes are too small individually and too spread out across the code base for a shout-out (or this report becomes just a fancy kind of “git log”), but two changes stand out: Native RAM init on Sandybridge gained support for multiple DIMMs on the same channel, further improving the reverse engineered code base for that chipset. To improve Skylake support, our 8250mem serial port driver now also supports Skylake's 32bit UART access mode. This may also be useful when reducing code duplication in our serial console drivers (such as on ARM SoCs). Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores

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New on blogs.coreboot.org: coreboot changelog - Week of 2015-07-20
by WordPress 29 Jul '15

29 Jul '15

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Suggestion about motherboard that implement coreboot ?
by Yu-Cheng Liu 29 Jul '15

29 Jul '15

hello, I want to trigger the SMI/SMM in the coreboot,and burn it on the motherboard what kind of motherboard is suggest to use?

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New on blogs.coreboot.org: [GSoC] EC/H8S firmware week #7|#8
by WordPress 29 Jul '15

29 Jul '15

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New on blogs.coreboot.org: [GSoC] coreboot for ARM64 Qemu – Week #7
by WordPress 28 Jul '15

28 Jul '15

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coreboot for vexpress-v9 qemu failed
by Iru Cai 28 Jul '15

28 Jul '15

Hi, I am using QEMU from Arch Linux x86_64 official repo. I need to test my built u-boot payload, so I tried to build a QEMU ARM coreboot image. However, it failed to run and had the following output. qemu: fatal: Trying to execute code outside RAM or ROM at 0xfffffffe R00=00000000 R01=00011b70 R02=00000000 R03=ffffffff R04=00c51878 R05=00000147 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000002 R13=000fffd8 R14=ffffffff R15=fffffffe PSR=600000ff -ZC- T sys32 s00=00000000 s01=00000000 d00=0000000000000000 s02=00000000 s03=00000000 d01=0000000000000000 s04=00000000 s05=00000000 d02=0000000000000000 s06=00000000 s07=00000000 d03=0000000000000000 s08=00000000 s09=00000000 d04=0000000000000000 s10=00000000 s11=00000000 d05=0000000000000000 s12=00000000 s13=00000000 d06=0000000000000000 s14=00000000 s15=00000000 d07=0000000000000000 s16=00000000 s17=00000000 d08=0000000000000000 s18=00000000 s19=00000000 d09=0000000000000000 s20=00000000 s21=00000000 d10=0000000000000000 s22=00000000 s23=00000000 d11=0000000000000000 s24=00000000 s25=00000000 d12=0000000000000000 s26=00000000 s27=00000000 d13=0000000000000000 s28=00000000 s29=00000000 d14=0000000000000000 s30=00000000 s31=00000000 d15=0000000000000000 s32=00000000 s33=00000000 d16=0000000000000000 s34=00000000 s35=00000000 d17=0000000000000000 s36=00000000 s37=00000000 d18=0000000000000000 s38=00000000 s39=00000000 d19=0000000000000000 s40=00000000 s41=00000000 d20=0000000000000000 s42=00000000 s43=00000000 d21=0000000000000000 s44=00000000 s45=00000000 d22=0000000000000000 s46=00000000 s47=00000000 d23=0000000000000000 s48=00000000 s49=00000000 d24=0000000000000000 s50=00000000 s51=00000000 d25=0000000000000000 s52=00000000 s53=00000000 d26=0000000000000000 s54=00000000 s55=00000000 d27=0000000000000000 s56=00000000 s57=00000000 d28=0000000000000000 s58=00000000 s59=00000000 d29=0000000000000000 s60=00000000 s61=00000000 d30=0000000000000000 s62=00000000 s63=00000000 d31=0000000000000000 FPSCR: 00000000 After I add '-S -s' option to QEMU, I found the problem is in bootblock_simple.c, and the `main()' function in gdb is: 0x00000192 in ?? () => 0x00000192: 08 b5 push {r3, lr} (gdb) disas $pc,+50 Dump of assembler code from 0x192 to 0x1c4: => 0x00000192: push {r3, lr} 0x00000194: bl 0x1704 0x00000198: bl 0x18c 0x0000019c: bl 0xd10 0x000001a0: bl 0x634 0x000001a4: bl 0x18e 0x000001a8: bl 0x190 0x000001ac: ldmia.w sp!, {r3, lr} 0x000001b0: b.w 0x159c 0x000001b4: push {r3, lr} 0x000001b6: mrc 15, 0, r3, cr1, cr0, {0} 0x000001ba: lsls r2, r3, #29 0x000001bc: bpl.n 0x1c4 0x000001be: bl 0x2ac 0x000001c2: b.n 0x1cc End of assembler dump. (gdb) si 0x00000194 in ?? () => 0x00000194: 01 f0 b6 fa bl 0x1704 (gdb) b *0x198 Breakpoint 3 at 0x198 (gdb) c Continuing. Breakpoint 3, 0x00000198 in ?? () => 0x00000198: ff f7 f8 ff bl 0x18c (gdb) b *0x19c Breakpoint 4 at 0x19c (gdb) c Continuing. Breakpoint 4, 0x0000019c in ?? () => 0x0000019c: 00 f0 b8 fd bl 0xd10 (gdb) b *0x1a0 Breakpoint 5 at 0x1a0 (gdb) c Continuing. Remote connection closed So there may be something wrong when setting up the console, however I'm not so familiar with debugging the ROM so I don't know which function call raise the problem. Thanks, Iru

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coreboot July 2015