coreboot March 2015

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ASUS F2A85-M PRO
by David Englund 07 Mar '15

07 Mar '15

Is this board supported?

3 5

Re: [coreboot] Bare metal hello world rs232 payload
by Adam Duncan 07 Mar '15

07 Mar '15

Thanks Marc, Can I use libpayload to make a payload for a 64 bit ROM? I'm following the coreboot minnowboard max 64bit instructions below and substituting the default payload for the payloadlib sample hello world payload. http://elinux.org/Minnowboard:MinnowMaxCoreboot Also, is there a lower level method than using payloadlib to make a simple coreboot payload elf that just initializes rs232 and prints a string over rs232? Any good low level documentation you would recommend for understanding how a payload needs to initialize rs232 and prints a string? Thanks again! Adam Hi Adam On Sat, Mar 7, 2015 at 5:46 AM Adam Duncan <adam.duncan(a)gmail.com> wrote: > Hi all. I am new to coreboot and just built a default coreboot+seabios ROM > and ran it on a 64bit minnowboard max. Now I'd like to build a simple hello > world payload elf that would simply print a string on rs232. > > Can you recommend the best approach to do this? I was looking at using > libpayload but read in the README that it creates 32 bit elfs. > Libpayload is exactly what you want to use to make a simple hello world. The processor is in 32bit mode and can run 32bit code, if that is your concern. Regards, Marc > Thanks! > Adam > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] [GSoC-2015] Interested in Participating - Discussing Ideas
by Varad Gautam 07 Mar '15

07 Mar '15

Hi Marc, On 03/06/15 at 06:26 PM Marc Jones <marcj303(a)gmail.com> wrote: > Hi Varad, > > Welcome! It is great to hear that you are interested in coreboot GSoC. > > On Thu, Mar 5, 2015 at 8:44 AM Varad Gautam <varadgautam(a)gmail.com> wrote: > > Hi, > > > > I would like to participate in Google Summer of Code 2015 with coreboot to > > work on one of the following ideas: > > > > - Enable coreboot + Tianocore over an ARM board: The Ideas page mentions > > something similar [1], but I think the hardware details are to be > > finalized. I > > worked on adding BeagleBone Black support to Tianocore during GSoC-2014 > > with > > Linaro, and so have some experience with JTAG, ARM bringup and > > bootloaders. > > Which mainboard would be the intended target? I have a HiKey board > > (HiSilicon > > Kirin 6220 Cortex-A53 ARM64) [2] which could be used - I'm checking if > > coreboot already supports a similar SoC to base the port on. > > There are a number of ARM SOCs in development that are being merged from > chromium.org (chromebook). Take a look at src/soc and src/arch. This is a > pretty big task, but might be a good match if you have done some similar > work in past projects. I will look into it, thanks. > > > - Eliminate Video BIOS requirement for AMD/ATI graphics init: I understand > > this would involve dumping AtomBIOS ROM and performing those > > initializations > > under coreboot. I came across atomdis [3] and am looking for a Video BIOS > > ROM > > I could try disassembling. I need some input on how I could go about the > > implementation of this idea - what hardware would be suitable / what the > > boot > > flow would be. Although I haven't worked with the Linux graphics stack > > yet, I > > would like to get my hands dirty. I am currently looking through the > > resources > > at [4]. > > You might look at Gizmo2. I dumped the BIOS binary for a Radeon GPU and am trying to make sense of it using the atombios kernel header [1] - are there any resources on ATOMBIOS internals I can use? I believe the GPU initialization can be done by tracing the dump contents as suggested in this thread [2], but cannot figure how new ATOMBIOS tables would be created and used. I also need to check the coreboot source to plan how this can be implemented. > > > I recently tried running coreboot + SeaBIOS + SYSLINUX under QEMU (as > > suggested on the Easy tasks page [5]), and it seems to work alright - but > > is > > it possible to find a SYSLINUX ELF image so I can eliminate SeaBIOS? > > I don't know if anyone has made a SYSLINUX elf. Any small kernelvmlinuz and > initrd could be used. > http://www.coreboot.org/QEMU_Build_Tutorial#Building_a_Linux_kernel_payload > > > I would be glad to have your suggestions on how I could get started. > > You can join #coreboot on IR and , start looking at the patches on Gerrit > and get a feel for what is being developed. > > Again, Welcome! > Marc > Thanks! Are there any 'easy' bugs / features I could implement to get familiar with the development process? [1] http://lxr.free-electrons.com/source/drivers/gpu/drm/radeon/atombios.h [2] http://www.coreboot.org/pipermail/coreboot/2013-March/075522.html Thanks, Varad > > [1] http://www.coreboot.org/Project_Ideas#coreboot_ARM_ > > SoC.27s_mainboard_port > > [2] https://www.96boards.org/products/hikey/ > > [3] > > http://www.phoronix.com/scan.php?page=article&item=amd_ > > atombios_dumper&num=1 > > [4] http://www.coreboot.org/Project_Ideas#Native_graphics_init > > [5] http://www.coreboot.org/Easy_projects#Add.2Ftest_new_ > > supported_payloads > > > > Thanks, > > Varad > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] A new project proposal - MicroHOPE
by Marc Jones 07 Mar '15

07 Mar '15

Hi Arun, On Sat, Mar 7, 2015 at 1:46 AM Arun Jayan <arunjayan32(a)gmail.com> wrote: > Hello , > This is Arun Jayan from College of Engineeiring Poonjar , Kerala , India . > I am 3rd year Computer Science student , interested in FOSS technologies . > But i am totally beginner to GSoC . > > Currently i am working on open source project called MicroHOPE . Its a > open hardware developed by IUAC New Delhi , and released as a open hardware > . MicroHOPe is similar to arduino and its is lowest priced board available > in that category . It is based on atmega32 micro-controller . > > More info about microhope : > www.microhope.org > www.expeyes.in/microhope > https://github.com/ArunJayan > http://arunjayank.wordpress.com/ > > I mainly desiging a IDE for MicroHOPE to program its hardware .I had > written one version , its a simple version and available in debian unstable > section . Now I am designing a better IDE using PyQt4 with lot of features > . also i am working on a real time control to micro-controller (PyMicro) > using python for learning purposes (a addon to IDE ) and also UI for > PyMicro. > > One of my sir told me to apply for GSoC using this microhope project and > he told me that there i got all the technical help to make it more good > that i am thinking now . > So is there any chance for microhope in GSoC 2015 ? Please help me > MicroHOPE looks like an interesting microcontroller project, but may not fit well in the coreboot firmware project. Please read our wiki and project page for more information. http://www.coreboot.org/Project_Ideas Marc > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Bare metal hello world rs232 payload
by Marc Jones 07 Mar '15

07 Mar '15

Hi Adam On Sat, Mar 7, 2015 at 5:46 AM Adam Duncan <adam.duncan(a)gmail.com> wrote: > Hi all. I am new to coreboot and just built a default coreboot+seabios ROM > and ran it on a 64bit minnowboard max. Now I'd like to build a simple hello > world payload elf that would simply print a string on rs232. > > Can you recommend the best approach to do this? I was looking at using > libpayload but read in the README that it creates 32 bit elfs. > Libpayload is exactly what you want to use to make a simple hello world. The processor is in 32bit mode and can run 32bit code, if that is your concern. Regards, Marc > Thanks! > Adam > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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[Mohon Peak] Console output on external UARTs behind PCIe
by Patrick Agrain 07 Mar '15

07 Mar '15

Hello everybody, Do you think that it would be possible to output the console messages from coreboot (seabios) on another UART port (strapped to be visible on Memory-based space or IO Space) connected on a PCIe slot ? I've purchased a StarTech UART board with an OXPCIe952 chip, with the same IDs as visible in ./src/drivers/uart/oxpcie.c. On http://www.coreboot.org/Serial_console#PCIe.2FMini_PCIe_based_serial_cards, what is behind the sentence: "In order to use the card for romstage debugging, minimal setup of the PCIe bridge and the MPEX2S952 have to be added to romstage.c" ? Thanks in advance. Best regards, Patrick Agrain

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Bare metal hello world rs232 payload
by Adam Duncan 07 Mar '15

07 Mar '15

Hi all. I am new to coreboot and just built a default coreboot+seabios ROM and ran it on a 64bit minnowboard max. Now I'd like to build a simple hello world payload elf that would simply print a string on rs232. Can you recommend the best approach to do this? I was looking at using libpayload but read in the README that it creates 32 bit elfs. Thanks! Adam

1 0

Fallback mechanism fails to build on Lenovo T60
by Paul Menzel 07 Mar '15

07 Mar '15

Dear coreboot folks, trying to build a normal/fallback image [1] for the Lenovo T60 fails with the following error. $ make fatal: Repository '/src/nvidia-cbootimage.git' existiert nicht. Klonen von '/src/nvidia-cbootimage.git' in Submodul-Pfad 'util/nvidia/cbootimage' fehlgeschlagen LINK cbfs/normal/romstage_null.debug BFD: build/cbfs/normal/romstage_null.debug: warning: Empty loadable segment detected, is this intentional ? nm: build/cbfs/normal/romstage_null.offenders: no symbols OBJCOPY cbfs/normal/romstage_null.elf OBJCOPY cbfs/normal/romstage_null.bin GEN generated/romstage.ld LINK cbfs/normal/romstage.debug OBJCOPY cbfs/normal/romstage.elf CBFS coreboot.pre OBJCOPY cpu/x86/smm/smm_wrap.ramstage.o CC generated/ramstage.o CC cbfs/normal/ramstage.debug OBJCOPY cbfs/normal/ramstage.elf CBFS coreboot.rom PAYLOAD payload.elf (compression: LZMA) SeaBIOS Wait up to 3000 ms for PS/2 keyboard controller initialization E: 'etc/ps2-keyboard-spinup' already in ROM image. Makefile.inc:555: recipe for target 'build/coreboot.rom' failed make: *** [build/coreboot.rom] Error 1 Any ideas, how to deal with it? Just ignore the error in `Makefile.inc`? ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif Looking through `Makefile.inc` there might be more places where this might blow up. Thanks, Paul [1] http://www.coreboot.org/Fallback_mechanism

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A new project proposal - MicroHOPE
by Arun Jayan 07 Mar '15

07 Mar '15

Hello , This is Arun Jayan from College of Engineeiring Poonjar , Kerala , India . I am 3rd year Computer Science student , interested in FOSS technologies . But i am totally beginner to GSoC . Currently i am working on open source project called MicroHOPE . Its a open hardware developed by IUAC New Delhi , and released as a open hardware . MicroHOPe is similar to arduino and its is lowest priced board available in that category . It is based on atmega32 micro-controller . More info about microhope : www.microhope.org www.expeyes.in/microhope https://github.com/ArunJayan http://arunjayank.wordpress.com/ I mainly desiging a IDE for MicroHOPE to program its hardware .I had written one version , its a simple version and available in debian unstable section . Now I am designing a better IDE using PyQt4 with lot of features . also i am working on a real time control to micro-controller (PyMicro) using python for learning purposes (a addon to IDE ) and also UI for PyMicro. One of my sir told me to apply for GSoC using this microhope project and he told me that there i got all the technical help to make it more good that i am thinking now . So is there any chance for microhope in GSoC 2015 ? Please help me

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GSOC 2015 Aspirant for coreboot ARM SoC's mainboard port
by Saket Sinha 07 Mar '15

07 Mar '15

Hi, I would like to participate to Google Summer of Code 2015 by contributing to coreboot ARM SoC's mainboard port for Coreboot. I can see from the below link http://www.coreboot.org/Project_Ideas#coreboot_ARM_SoC.27s_mainboard_port This mainly targets- Xilinx Zynq-7030 Altera Cyclone V ST spear1340 Thus for this project, either of these hardware would be required. Kindly let me know the availability of these hardware for students and how to get started for the same. Regards, Saket Sinha

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coreboot March 2015