coreboot March 2015

coreboot@coreboot.org

62 participants
166 discussions

Re: [coreboot] Plans for upcoming Broadwell Thinkpads
by Zaolin 12 Mar '15

12 Mar '15

Hi, let's say goodbye to all Intel notebooks produced by OEM's which are not Google ( Chromebooks ). Maybe the haswell/broadwell notebooks of Lenovo without U/Y processor can be used ( Thinkpad tXX xXX ). It depends if they are supporting Intel Boot Guard on the southbridge... Regards Zaolin > On 02/06/2015 06:29 AM, Zaolin wrote: > > Hi, > > > > new thinkpad's can't be used anymore for coreboot. Especially the U and > > Y Intel CPU Series. > > They come with Intel Boot Guard and you are won't be able to boot > > anything which is unsigned and > > not approved by OEM. This means the OEM are fusing SHA256 public key > > hashes into the southbridge. > > > > For more details take a look at Intel Boot Guard architecture. It could > > be also confirmed by Secunet AG and Google. > > > > Regards Zaolin > > That's scary to say the least. No more Thinkpads for us... >

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Any modern server motherboards supported by coreboot?
by Dave Pifke 11 Mar '15

11 Mar '15

If one wanted to use a relatively recent Opteron or Xeon, are there any motherboards known to work with coreboot? I looked at the wiki and there's a lot of red "unknown"s there, the lone exception being the ASUS KFSN4-DRE, which is Socket F/DDR2. And it appears to no longer be available other than via Ebay or surplus dealers. -- Dave Pifke, dave(a)pifke.org

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Re: [coreboot] [Mohon Peak] Console output on external UARTs behind PCIe
by Patrick Agrain 11 Mar '15

11 Mar '15

Thanks Marc and Kyösti for your hints. As I'm just discovering coreboot and its multiple possibilities, please apologize if my questions seems "too simple"... ;-) A) UART Type ------------------- From Kconfig file in ./src/drivers/uart, the valid ID for the oxpcie is 1415:c158. I can obtain this ID on my Startech board only when I strapped it as "native UART" (Startech documentation), that is : memory-mapped. From Kconfig file in ./src/console, there is following sentence : "Supporting multiple different types of UARTs in one build is not supported.". Q: Am I correct if I translate this like : "Use only memory-mapped or IO-mapped UARTs, but not both at the same time." ? B) Memory-mapped UART required options -------------------------------------------------------------- From the answers received, I would say that the required options (in make menuconfig) would be: - In "Generic Drivers": validate Oxford OXPCIe952 and de-validate "Serial Port on SuperIO". - In "Devices": Set the device and function numbers of the PCie bridge, behind which is connected the Startech board. On Mohon Peak, it's D1-F0. Q: What about the MMIO window base ? Is it the memory address of the UARTs, defined by the values in the BAR registers ? - in "Console": Validate "Serial Port Console Output". Q: What about the index of the "Serial Port console output" ? IMHO, there are only valid for IO-mapped UART. Correct ? Q: Am I missing anything ? Thanks in advance for the time you want to spent on it. Regards, Patrick Le 06/03/2015 19:01, Marc Jones a écrit : > Hi Patrick, > > You can look at the Oxford pcie card and 8250MEM drivers for reference: > src/drivers/uart/oxpcie* > src/drivers/uart/uart8250mem* > > Marc > > > > On Fri, Mar 6, 2015 at 9:37 AM Patrick Agrain > <patrick.agrain(a)alcatel-lucent.com > <mailto:patrick.agrain@alcatel-lucent.com>> wrote: > > Hello everybody, > > Do you think that it would be possible to output the console messages > from coreboot (seabios) on another UART port (strapped to be > visible on > Memory-based space or IO Space) connected on a PCIe slot ? > > I've purchased a StarTech UART board with an OXPCIe952 chip, with the > same IDs as visible in ./src/drivers/uart/oxpcie.c. > > On > http://www.coreboot.org/Serial_console#PCIe.2FMini_PCIe_based_serial_cards, > what is behind the sentence: > "In order to use the card for romstage debugging, minimal setup of the > PCIe bridge and the MPEX2S952 have to be added to romstage.c" ? > > Thanks in advance. > Best regards, > Patrick Agrain > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > http://www.coreboot.org/mailman/listinfo/coreboot >

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MSR read in libpayload
by Adam Duncan 11 Mar '15

11 Mar '15

Hi, I'm working on a custom payload using libpayload. Is there a way to way to use libpayload to read and write to MSRs? I'm been reading the libpayload documentation and haven't been able to find a solution. Thanks!

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Re: [coreboot] H8 EC question
by Alexander Couzens 10 Mar '15

10 Mar '15

That would be great! If you need to query the EC by ectool - there's a patch waiting for review at https://review.coreboot.org/#/c/8382/ Best, lynxis

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Re: [coreboot] H8 EC question
by Alexander Couzens 10 Mar '15

10 Mar '15

Hi Charles, it would be nice if you could extend the wiki page http://www.coreboot.org/EC:lenovo/x201 I'ven't found anything yet, what's x201 specific. A good source of EC behaviour is the OEM ACPI Tables (dsdt) and the thinkpad acpi lkernel module. Best, lynxis

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H8 EC question
by Charles Devereaux 10 Mar '15

10 Mar '15

Hello, Is there documentation for the H8 EC somewhere? (not just some code - even if ec/lenovo/h8/acpi/ec.asl is very interesting) There seem to be a discrepancy on battery charge thesholds, with ACPI events such as "charge complete" (battery PNP0C0A:00 00000080 00000001) happening at 80%, while in /proc/acpi/battery/BAT0/ it keeps charging. At the moment,it's not possible to use tp-smapi, but it might be possible to manually correct the threshold by writing to the EC, cf http://www.thinkwiki.org/wiki/Talk:Maintenance. However, I see nothing at offset 0x24 with ec-access. I have no documentation for the H8 EC, but in src/ec/quanta/it8518/acpi/ec.asl I see values that seem familiar for thinkpads (ex: at offset 0x3A, the rfkill wifi/bluetooth/wwan) and a very interesting reference, which seems to match thinkwiki discussion: Offset(0x03), // [Configuration Space 3] (...) CHGR, 1, // Charge/Stop Charge threshold selector // 0: Battery Charge Threshold / 1: Stop Battery Charge Threshold Offset(0x24), // [Battery Charge / Stop Charge Threshold Setting for Primary Battery] (Read/Write) For the rfkill things, I see : Offset(0x01), // [Configuration Space 1] ENBT, 1, // Enable to toggle the BlueTooth and BDC power state every when the button is pressed. Maybe the following control the USB port, to have a proper rfkill for wwan (on EHCI port 1) 1. Offset(0x26), // [Reserved] 2. USP0, 1, // bit 0 USB0 3. USP3, 1, // bit 1 USB3 4. USP4, 1, // bit 2 USB4 5. EHP0, 1, // bit 3 EHCI0 6. EHP1, 1, // bit 4 EHCI1 Or : Offset(0x3B), // [Peripheral control 1] (...) USBN, 1, // USB On Anyway, it might not be a reliable description of the H8 features, so I though I should ask. I am also interested in the codes returned by the EC for various events to complete the ACPI tables. Any EC information is welcome! Thanks Charles

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Re: [coreboot] Legacy BIOS
by Timothy Pearson 09 Mar '15

09 Mar '15

On 03/09/2015 06:38 AM, ron minnich wrote: > I don't understand why you think we need a "legacy BIOS for minnowboard" > given what this group has been doing for the last 15 years. > > On Mon, Mar 9, 2015 at 4:24 AM Corey Osgood <corey.osgood(a)gmail.com > <mailto:corey.osgood@gmail.com>> wrote: > > He's trying to advertise his company's legacy BIOS solution. > > -Corey > Sounds like pure spam to me. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

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[Gsoc 15] Interested in participating - Idea Discussion (Ganesh Sundar)
by 107112017＠nitt.edu 09 Mar '15

09 Mar '15

Hi! I would like to contribute to coreboot. I have configured the development environment for coreboot, tianocore and am able to build properly. I am a newbie and have been going through the code, its docs, & the hardware datasheets recently. On IRC, kmalkki suggested me to start on providing header/footer encapsulation for hexdumps of memory (for lspci -F and iasl disassembly). I tried something in [2], but am very unsure if that is what he meant. patricg told some ideas related to tianocore and I am interested in working on CBFS driver for tiano. I still need more time to understand the code (particularly CBFS, libpayload and tiano), and during the period I would like to work on documentation in [1] or any other easy tasks. Kindly guide me. [1]: https://trello.com/b/kxojIGTB/todos [2]: https://github.com/77ganesh/small-works/blob/master/pci-hex-format/ Thanking You! Ganesh

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Re: [coreboot] (no subject)
by Marc Jones 09 Mar '15

09 Mar '15

Hi Vinamra, Welcome, There are a number of solutions on the flashrom page. Have you examined the flashrom wiki? I recommend that you join the flashrom email list and irc channel to learn more. Regards, Marc On Sun, Mar 8, 2015 at 1:56 AM vin ben <vinben94(a)gmail.com> wrote: > Hi , > > I am Vinamra. I am an Electronics undergraduate at IIIT-Hyderabad in > India. I want to contribute to the FPGA-based flash chip > emulator project (Flashrom) in the summer of code program. I have good > experience > with digital design and VHDL . Can you please get me started. > > many thanks > -Vinamra. > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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coreboot March 2015