coreboot guys,
I noticed the source code check-in last week have a problem - modifying
some items with "make menuconfig", such as bootsplash file, then building
with "make" command, the new bootsplash file will be **NOT** compiled into
new coreboot image.
I dont notice this issue one week before (I update my coreboot source code
one a week), does anyone have the same issue?
This is just a quick query, I can update the details tomorrow.
-Fei
On 19.07.2014 07:42, Charles Devereaux wrote:
> Hello,
>
> On Wed, Jul 9, 2014 at 2:15 AM, Denis 'GNUtoo' Carikli
> <GNUtoo(a)no-log.org <mailto:GNUtoo@no-log.org>> wrote:
>
> My pomona clip had issues with its contact pins(the ones in contact
> with the flash chip) over time, so I unmounted it and repaired it.
>
>
> I tried pushing the pins down - it looks better but it didn't help. Mine
> only work with a lot of duct tape to keep it firmly pressed to the
> motherboard. Otherwise, it slides up just a bit, enough to avoid making
> contact. It seems more like a problem with the plastic
>
>
> Example in grub.cfg:
> menuentry 'Normal' {
> cmosclean 0x30:0
> cmosclean 0x30:1
> cmosclean 0x30:2
> cmosclean 0x30:3
> cmosclean 0x30:4
> cmosclean 0x30:5
>
> halt
> }
>
>
> Interesting. Is there a reason why different values are used on gluglug
> halt? cf http://samnoble.org/thinkpad/grub/gluglug.grub.custom.cfg:
>
The values are exactly the same. Search for hex.
> There is only cbmemc, cbls and cbtime. They could be good menu options
> but the output is displayed without a pager (so you can't see them as it
> goes back to the menu - you have to enter a command line)
>
pager=1
> Of all of these, cbtime would be especially interesting to add a title
> to grub menu, to show if the boot was in normal or fallback and how long
> it took.
>
> I'll see if it's possible to add the result of a command to grub menu
Tuan, Sorry - I've been on vacation and missed this thread until now.
What Wang Fei suggested is exactly right - you need to start with a
different BIOS flashed on the board.. The problem is the Descriptor/TXE
that is being used. Intel has said that they would update the build
instructions included with the FSP to highlight this issue, but I don't
know if this has been done.
I'm thinking I'll put in a check for this condition and print out a
message stating what needs to be done. I'll try to get that added shortly.
Martin
On 07/17/2014 03:55 PM, WANG FEI wrote:
> Tuan,
>
> Your platform's northbirdge and GFX device ID is 0x0 and 0x0031? It's
> definitely wrong, I would suggest you to download the Bayley Bay
> platform's official UEFI BIOS from Intel IBL and flash it to you
> Bayley Bay platform, then see what's the correct ID.
>
>
> On Fri, Jul 11, 2014 at 4:36 AM, Patrick Georgi
> <patrick(a)georgi-clan.de <mailto:patrick@georgi-clan.de>> wrote:
>
> Am 01.07.2014 17:55, schrieb Tuan Vu:
> > Typically, what creates the memory ranges?
> To a large degree the memory init code, which is closed source in the
> FSP model and thus unavailable to us.
>
> When it comes to memory issues with FSP, it might be better to ask
> Intel
> directly.
>
>
> Regards,
> Patrick
>
>
> --
> coreboot mailing list: coreboot(a)coreboot.org
> <mailto:coreboot@coreboot.org>
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>
>
>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On Mon, 7 Jul 2014 20:56:12 -0400
Charles Devereaux <coreboot(a)guylhem.net> wrote:
> Problem is my pomona is not establishing reliable connections, unless
> I use a lot of duct tape. I'd be interested in using the ISP header
> if possible.
My pomona clip had issues with its contact pins(the ones in contact
with the flash chip) over time, so I unmounted it and repaired it.
> Also, is it possible to indicate a normal boot from grub with
> cmostest / cmosclear / cmosset / cmosdump functions?
The cmos layout is in src/mainboard/lenovo/x60/cmos.layout
Example in grub.cfg:
menuentry 'Normal' {
cmosclean 0x30:0
cmosclean 0x30:1
cmosclean 0x30:2
cmosclean 0x30:3
cmosclean 0x30:4
cmosclean 0x30:5
halt
}
Vladimir Serbinenko said me that it was a bad idea to do this and that
he would instead work on something better that would understand the
coreboot cmos layout. I've not checked if there is now something for it
in grub.
Denis.
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Charles Devereaux wrote:
> BTW, here seem to be other ACPI issues.
Yes, there are lots of known issues.
They can all be solved by someone who knows how to solve them, or who
spends the time to learn how to solve them, and then spends the time
to implement the solutions.
//Peter
I'm trying to investigate Coreboot and FSP booting performance on the Intel's Bayley Bay board and having trouble getting it to boot SeaBIOS. I had to modify some files to get it to the point of attempting to load the payload but it gets stuck here:
Could not find a bounce buffer...
Could not load payload
Additional printfk reveals that none of the memory ranges described in bootmem has the tag LB_MEM_RAM; they all have the LB_MEM_RESERVED, LB_MEM_TABLE and LB_MEM_UNUSABLE. Any ideas what went wrong here? Typically, what creates the memory ranges?
Thanks,
Tuan Vu
Software Engineer
Insyde Software, Inc.
hi ruik,
i'm back to building and installing coreboot on the f2a85-m. (i was
previously having stability issues with something coreboot-, kernel-, or
blob-related in january.)
coreboot is now working fairly well with the proper toolchain, etc. when
not using the vga option rom. one of the graphics cards i'm using is a
geforce 7600 gs pci card.
the latest vga option rom i've semi-sucessfully used comes from the uefi
rev 6402. that install crashed after ~5 hours, perhaps due to the very
recent kernel i used. i've briefly tested with a stable kernel, which at
least boots fine.
i've tried using a vga blob extracted from rev 6506, but there is no dvi
or vga output with that binary revision.
which vga option rom do you use?
thanks,
-andrew
Hello
I tried to investigate the status of TPM support on the X60. Unlike on the
Acer C270, it is not used by coreboot at all (CONFIG_TPM is not set) - the
problems seems to be that it is not initialized.
On a standard bios, I can see at boot :
Jul 17 09:47:45 lenovo kernel: [ 0.118724] pnp 00:0d: Plug and Play
ACPI device, IDs ATM1200 PNP0c31 (active)
With coreboot, nothing like that. Booting with tpm_tis.force=1 still fails
(because of a missing PNP0C31 in the DSDT I believe)
Probing further, I found the device initialization on acpi_3.rom (after
running bios-extract on the standard bios). Running that though iasl, the
code is quite complex - it is attached below.
Based on my understanding, ACPI tables are created on coreboot from
devicetree.cb file, which is quite different and that I don't fully
understand.
At the moment, I'm trying to use http://www.coreboot.org/pipermail/coreboot
gerrit/2014-May/010810.html as a base for ATM1200 and PNP0C31 definitions
(with apparently the same parameters (mem, etc) as in acpi_3.dsl
BTW, here seem to be other ACPI issues. With thinkpad_acpi, leds can only
be turned off. Doing anything else, one only gets the following warning:
[ 1033.498022] ACPI Warning: For \_SB_.PCI0.LPCB.EC__.LED_: Excess
arguments - needs 1, found 2 (20130328/nspredef-272)
Likewise, the stylus insertion/removal, (detected by a small swtich)
triggers TP_HKEY_EV_PEN_INSERTED and REMOVED in thinkpad-acpi, ie
ibm/hotkey HKEY 00000080 0000500b and ibm/hotkey HKEY 00000080 0000500c
Nothing like that with coreboot and thinkpad_acpi.
I haven't looked much into that, but the problem seems the same : a missing
or incomplete definition.
Hello!
I added support from the TPM to SeaBIOS and have parts of the BIOS
functionality successfully running on a Chromebook Acer C720 (as example
hardware). Here are some findings on the Acer:
The TPM is successfully detected but sending TPM_Startup(ST_Clear) to
the TPM fails since either coreboot or some other firmware seems to
already have initialized the TPM, which is fine, and also extended PCR 0
with at least one hash. Ideally there would be a TCPA ACPI table
containing information about what was logged, since otherwise the state
of the PCR seems not that useful. SeaBIOS's TPM extensions could then
also use this TCPA table and add its own logs into it along with
extending PCRs in the TPM. So, in this case the TPM SeaBIOS extensions
don't log anything and adding additional ACPI tables to the existing
coreboot tables seems 'impractical'. I was wondering if coreboot could
add such a table if a TPM was found to be present?
The latest set of TPM patches can be found here:
http://www.seabios.org/pipermail/seabios/2014-July/008178.html
Regards,
Stefan
