Michael Brown wrote:
> Wondering if coreboot supports my motherboard. Asus P5Q Pro using P45 and
> ICH10 chipset. Core 2 Duo.
Doesn't.
> If not, what is the main impediment?
I don't think the chipset is supported at all. Significant (man-year) effort.
//Peter
Wondering if coreboot supports my motherboard. Asus P5Q Pro using P45 and
ICH10 chipset. Core 2 Duo.
If not, what is the main impediment? Is it the lack of soft strap
documentation?
Thanks.
--
Michael
Sorry, I forgot to include the contents of the ROM image:
ricardo@ricardo-VirtualBox:~/BAY_TRAIL_FSP_KIT/coreboot$
build/cbfstool build/coreboot.rom print
coreboot.rom: 8192 kB, bootblocksize 1024, romsize 8388608, offset 0x600000
alignment: 64 bytes
Name Offset Type Size
cmos_layout.bin 0x600000 cmos_layout 1132
pci8086,0f31.rom 0x6004c0 optionrom 65536
fallback/romstage 0x610500 stage 26364
fallback/ramstage 0x616c40 stage 58469
fallback/payload 0x625100 payload 118456
config 0x642000 raw 4012
(empty) 0x643000 null 839640
cpu_microcode_blob.bin 0x710000 microcode 104448
(empty) 0x729840 null 616280
fsp.bin 0x7bffc0 (unknown) 229376
(empty) 0x7f8000 null 31640
On Tue, Jul 15, 2014 at 2:45 PM, Ricardo Menzer <ricardomenzer(a)gmail.com> wrote:
> Hi.
> I'm also trying to use Coreboot with a COM Express Module from
> Cogatec. It is a Conga-MA3 model
> [http://www.congatec.com/products/com-express-type10/conga-ma3.html].
> Booting the original BIOS into Linux, and doing a cat /proc/cpu shows
> the processor stepping is 3, so i'm assuming it's a B3 silicon.
> I have used Intel BCT to patch the FSP so its configuration matches
> the memory chips used in this module.
> I am testing it with a base board made by Kontron, which provides a
> four digit port 80h/81h display and a SPI socket, allowing me to use
> an external flash and preserve module's flash.
> I couldn't make flashrom detect the flash memory when using this
> module from Congatec, even disabling BIOS memory write protection on
> BIOS setup, but I'm using another module to flash the external SPI and
> swapping modules after. (I plan to find out why it isn't detected
> later).
>
> I've copied
> /home/ricardo/BAY_TRAIL_FSP_KIT/Microcode/M013067331E.h
> /home/ricardo/BAY_TRAIL_FSP_KIT/Microcode/M0230672228.h
> to /home/ricardo/BAY_TRAIL_FSP_KIT/coreboot/src/soc/intel/fsp_baytrail/microcode
> so Coreboot can compile (otherwise Make fails).
>
> The first image I've burned didn't worked (.config file attached).
> There's no POST codes in the display. I think it may be a issue with
> the TXE firmware. How can I check it?
>
> I'm trying to learn about the inner workings of coreboot. How can I
> help to support this module/chipset?
>
> Thanks.
>
> On Thu, Jul 10, 2014 at 7:29 PM, ron minnich <rminnich(a)gmail.com> wrote:
>>
>>
>>
>> On Wed, Jun 25, 2014 at 4:11 AM, benjamin nakache <bnakache(a)nolam.com>
>> wrote:
>>>
>>> Hello ,
>>>
>>>
>>>
>>> When will support the new Atom E38XX
>>>
>>>
>>
>>
>>
>> Would you or someone from your company like to help?
>>
>>>
>>>
>>>
>>> Note: This message and any attachment hereto is intended solely for the
>>> use of the designated recipient(s) and their appointed delegates and may
>>> contain confidential information. Any unauthorized use, disclosure,copying,
>>> or distribution of its contents is strictly prohibited. If you have received
>>> this message in error, please destroy it and advise Nolam Embedded Systems
>>> immediately by phone, email, or fax.Thank you for your cooperation.
>>>
>>>
>>>
>>>
>>
>>
>>
>> You should remove this Note:, else we won't be able to receive your messages
>> any more :-)
>>
>> thanks
>>
>> ron
>>
>> --
>> coreboot mailing list: coreboot(a)coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>
>
>
> --
>
>
> Ricardo Menzer
> ricardomenzer(a)gmail.com
> (32)8865-8805
--
Ricardo Menzer
ricardomenzer(a)gmail.com
(32)8865-8805
Hi.
I'm also trying to use Coreboot with a COM Express Module from
Cogatec. It is a Conga-MA3 model
[http://www.congatec.com/products/com-express-type10/conga-ma3.html].
Booting the original BIOS into Linux, and doing a cat /proc/cpu shows
the processor stepping is 3, so i'm assuming it's a B3 silicon.
I have used Intel BCT to patch the FSP so its configuration matches
the memory chips used in this module.
I am testing it with a base board made by Kontron, which provides a
four digit port 80h/81h display and a SPI socket, allowing me to use
an external flash and preserve module's flash.
I couldn't make flashrom detect the flash memory when using this
module from Congatec, even disabling BIOS memory write protection on
BIOS setup, but I'm using another module to flash the external SPI and
swapping modules after. (I plan to find out why it isn't detected
later).
I've copied
/home/ricardo/BAY_TRAIL_FSP_KIT/Microcode/M013067331E.h
/home/ricardo/BAY_TRAIL_FSP_KIT/Microcode/M0230672228.h
to /home/ricardo/BAY_TRAIL_FSP_KIT/coreboot/src/soc/intel/fsp_baytrail/microcode
so Coreboot can compile (otherwise Make fails).
The first image I've burned didn't worked (.config file attached).
There's no POST codes in the display. I think it may be a issue with
the TXE firmware. How can I check it?
I'm trying to learn about the inner workings of coreboot. How can I
help to support this module/chipset?
Thanks.
On Thu, Jul 10, 2014 at 7:29 PM, ron minnich <rminnich(a)gmail.com> wrote:
>
>
>
> On Wed, Jun 25, 2014 at 4:11 AM, benjamin nakache <bnakache(a)nolam.com>
> wrote:
>>
>> Hello ,
>>
>>
>>
>> When will support the new Atom E38XX
>>
>>
>
>
>
> Would you or someone from your company like to help?
>
>>
>>
>>
>> Note: This message and any attachment hereto is intended solely for the
>> use of the designated recipient(s) and their appointed delegates and may
>> contain confidential information. Any unauthorized use, disclosure,copying,
>> or distribution of its contents is strictly prohibited. If you have received
>> this message in error, please destroy it and advise Nolam Embedded Systems
>> immediately by phone, email, or fax.Thank you for your cooperation.
>>
>>
>>
>>
>
>
>
> You should remove this Note:, else we won't be able to receive your messages
> any more :-)
>
> thanks
>
> ron
>
> --
> coreboot mailing list: coreboot(a)coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
--
Ricardo Menzer
ricardomenzer(a)gmail.com
(32)8865-8805
Paul,
Attached please find the console log for coreboot and seabios (not really
anything).
Since my board does not have a physical VGA adapter. I did not configure
anything for VGA in coreboot. Do I need to configure anything to tell
coreboot to load the sgabios? As you can see in the log, there is nothing
indicating coreboot loading the sgabios.
Thanks!
Wen
PS: I set my outlook to send plain text. Hope the setting works. :-)
Date: Fri, 11 Jul 2014 23:10:25 +0200
From: Paul Menzel <paulepanter(a)users.sourceforge.net>
To: coreboot(a)coreboot.org
Subject: Re: [coreboot] sgabios no console output from Seabios
Message-ID: <1405113025.6921.73.camel@mattotaupa>
Content-Type: text/plain; charset="utf-8"
Dear Wen,
Am Freitag, den 11.07.2014, 10:41 -0400 schrieb Wen Wang:
> I am experimenting Coreboot on an Intel Rangeley based system using
> Seabios
> (master) as payload. The system does not have VGA adapter. So I added
> sgabios.
welcome to coreboot! Please note that the official spelling of coreboot is
all lowercase. (Also SeaBIOS.)
> $ ./build/cbfstool build/coreboot.rom print
>
> coreboot.rom: 8192 kB, bootblocksize 720, romsize 8388608, offset
> 0x400000
>
> Alignment: 64 bytes
>
> Name Offset Type Size
>
> cpu_microcode_blob.bin 0x0 microcode 166976
>
> cmos_layout.bin 0x28c80 cmos layout 1164
>
> fallback/coreboot_ram 0x29140 stage 41355
>
> config 0x33340 raw 3307
>
> vgaroms/sgabios.bin 0x34080 raw 4096
>
> (empty) 0x350c0 null 44696
>
> fallback/romstage 0x3ff80 stage 182967
>
> fallback/payload 0x6cac0 payload 58701
>
> (empty) 0x7b080 null 3165976
>
> FvFsp.bin 0x37ffc0 raw 372736
>
> (empty) 0x3db000 null 150760
>
> However I don't see Seabios boot menu on console. The system pauses
> after Seabios is loaded and then starts OS. There is no problem with
> Coreboot and Linux console output, but no output from Seabios is seen
> at all on the console.
>
> ..
>
> Payload (probably SeaBIOS) loaded into a reserved area in the lower
> 1MB
>
> Loading Segment: addr: 0x00000000000e4350 memsz: 0x000000000001bcb0
filesz:
> 0x000000000000e50c
>
> lb: [0x0000000000100000, 0x00000000001a4000)
>
> Post relocation: addr: 0x00000000000e4350 memsz: 0x000000000001bcb0
filesz:
> 0x000000000000e50c
>
> using LZMA
>
> [ 0x000e4350, 00100000, 0x00100000) <- ffc6cb30
>
> dest 000e4350, end 00100000, bouncebuffer 7fc98000
>
> Loaded segments
>
> Jumping to boot code at fd567
>
> entry = 0x000fd567
>
> lb_start = 0x00100000
>
> lb_size = 0x000a4000
>
> adjust = 0x7fc3c000
>
> buffer = 0x7fc98000
>
> elf_boot_notes = 0x001185b4
>
> adjusted_boot_notes = 0x7fd545b4
>
> [ 0.000000] Initializing cgroup subsys cpuset
> [ 0.000000] Initializing cgroup subsys cpu..
>
> Seabios (master) is pulled and automatically built as part of the
> coreboot build. During the build, it popped out a menu to for VGA hardware
type.
>
> VGA Hardware Type
>
> > 1. None (NO_VGABIOS)
> 2. GeodeGX2 (VGA_GEODEGX2)
> 3. GeodeLX (VGA_GEODELX)
> 4. coreboot linear framebuffer (VGA_COREBOOT) (NEW)
>
> choice[1-4]:
>
> I tried both 1 and 4. Neither of them seem to work. Did I miss something?
I did not spot anything. Could you please attach/paste the whole coreboot
and SeaBIOS log?
Thanks,
Paul
PS: Could you please just send plain text messages, that means no HTML, to
the list? Big thanks in advance.
Wang Fei,
The I/O port base address was problem. I changed it to 0x2f8, and I am seeing seabios output now. Thanks!
Wen
From: WANG FEI [mailto:wangfei.jimei@gmail.com]
Sent: Tuesday, July 15, 2014 8:37 AM
To: Paul Menzel
Cc: coreboot; Wen Wang
Subject: Re: [coreboot] sgabios no console output from Seabios (was: coreboot Digest, Vol 113, Issue 17)
Wang Wen,
I found following message in the coreboot-seabios log,
[ 0.000000] Command line: BOOT_IMAGE=/vmlinuz-3.3.4-5.fc17.x86_64 root=UUID=c4d4a429-d880-4caa-831e-9e95b5595f67 ro rd.md <http://rd.md> =0 rd.lvm=0 rd.dm <http://rd.dm> =0 SYSFONT=True KEYTABLE=us rd.luks=0 LANG=en_US.UTF-8 console=ttyS1,115200n8
It shows "console=ttyS1,115200n8", it means the Linux kernel is using ttyS1 as the primary serial console, which is I/O port 0x2f8. But the seabios configure file shows seabios is configured using I/O port 0x3f8. it might be the problem.
Please run "make menuconfig" in seabios and reconfigure the serial port to 0x2f8, let us know any difference.
-Wang Fei
On Mon, Jul 14, 2014 at 9:53 PM, Paul Menzel <paulepanter(a)users.sourceforge.net <mailto:paulepanter@users.sourceforge.net> > wrote:
Dear Wen,
Am Montag, den 14.07.2014, 11:32 -0400 schrieb Wen Wang:
> Thanks for looking into to it!
>
> I pulled the seabios tree and built seabios manually (.config shown
> below). I then loaded seabios/out/bios.bin.elf as coreboot payload and
> sgabios as option rom. Unfortunately the same result, no output from
> seabios at all.
If you build and run the utility `cbmem` as shown below, what is the
output of the last two commands?
$ cd util/cbmem
$ make
$ sudo cbmem -l
$ sudo cbmem -c
Thanks,
Paul
--
coreboot mailing list: coreboot(a)coreboot.org <mailto:coreboot@coreboot.org>
http://www.coreboot.org/mailman/listinfo/coreboot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Dear coreboot community,
If you have one with an Intel (GMA 950) GPU and it is the 15.4"
(widescreen) T60, I need testers for libreboot 6 (see details on
libreboot.org homepage).
Looking forward to replies!
Regards,
Francis Rowe.
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Wondering if you support my motherboard. Asus P5Q Pro using P45 and ICH10
chipset. Core 2 Duo.
Also, after reading the ICH10 datasheet, I see a lot of GPIO pins available
if enabled. Has anyone used these to communicate status during bootup.
Seems like it wouldn't be hard to connect to a microcontroller to read them.
Thanks.
--
Michael
Hi all,
I am experimenting Coreboot on an Intel Rangeley based system using Seabios
(master) as payload. The system does not have VGA adapter. So I added
sgabios.
$ ./build/cbfstool build/coreboot.rom print
coreboot.rom: 8192 kB, bootblocksize 720, romsize 8388608, offset 0x400000
Alignment: 64 bytes
Name Offset Type Size
cpu_microcode_blob.bin 0x0 microcode 166976
cmos_layout.bin 0x28c80 cmos layout 1164
fallback/coreboot_ram 0x29140 stage 41355
config 0x33340 raw 3307
vgaroms/sgabios.bin 0x34080 raw 4096
(empty) 0x350c0 null 44696
fallback/romstage 0x3ff80 stage 182967
fallback/payload 0x6cac0 payload 58701
(empty) 0x7b080 null 3165976
FvFsp.bin 0x37ffc0 raw 372736
(empty) 0x3db000 null 150760
However I don't see Seabios boot menu on console. The system pauses after
Seabios is loaded and then starts OS. There is no problem with Coreboot and
Linux console output, but no output from Seabios is seen at all on the
console.
..
Payload (probably SeaBIOS) loaded into a reserved area in the lower 1MB
Loading Segment: addr: 0x00000000000e4350 memsz: 0x000000000001bcb0 filesz:
0x000000000000e50c
lb: [0x0000000000100000, 0x00000000001a4000)
Post relocation: addr: 0x00000000000e4350 memsz: 0x000000000001bcb0 filesz:
0x000000000000e50c
using LZMA
[ 0x000e4350, 00100000, 0x00100000) <- ffc6cb30
dest 000e4350, end 00100000, bouncebuffer 7fc98000
Loaded segments
Jumping to boot code at fd567
entry = 0x000fd567
lb_start = 0x00100000
lb_size = 0x000a4000
adjust = 0x7fc3c000
buffer = 0x7fc98000
elf_boot_notes = 0x001185b4
adjusted_boot_notes = 0x7fd545b4
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu..
.
Seabios (master) is pulled and automatically built as part of the coreboot
build. During the build, it popped out a menu to for VGA hardware type.
VGA Hardware Type
> 1. None (NO_VGABIOS)
2. GeodeGX2 (VGA_GEODEGX2)
3. GeodeLX (VGA_GEODELX)
4. coreboot linear framebuffer (VGA_COREBOOT) (NEW)
choice[1-4]:
I tried both 1 and 4. Neither of them seem to work. Did I miss something?
Thanks!
Wen
Wen Wang
Senior Software Engineer
ADI Engineering, Inc.
1758 Worth Park
Charlottesville, VA 22911
(434)978-2888
wen.wang(a)adiengineering.com <mailto:wen.wang@adiengineering.com>
