July 2014 - coreboot - mail.coreboot.org

Re: [coreboot] microcode updates
by Gregg Levine July 8, 2014

July 8, 2014

Hello! Agreed on all points. Now Scott, I'm certainly no expert on Intel processors either, but in a word, "Thank you!", regarding all of that searching and finding out where that stuff is based. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again." On Tue, Jul 8, 2014 at 2:57 PM, ron minnich <rminnich(a)gmail.com> wrote: > Yes, and that's sensible for some cases, if you consider that people don't > always keep their firmware up to date! > > To be honest, I'm trying a little bit to discourage the idea that it's safe > to build coreboot without microcode blobs on modern CPUs. Might work on your > x60. Not recommended on more recent chipsets. Yes, you might get it to boot. > That's almost worse than having it fail. > > ron > > > On Tue, Jul 8, 2014 at 11:26 AM, Scott Duplichan <scott(a)notabs.org> wrote: >> >> ron minnich [mailto:rminnich@gmail.com] wrote: >> >> ]you can no longer update microcode after the kernel boots >> ](on modern Intel CPUs). It has to happen before you do Cache >> ]As Ram in many cases, or you'll get some pretty unpleasant >> ]consequences. >> ] >> ]ron >> ] >> ][...] >> >> While I am no expert on recent Intel processors, it appears >> Intel still distributes patch packages for OS use (goo.gl/ffLdyq) >> and Linux still applies them (goo.gl/oaBvdE). >> >> Thanks, >> Scott >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] microcode updates
by Scott Duplichan July 8, 2014

July 8, 2014

ron minnich [mailto:rminnich@gmail.com] wrote: ]you can no longer update microcode after the kernel boots ](on modern Intel CPUs). It has to happen before you do Cache ]As Ram in many cases, or you'll get some pretty unpleasant ]consequences. ] ]ron ] ][...] While I am no expert on recent Intel processors, it appears Intel still distributes patch packages for OS use (goo.gl/ffLdyq) and Linux still applies them (goo.gl/oaBvdE). Thanks, Scott

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Re: [coreboot] microcode updates
by ron minnich July 8, 2014

July 8, 2014

no, that is not early enough on some CPUs. ron On Tue, Jul 8, 2014 at 11:20 AM, yhlu <yinghailu(a)gmail.com> wrote: > On Tue, Jul 8, 2014 at 10:39 AM, ron minnich <rminnich(a)gmail.com> wrote: > > you can no longer update microcode after the kernel boots (on modern > Intel > > CPUs). It has to happen before you do Cache As Ram in many cases, or > you'll > > get some pretty unpleasant consequences. > > so even microcode_early will not help? > > config MICROCODE_EARLY > bool "Early load microcode" > depends on MICROCODE=y && BLK_DEV_INITRD > select MICROCODE_INTEL_EARLY if MICROCODE_INTEL > select MICROCODE_AMD_EARLY if MICROCODE_AMD > default y > help > This option provides functionality to read additional microcode > data > at the beginning of initrd image. The data tells kernel to load > microcode to CPU's as early as possible. No functional change if > no > microcode data is glued to the initrd, therefore it's safe to > say Y. >

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Re: [coreboot] microcode updates
by yhlu July 8, 2014

July 8, 2014

On Tue, Jul 8, 2014 at 10:39 AM, ron minnich <rminnich(a)gmail.com> wrote: > you can no longer update microcode after the kernel boots (on modern Intel > CPUs). It has to happen before you do Cache As Ram in many cases, or you'll > get some pretty unpleasant consequences. so even microcode_early will not help? config MICROCODE_EARLY bool "Early load microcode" depends on MICROCODE=y && BLK_DEV_INITRD select MICROCODE_INTEL_EARLY if MICROCODE_INTEL select MICROCODE_AMD_EARLY if MICROCODE_AMD default y help This option provides functionality to read additional microcode data at the beginning of initrd image. The data tells kernel to load microcode to CPU's as early as possible. No functional change if no microcode data is glued to the initrd, therefore it's safe to say Y.

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Re: [coreboot] microcode updates
by ron minnich July 8, 2014

July 8, 2014

you can no longer update microcode after the kernel boots (on modern Intel CPUs). It has to happen before you do Cache As Ram in many cases, or you'll get some pretty unpleasant consequences. ron On Tue, Jul 8, 2014 at 9:34 AM, Gregg Levine <gregg.drwho8(a)gmail.com> wrote: > Hello! > No I haven't. But I've known about the Intel Microcode update idea for > about fifteen years. Turns out that the Linux Kernel 2.4.33.2 of > course has it, and described the update process. The two responsible > for that method have been out of business so to speak for a while now. > > But according to that site its still being done. Interesting. I do > also know its volatile, in that if the computer gets shutdown and > thence turned off, the feature would need to be flashed back onto its > CPU and so forth. > ----- > Gregg C Levine gregg.drwho8(a)gmail.com > "This signature fought the Time Wars, time and again." > > > On Tue, Jul 8, 2014 at 12:27 PM, ron minnich <rminnich(a)gmail.com> wrote: > > I had not seen this, maybe you all have, but: > > http://inertiawar.com/microcode/ > > > > ron > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] microcode updates
by Gregg Levine July 8, 2014

July 8, 2014

Hello! No I haven't. But I've known about the Intel Microcode update idea for about fifteen years. Turns out that the Linux Kernel 2.4.33.2 of course has it, and described the update process. The two responsible for that method have been out of business so to speak for a while now. But according to that site its still being done. Interesting. I do also know its volatile, in that if the computer gets shutdown and thence turned off, the feature would need to be flashed back onto its CPU and so forth. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again." On Tue, Jul 8, 2014 at 12:27 PM, ron minnich <rminnich(a)gmail.com> wrote: > I had not seen this, maybe you all have, but: > http://inertiawar.com/microcode/ > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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microcode updates
by ron minnich July 8, 2014

July 8, 2014

I had not seen this, maybe you all have, but: http://inertiawar.com/microcode/ ron

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installing Coreboot to T60(MX25L1605AM2C flash chip)
by Martin T July 8, 2014

July 8, 2014

Hi, I have an IBM ThinkPad T60 laptop(1951-CTO) which uses BIOS(version 2.27) from Phoenix Technologies. I would like to replace this with Coreboot and use SeaBIOS as a payload as I need to change the order of boot devices from time to time. I do not need SeaBIOS for BIOS callback functions as I use only Linux-based opeating systems on this machine. Based on the instructions in Coreboot wiki, I downloaded the flashrom source(r1711 according to ChangeLog file) and looked for the definition of my flash chip in flashrom's flashchips.c file. My flash chip is Macronix MX25L1605AM2C. What is the correct definition of my flash chip in flashchips.c file? As one can see, there are three ones which seem to match: root@T60:~/flashrom-0.9.7# grep name flashchips.c | grep MX25L1605 .name = "MX25L1605", .name = "MX25L1605A/MX25L1606E", .name = "MX25L1605D/MX25L1608D", root@T60:~/flashrom-0.9.7# In addition, I tried to find the datasheet for MX25L1605AM2C to look up the ID bytes the flash replies to the RES ID command and RES model ID, but I wasn't able to find the exact data sheet. Or could I use the datasheet of MX25L1605A(https://db.tt/oe6Cgm8K)? regards, Martin

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Re: [coreboot] Request for Intel Haswell info
by Peter Stuge July 8, 2014

July 8, 2014

Paul Wilcox-Baker wrote: > > as a first pass, did you burn coreboot for the wrong board just to see if > > you got anything al all on serial? > > We have some vaguely similar commercial desktop and 1U server designs, > but they aren't in the supported systems list. As Ron said, run the wrong coreboot code for the most similar board. You will learn about both coreboot and the hardware. //Peter

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Re: [coreboot] ISP header for x60, fallback: indicating normal boot from grub2
by Peter Stuge July 8, 2014

July 8, 2014

Charles Devereaux wrote: > Is there a ISP header? No. It is a Windows machine and not a development board. Add your own. //Peter

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