I'm trying to investigate Coreboot and FSP booting performance on the Intel's Bayley Bay board and having trouble getting it to boot SeaBIOS. I had to modify some files to get it to the point of attempting to load the payload but it gets stuck here:
Could not find a bounce buffer... Could not load payload
Additional printfk reveals that none of the memory ranges described in bootmem has the tag LB_MEM_RAM; they all have the LB_MEM_RESERVED, LB_MEM_TABLE and LB_MEM_UNUSABLE. Any ideas what went wrong here? Typically, what creates the memory ranges?
Thanks,
Tuan Vu
Software Engineer Insyde Software, Inc.
On Tue, Jul 1, 2014 at 10:55 AM, Tuan Vu tuan.vu@insyde.com wrote:
I’m trying to investigate Coreboot and FSP booting performance on the Intel’s Bayley Bay board and having trouble getting it to boot SeaBIOS. I had to modify some files to get it to the point of attempting to load the payload but it gets stuck here:
Could not find a bounce buffer...
Could not load payload
Additional printfk reveals that none of the memory ranges described in bootmem has the tag LB_MEM_RAM; they all have the LB_MEM_RESERVED, LB_MEM_TABLE and LB_MEM_UNUSABLE. Any ideas what went wrong here? Typically, what creates the memory ranges?
Could you provide all the logs?
In src/soc/intel/fsp_baytrail/northcluster.c there is a function nc_read_resources() which should add the appropriate resources. See if that is being called. If not, maybe another PCI device id needs to be added to that file to match on the appropriate driver.
Thanks,
Tuan Vu
Software Engineer
Insyde Software, Inc.
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we had this recently in another context. A log would be useful. It will try to find a bounce buffer if your payload will end up replacing parts of coreboot. What is your base/size for coreboot and for the payload?
ron
Am 01.07.2014 17:55, schrieb Tuan Vu:
Typically, what creates the memory ranges?
To a large degree the memory init code, which is closed source in the FSP model and thus unavailable to us.
When it comes to memory issues with FSP, it might be better to ask Intel directly.
Regards, Patrick
Tuan,
Your platform's northbirdge and GFX device ID is 0x0 and 0x0031? It's definitely wrong, I would suggest you to download the Bayley Bay platform's official UEFI BIOS from Intel IBL and flash it to you Bayley Bay platform, then see what's the correct ID.
On Fri, Jul 11, 2014 at 4:36 AM, Patrick Georgi patrick@georgi-clan.de wrote:
Am 01.07.2014 17:55, schrieb Tuan Vu:
Typically, what creates the memory ranges?
To a large degree the memory init code, which is closed source in the FSP model and thus unavailable to us.
When it comes to memory issues with FSP, it might be better to ask Intel directly.
Regards, Patrick
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