coreboot March 2014

coreboot@coreboot.org

57 participants
180 discussions

T60 - what went wrong?
by Marcus Moeller 07 Mar '14

07 Mar '14

Hi all, I have flashed my T60 according to the instructions on the wiki: The final flashing of the image showed the following error: ... Calibrating delay loop... delay loop is unreliable, trying to continue OK. Found chipset "Intel ICH7M". Enabling flash write... WARNING: SPI Configuration Lockdown activated. OK. Found SST flash chip "SST25VF016B.T60" (2048 kB, SPI) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -VE, -Vw), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading old flash chip contents... done. Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0 Reading current flash chip contents... done. spi_block_erase_52 failed during command execution at address 0x0 Reading current flash chip contents... done. Transaction error! spi_block_erase_d8 failed during command execution at address 0x1f0000 Reading current flash chip contents... done. spi_chip_erase_60 failed during command execution Reading current flash chip contents... done. spi_chip_erase_c7 failed during command execution FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- Which is quite similar to the error referenced in this mail: http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html So I tried to reboot, but the machine does not come up anymore. I am going to try to flash it, using an external prommer now, but I need to know what went wrong. Is there perhaps a prebuild image for initial flashing available, that I could use? Greets Marcus

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Build Coreboot Google Rambi SPD fail with ubuntu dash shell
by Kurt Qiao 07 Mar '14

07 Mar '14

Hi everyone, i just met a problem when i try to build coreboot google mainboard rambi, the spd.bin got incorrect content, and thanks for help from the great pgeorgi, finally problem solved. root cause: ubuntu 12.04 x86_64, and default shell use dash. solution: change to use bash as default, you can just 'sudo dpkg-reconfigure dash', and choose 'no'. the rambi spd make file may be updated to solve problem, hope my share can help other people like me, it really confuse me for couple of hours. -----below's in detail------------- i use ubuntu 12.04 x86_64, with gcc46 1. i git coreboot with git clone http://review.coreboot.org/p/coreboot 2. make menuconfig and select mainboard with google/rambi 3. make and everything goes well with build success. but when i check the spd.bin file, the content of spd.bin look like below: ---------spd.bin------- -e -n \x92 -e -n \x11 -e -n \x0b -e -n \x03 ... ... ... ----------------------------- check 'src/mainboard/google/rambi/spd/Makefile.inc', will see below: --------- ... # Include spd rom data $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ do echo -e -n "\\x$$c"; \ done; \ done > $@ ... ------------ when i modify the makefile to use 'printf' instead of 'echo -e -n', nothing in spd.bin after build. as patrick said, printf should also work when use dash. i still have no idea why this problem happened to me. thanks again for patrick and paule. BR, kurtqiao

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Re: [coreboot] coreboot on amd A85 can't work
by 陈军根 07 Mar '14

07 Mar '14

Hello Rudolf: Because coreboot can't work in F2A85-MLE ,I buy a new mainboard f2a85-M,and coreboot can run ok in my f2a85-m,also can boot ubuntu.But I find a strange question: when I plug my DIMM in DIMM_A1 or DIMM_B1,coreboot can't work ,and get the error messages "assertion Failed:file 'src/vendorcode/amd/agesa/f15tn/proc/mem/main/mmexcludedimm.c',line 236". but when I plug my DIMM in DIMM_A2 or DIMM_B2,coreboot work well; Did coreboot only support DIMM_A2 or DIMM_B2 in F2A85-M? I think this is also the reason why coreboot can't work in F2A85-MLE. Becuase F2A85-MLE only have DIMM_A1 and DIMM_B1. thanks 陈军根

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Re: [coreboot] PCI BAR resource problem
by Aaron Durbin 07 Mar '14

07 Mar '14

On Thu, Mar 6, 2014 at 5:06 AM, WANG Siyuan <wangsiyuanbuaa(a)gmail.com> wrote: > Hi, > I have a question about assigning PCI BAR resource. > In OliveHill, internal graphics(bus 0, dev 1, func 0)'s BAR0 (base address > register) is 0xe000000c. This is Graphic Memory Base Address. > I want to change this value to 0xc000000c. I have to do 2 things: > 1) alloc resource at 0xc0000000 whose length is 512M > 2) write the address value to internal graphics(bus 0, dev 1, func 0)'s BAR0 Is there a reason why you don't want to auto-assign the resource? > > for 1), maybe I can alloc resource when reading resource. > but I don't know how to deal with 2). It seems that, BAR's resources are > assigned by device's ops->set_resources() function. But I can't find this > function. There are a few options you can do. Let's use haswell's northbridge code as an example: http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/northbridge/i… First, you need to have a driver bound to your pci didvid. lines 470 thru 474 bind operations to pci didvid. Within the ops structure (lines 460-468) has the callbacks associated with the device. There, you'll find read_resources(), etc. I think your best bet is to define in your own read_resources(). In that call pci_dev_read_resources(dev) (line 389, e.g.). Then call find_resource(dev, PCI_BASE_ADDRESS_X) to obtain the associated resource for the BAR in question. res = find_resource(dev, PCI_BASE_ADDRESS_X); res->flags |= IORESOURCE_FIXED; res->base = 0xc0000000; Be sure you that pci_dev_set_resources() and pci_dev_enable_resources() in the set_resources() and enable_resources() callbacks, respectively. I think that should do what you need. I still am of the opinion you shouldn't be doing this manually. I'm wondering why you think it is needed? > > My question is > 1) when internal graphics(bus 0, dev 1, func 0)'s BAR0 is set to 0xe0000000? > How can I change it? > 2) How does coreboot alloc resources on 0xe0000000? I also can't find it. > > This is a general question: how does coreboot assign PCI device's BAR > resource? > For all non-fixed resources it will use the available address space for assigning those. Most of the hard work (at least more pointers into things to look at) is in pci_device.c: http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/pci_de… https://docs.google.com/a/google.com/presentation/d/1hwkzVrbAWUFqdEeWPaNSTp… That is from http://www.chromium.org/chromium-os/2014-firmware-summit which also has videos. Hope that helps. -Aaron

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Good fun
by ron minnich 06 Mar '14

06 Mar '14

http://k.lse.epita.fr/ Build yer own OS. Nice tutorial material. The author is cderbois(a)gmail.com ... k project ... corentin derbois ron

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PCI BAR resource problem
by WANG Siyuan 06 Mar '14

06 Mar '14

Hi, I have a question about assigning PCI BAR resource. In OliveHill, internal graphics(bus 0, dev 1, func 0)'s BAR0 (base address register) is 0xe000000c. This is Graphic Memory Base Address. I want to change this value to 0xc000000c. I have to do 2 things: 1) alloc resource at 0xc0000000 whose length is 512M 2) write the address value to internal graphics(bus 0, dev 1, func 0)'s BAR0 for 1), maybe I can alloc resource when reading resource. but I don't know how to deal with 2). It seems that, BAR's resources are assigned by device's ops->set_resources() function. But I can't find this function. My question is 1) when internal graphics(bus 0, dev 1, func 0)'s BAR0 is set to 0xe0000000? How can I change it? 2) How does coreboot alloc resources on 0xe0000000? I also can't find it. This is a general question: how does coreboot assign PCI device's BAR resource? Yours sincerely, WANG Siyuan

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Re: [coreboot] Set Top Boxes and Linux?
by Marc Jones 04 Mar '14

04 Mar '14

Gizmo would also make a good settop box. Marc On Mon, Mar 3, 2014 at 10:38 PM, Gregg Levine <gregg.drwho8(a)gmail.com> wrote: > Hello! > Nah, not that one. Ron is stressing a point that if someone, myself, > wants to try and get coreboot running on something, instead of a six > and seven, even eight year old hardware, or even older in some cases, > I should target one of the Chromebox family members. > > Back about the time the fellow that Carl-Daniel mentioned brought up > the subject, I was looking at doing that, because I needed a special > purpose platform, for, ah, special purposes. > > Back then Linux was target limited, and even the RasPi platform hadn't > even been envisioned. ARM was just beginning to take off, but > platforms were scarce. > > I originally looked at one of the Geode based platforms, because it > had several uncommitted I/O points on it, but the idea behind it > wasn't successful. > > I only asked about them yesterday, because there's been no discussion > whatsoever within the past few years. > ----- > Gregg C Levine gregg.drwho8(a)gmail.com > "This signature fought the Time Wars, time and again." > > > On Tue, Mar 4, 2014 at 12:20 AM, mrnuke <mr.nuke.me(a)gmail.com> wrote: >> On Monday, March 03, 2014 06:05:49 PM ron minnich wrote: >>> The new chromeboxes are pretty compelling and modern, so it's hard to see >>> the case for those very old boxes. >>> >> Blobs? >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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Re: [coreboot] how to model the Quark architecture
by Patrick Georgi 04 Mar '14

04 Mar '14

Am 2014-02-25 09:37, schrieb Stojsavljevic, Zoran: > Then to do minimalistic configuration of EDK2, and practically to > assemble Quark FSP. And to extract this FSP (SEC and PEI phases, which > is not easy at all) as source code from Quark EDK2 source code. > Incorporate this into Coreboot as Quark FSP source code. One problem is that in coreboot development we care about style (although there will be disagreement to which degree). And not just in a formal way (which indent could solve), but I'd rather not see things like (BIT31 | BIT30 | BIT29 | .. all the way down to .. | BIT 1 | BIT 0) in our tree. While looking terribly enterprisey, it's just terrible. Intel code, at least as far as it is public and not part of the Linux kernel, manages to collect all the horrible code standards in a single place. > Rest supposed to be straight forward... As Sage did it for IVB (using > IVB FSP as binary blob), similar idea for Quark, as then it complies > to Coreboot model, with all done by source code (strange to read this > for INTEL, isn't it!). "Luckily", Intel being Intel, the boot code is signed, so it's not as simple as it sounds. > Other idea is old one, from this thread, to incorporate the whole EDK2 > into Coreboot, but then, EDK2 is UEFI compliant BIOS, as my best > understanding is (why then to run Coreboot, instead from UEFI BIOS to > transition to legacy GRUB 0.97 with some security features > incorporated)! Indeed. There is no need to bloat coreboot by factor 6. I measured. Regards, Patrick

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Re: [coreboot] Set Top Boxes and Linux?
by mrnuke 04 Mar '14

04 Mar '14

On Monday, March 03, 2014 06:05:49 PM ron minnich wrote: > The new chromeboxes are pretty compelling and modern, so it's hard to see > the case for those very old boxes. > Blobs?

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Re: [coreboot] Set Top Boxes and Linux?
by Carl-Daniel Hailfinger 04 Mar '14

04 Mar '14

Hi Gregg, Am 04.03.2014 02:43 schrieb Gregg Levine: > Hello! > I've not seen anything (so far) concerning the ideas of installing > Core Boot, into a system originally designated as a Set Top box. Is > the idea still an active one? Or did it go into hibernation? Joseph Smith was working on this and IIRC he succeeded in having coreboot on some settop boxes: www.settoplinux.org He kind of disappeared from the mailing list, though. I hope he's still alive. > And I'm bringing this up, not just because of prior discussions, but > because it happens I have here one of those penguins that were given > out at the former Linux World Expo events, and it says "TV Linux > Alliance" on its middle. Which model? Regards, Carl-Daniel -- http://www.hailfinger.org/

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coreboot March 2014