coreboot March 2014

coreboot@coreboot.org

57 participants
180 discussions

Re: [coreboot] I've turned on paging as a test
by ron minnich 11 Mar '14

11 Mar '14

Ah well, too bad. This CL may end up as an historical curiousity. But that said most OSes I've work on last 10 years use PTEs for lots of this control. I'll check out that table. ron On Mon, Mar 10, 2014 at 5:36 PM, Aaron Durbin <adurbin(a)google.com> wrote: > On Mon, Mar 10, 2014 at 5:32 PM, ron minnich <rminnich(a)gmail.com> wrote: > > I'm *pretty* *sure* that you can use the PATs as an alternative to > MTRRs. I > > am going to dig a bit. It would sure make our life easier if we could > live > > without all this MTRR fuss. We keep having to tweak the code and it's > never > > been fun. > > > > And I like the idea of write-protecting coreboot code. > > In Intel manuals, there's a table named "Effective Page-Level Memory > Types for Pentium III and More Recent Processor Families." There's a > table that lists the combination of PAT and MTRR. It's not a an > alternative. It describes how those settings interact. > > Anyway, depending on what exactly you want to solve there may be other > solutions to your problem. > > -Aaron >

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Re: [coreboot] I've turned on paging as a test
by Aaron Durbin 11 Mar '14

11 Mar '14

On Mon, Mar 10, 2014 at 5:32 PM, ron minnich <rminnich(a)gmail.com> wrote: > I'm *pretty* *sure* that you can use the PATs as an alternative to MTRRs. I > am going to dig a bit. It would sure make our life easier if we could live > without all this MTRR fuss. We keep having to tweak the code and it's never > been fun. > > And I like the idea of write-protecting coreboot code. In Intel manuals, there's a table named "Effective Page-Level Memory Types for Pentium III and More Recent Processor Families." There's a table that lists the combination of PAT and MTRR. It's not a an alternative. It describes how those settings interact. Anyway, depending on what exactly you want to solve there may be other solutions to your problem. -Aaron

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Re: [coreboot] I've turned on paging as a test
by ron minnich 11 Mar '14

11 Mar '14

I'm *pretty* *sure* that you can use the PATs as an alternative to MTRRs. I am going to dig a bit. It would sure make our life easier if we could live without all this MTRR fuss. We keep having to tweak the code and it's never been fun. And I like the idea of write-protecting coreboot code. ron

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Re: [coreboot] I've turned on paging as a test
by Aaron Durbin 11 Mar '14

11 Mar '14

On Mon, Mar 10, 2014 at 5:10 PM, ron minnich <rminnich(a)gmail.com> wrote: > By PAT do you mean the old-school Attribute table or the per-page bits? I meant this: http://en.wikipedia.org/wiki/Page_attribute_table which is per-page bits, IIRC which index into an array of types. I could be wrong; I assumed one needed MTRRs all the time. What happens if MTRRs are disabled entirely and PAT is used? Is that the magic path to getting the granularity one desires? That's a combination I'm not familiar with. -Aaron

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Re: [coreboot] I've turned on paging as a test
by ron minnich 11 Mar '14

11 Mar '14

By PAT do you mean the old-school Attribute table or the per-page bits? ron

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Re: [coreboot] I've turned on paging as a test
by Aaron Durbin 11 Mar '14

11 Mar '14

On Mon, Mar 10, 2014 at 5:00 PM, ron minnich <rminnich(a)gmail.com> wrote: > I think the bigger question that we need to answer, now that we know > it's doable, is whether we want paging or not. We may not. I was hoping > it would give us a more convenient way to cover cache-disabled, write-back, > and write-through ranges without all the fuss of MTRRs. But there may be > other issues that make it impractical. I'm open to discussion. > I assume you were wanting use PAT to cover different regions? Sadly, the precedence for "upgrading" the caching type is from UC to WC. There is no way to turn a UC MTRR region into a WP region through PAT. At least that's what I recall when I looked it up a couple of weeks ago. -Aaron

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Re: [coreboot] I've turned on paging as a test
by ron minnich 11 Mar '14

11 Mar '14

I think the bigger question that we need to answer, now that we know it's doable, is whether we want paging or not. We may not. I was hoping it would give us a more convenient way to cover cache-disabled, write-back, and write-through ranges without all the fuss of MTRRs. But there may be other issues that make it impractical. I'm open to discussion. Thanks ron

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Re: [coreboot] I've turned on paging as a test
by Aaron Durbin 11 Mar '14

11 Mar '14

On Mon, Mar 10, 2014 at 4:50 PM, ron minnich <rminnich(a)gmail.com> wrote: > > > > On Mon, Mar 10, 2014 at 4:37 PM, Aaron Durbin <adurbin(a)chromium.org> wrote: >> >> >> You'll find that once you try to write coreboot tables, things will >> page fault as well: >> >> 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES >> > > > Yep. Well, so much for catching NULL pointers. We can do that on ARM, but > not x86. > > It's hard to complain. When the 8086 came out, the idea that it might do > paging was many years off. > I think it could be changed. I was just pointing out that after you get past the initial NULL deref there is another one lurking. -Aaron

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Re: [coreboot] I've turned on paging as a test
by ron minnich 11 Mar '14

11 Mar '14

On Mon, Mar 10, 2014 at 4:37 PM, Aaron Durbin <adurbin(a)chromium.org> wrote: > > You'll find that once you try to write coreboot tables, things will > page fault as well: > > 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES > Yep. Well, so much for catching NULL pointers. We can do that on ARM, but not x86. It's hard to complain. When the 8086 came out, the idea that it might do paging was many years off. ron

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Re: [coreboot] I've turned on paging as a test
by Aaron Durbin 11 Mar '14

11 Mar '14

On Mon, Mar 10, 2014 at 3:24 PM, ron minnich <rminnich(a)gmail.com> wrote: > Which option ROMs? newish ones or 3c509 :-)? Ah well guess I believe you. I > guess I never needed it because in my main uses we did not use or want > option roms -- we loaded Linux and there was no need there. Running some > option rom in an 8086 mode was never desired ... > > We've gone backwards in some ways from when Linux was our bootstrap. You'll find that once you try to write coreboot tables, things will page fault as well: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000001fffffff: RAM 4. 0000000020000000-00000000200fffff: RESERVED 5. 0000000020100000-000000007ae6dfff: RAM 6. 000000007ae6e000-000000007affffff: CONFIGURATION TABLES 7. 000000007b000000-000000007fffffff: RESERVED 8. 00000000e0000000-00000000efffffff: RESERVED 9. 00000000feb00000-00000000febfffff: RESERVED 10. 00000000fed01000-00000000fed01fff: RESERVED 11. 00000000fed03000-00000000fed03fff: RESERVED 12. 00000000fed05000-00000000fed05fff: RESERVED 13. 00000000fed08000-00000000fed08fff: RESERVED 14. 00000000fed0c000-00000000fed0ffff: RESERVED 15. 00000000fed1c000-00000000fed1cfff: RESERVED Notice that first entry? > > ron > > > On Mon, Mar 10, 2014 at 3:21 PM, Stefan Reinauer > <stefan.reinauer(a)coreboot.org> wrote: >> >> * ron minnich <rminnich(a)gmail.com> [140310 22:43]: >> > Now you've just made me sad. >> > >> > OK, given that in the beginning times we never supplied this little >> > tidbit, who >> > or what needs it? It looks like another memory turd whose time has gone. >> > >> > ron >> >> It's needed by some option roms. See void dev_initialize(void) in >> src/device/device.c >> >> >> Stefan >> >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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coreboot March 2014