coreboot March 2013

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Patch set updated for coreboot: 9919f0e lynxpoint: Change sata.c to get rid of #if
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2818 -gerrit commit 9919f0e94222eb92504dddb41c7c34e4346ff379 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 8 17:17:33 2013 -0800 lynxpoint: Change sata.c to get rid of #if This uses the new helper function added earlier. Change-Id: Icdb5d5c51f70eeb7e39e11062276ceb3eb3d9473 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/sata.c | 41 ++++++++++++++++------------------ 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 25eb94f..8912865 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -137,11 +137,11 @@ static void sata_init(struct device *dev) reg32 |= 1 << 5; /* BWG step 9 */ reg32 |= 1 << 18; /* BWG step 10 */ reg32 |= 1 << 29; /* BWG step 11 */ -#if CONFIG_INTEL_LYNXPOINT_LP - reg32 &= ~((1 << 31) | (1 << 30)); - reg32 |= 1 << 23; - reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ -#endif + if (pch_is_lp()) { + reg32 &= ~((1 << 31) | (1 << 30)); + reg32 |= 1 << 23; + reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ + } pci_write_config32(dev, 0x98, reg32); /* Setup register 9Ch */ @@ -162,9 +162,8 @@ static void sata_init(struct device *dev) reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS -#if CONFIG_INTEL_LYNXPOINT_LP - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY -#endif + if (pch_is_lp()) + reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); @@ -172,12 +171,11 @@ static void sata_init(struct device *dev) (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); -#if CONFIG_INTEL_LYNXPOINT_LP /* Enable DEVSLP */ - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); -#else - reg32 &= ~0x00000002; -#endif + if (pch_is_lp()) + reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + else + reg32 &= ~0x00000002; write32(abar + 0x24, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); @@ -239,11 +237,10 @@ static void sata_init(struct device *dev) /* Power Optimizer */ /* Step 1 */ -#if CONFIG_INTEL_LYNXPOINT_LP - sir_write(dev, 0x64, 0x883c9003); -#else - sir_write(dev, 0x64, 0x883c9001); -#endif + if (pch_is_lp()) + sir_write(dev, 0x64, 0x883c9003); + else + sir_write(dev, 0x64, 0x883c9001); /* Step 2: SIR 68h[15:0] = 880Ah */ reg32 = sir_read(dev, 0x68); @@ -268,10 +265,10 @@ static void sata_init(struct device *dev) /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); -#if CONFIG_INTEL_LYNXPOINT_LP - sir_write(dev, 0x54, 0xcf000f0f); - sir_write(dev, 0x58, 0x00190000); -#endif + if (pch_is_lp()) { + sir_write(dev, 0x54, 0xcf000f0f); + sir_write(dev, 0x58, 0x00190000); + } reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16);

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Patch set updated for coreboot: 58ac712 rmodule: add string functions to rmodules class
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2821 -gerrit commit 58ac7123bc9099a6d0c862ec6de699e66aceb278 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 16:56:34 2013 -0600 rmodule: add string functions to rmodules class The standard string functions memcmp(), memset(), and memcpy() are needed by most programs. The rmodules class provides a way to build objects for the rmodules class. Those programs most likely need the string functions. Therefore provide those standard functions to be used by any generic rmodule program. Change-Id: I2737633f03894d54229c7fa7250c818bf78ee4b7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/lib/Makefile.inc | 3 +++ src/lib/Makefile.inc | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 49d7e9e..82f4e62 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -20,4 +20,7 @@ smm-y += memset.c smm-y += memcpy.c smm-y += rom_media.c +rmodules-y += memset.c +rmodules-y += memcpy.c + $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index fe04e43..fe57f9f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -29,12 +29,15 @@ bootblock-y += memcmp.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c +rmodules-y += memset.c endif romstage-y += memchr.c ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) romstage-y += memcpy.c +rmodules-y += memcpy.c endif romstage-y += memcmp.c +rmodules-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c #romstage-y += lzmadecode.c @@ -126,3 +129,4 @@ $(strip $(1)): $(strip $(2)) $$(RMODULE_LDSCRIPT) $$(obj)/ldoptions endef endif +

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Patch set updated for coreboot: 15f7993 rmodule: correct ordering of bss clearing
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2822 -gerrit commit 15f7993590b90e61ee85ce4bf1d9a3e8b5b5787f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 17:00:39 2013 -0600 rmodule: correct ordering of bss clearing This patch fixes an issue for rmodules which are copied into memory at the final load/link location. If the bss section is cleared for that rmodule the relocation could not take place properly since the relocation information was wiped by act of clearing the bss. The reason is that the relocation information resides at the same address as the bss section. Correct this issue by performing the relocation before clearing the bss. Change-Id: I01a124a8201321a9eaf6144c743fa818c0f004b4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/rmodule.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 60c89f0..d36f9f3 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -241,14 +241,18 @@ static int __rmodule_load(void *base, struct rmodule *module, int clear_bss) * In order to load the module at a given address, the following steps * take place: * 1. Copy payload to base address. - * 2. Clear the bss segment. - * 3. Adjust relocations within the module to new base address. + * 2. Adjust relocations within the module to new base address. + * 3. Clear the bss segment last since the relocations live where + * the bss is. If an rmodule is being loaded from its load + * address the relocations need to be processed before the bss. */ module->location = base; rmodule_copy_payload(module); + if (rmodule_relocate(module)) + return -1; if (clear_bss) rmodule_clear_bss(module); - return rmodule_relocate(module); + return 0; } int rmodule_load(void *base, struct rmodule *module)

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Patch merged into coreboot/master: 94998c4 lynxpoint: Add cbfs_load_payload() implementation
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit 94998c4d3fa1c9f1f0aaf3623a070e8c7e364f8b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 22 13:54:12 2013 -0600 lynxpoint: Add cbfs_load_payload() implementation SPI accesses can be slow depending on the setup and the access pattern. The current SPI hardware setup to cache and prefetch. The alternative cbfs_load_payload() function takes advantage of the caching in the CPU because the ROM is cached as write protected as well as the SPI's hardware's caching/prefetching implementation. The CPU will fetch consecutive aligned cachelines which will hit the ROM as cacheline-aligned addresses. Once the payload is mirrored into RAM the segment loading can take place by reading RAM instead of ROM. With the alternative cbfs_load_payload() the boot time on a baskingridge board saves ~100ms. This savings is observed using cbmem.py after performing warm reboots and looking at TS_SELFBOOT_JUMP (99) entries. This is booting with a depthcharge payload whose payload file fits within the SMM_DEFAULT_SIZE (0x10000 bytes). Datapoints with TS_LOAD_PAYLOAD (90) & TS_SELFBOOT_JUMP (99) cbmem entries: Baseline Alt -------- -------- 90:3,859,310 (473) 90:3,863,647 (454) 99:3,989,578 (130,268) 99:3,888,709 (25,062) 90:3,899,450 (477) 90:3,860,926 (463) 99:4,029,459 (130,008) 99:3,890,583 (29,657) 90:3,834,600 (466) 90:3,890,564 (465) 99:3,964,535 (129,934) 99:3,920,213 (29,649) Booted baskingridge many times and observed 100ms reduction in TS_SELFBOOT_JUMP times (time to load payload). Change-Id: I27b2dec59ecd469a4906b4179b39928e9201db81 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Tue Mar 19 19:14:14 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Mar 19 20:21:49 2013, giving +2 See http://review.coreboot.org/2783 for details. -gerrit

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New patch to review for coreboot: d3e6ce1 Remove __PRE_RAM__ guard around log2 prototype
by David Hendricks 19 Mar '13

19 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2832 -gerrit commit d3e6ce1ffd918180713069e30b128abc289ceeae Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 19 11:55:44 2013 -0700 Remove __PRE_RAM__ guard around log2 prototype The prototype for log2() should be visible everywhere except romcc, which is handled by an #ifndef __ROMCC__ just above this guard. Change-Id: I713569ed95bd5427db0e5dc3e3f0499bd1914297 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/lib.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/include/lib.h b/src/include/lib.h index 9d81085..31b8669 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -24,10 +24,8 @@ #include <stdint.h> #ifndef __ROMCC__ /* romcc doesn't support prototypes. */ -#ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */ -/* Defined in src/lib/clog2.c */ +/* Defined in src/lib/clog2.c (note: conflicts with romcc_io.h) */ unsigned long log2(unsigned long x); -#endif /* Defined in src/lib/lzma.c */ unsigned long ulzma(unsigned char *src, unsigned char *dst);

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Patch set updated for coreboot: baa3d3c google/snow: workaround a buggy recovery mode GPIO reading
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2826 -gerrit commit baa3d3c366630243bf074bde32e82964d07ddbf7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Mar 18 23:27:09 2013 -0700 google/snow: workaround a buggy recovery mode GPIO reading We don't really have a recovery mode GPIO. Instead it's fed into the SoC by another chip. And for whatever reason we're reading a weird value. Hard-code as a workaround. Change-Id: I02703e80c953d463706757c9398b6afda4941f8d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 1a98244..6694b59 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -63,7 +63,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: active high */ gpios->gpios[1].port = EXYNOS5_GPY1; gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); +// gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); + gpios->gpios[1].value = 0; strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); /* Lid: the "switch" comes from the EC */

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Patch set updated for coreboot: ba1feda armv7/exynos/snow: new cache maintenance API
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2729 -gerrit commit ba1fedae50b154b6a3b2da40fec223844b9fb415 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 14 15:24:57 2013 -0700 armv7/exynos/snow: new cache maintenance API This adds a new API for cache maintenance operations. The idea is to be more explicit about operations that are going on so it's easier to manage branch predictor, cache, and TLB cleans and invalidations. Also, this adds some operations that were missing but required early on, such as branch predictor invalidation. Instruction and sync barriers were wrong earlier as well since the imported API assumed we compield with -march=armv5 (which we don't) and was missing wrappers for the native ARMv7 ISB/DSB/DMB instructions. For now, this is a start and it gives us something we can easily use in libpayload for doing things like cleaning and invalidating dcache when doing DMA transfers. TODO: - Set cache policy explicitly before re-enabling. Right now it's left at default. - Finish deprecating old cache maintenance API. - We do an extra icache/dcache flush when going from bootblock to romstage. Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 71 +++++++++ src/arch/armv7/include/arch/cache.h | 231 ++++++++++++++++++++++++++++++ src/arch/armv7/include/arch/io.h | 3 +- src/arch/armv7/include/cache.h | 56 -------- src/arch/armv7/include/system.h | 6 +- src/arch/armv7/lib/Makefile.inc | 6 + src/arch/armv7/lib/cache-cp15.c | 3 +- src/arch/armv7/lib/cache.c | 178 +++++++++++++++++++++++ src/arch/armv7/lib/cache_v7.c | 2 +- src/arch/armv7/stages.c | 5 +- src/cpu/samsung/exynos5250/Makefile.inc | 1 - src/cpu/samsung/exynos5250/exynos_cache.c | 11 -- src/mainboard/google/snow/romstage.c | 26 +--- 13 files changed, 502 insertions(+), 97 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 0132b87..7012e17 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -20,6 +20,7 @@ */ #include <bootblock_common.h> +#include <arch/cache.h> #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> @@ -27,6 +28,58 @@ #include "stages.c" +static void armv7_invalidate_caches(void) +{ + uint32_t clidr; + int level; + + /* Invalidate branch predictor */ + bpiall(); + + /* Iterate thru each cache identified in CLIDR and invalidate */ + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x0: + /* no cache */ + break; + case 0x1: + /* icache only */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + break; + case 0x2: + case 0x4: + /* dcache only or unified cache */ + dcache_invalidate_all(); + break; + case 0x3: + /* separate icache and dcache */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + + csselr = level < 1; + write_csselr(csselr); + dcache_invalidate_all(); + break; + default: + /* reserved */ + break; + } + } + + /* Invalidate TLB */ + /* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction + * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't + * really seem true for Cortex-A15? */ + tlb_invalidate_all(); +} + static int boot_cpu(void) { /* @@ -41,6 +94,24 @@ void main(void) { const char *stage_name = "fallback/romstage"; void *entry; + uint32_t sctlr; + + /* Globally disable MMU, caches, and branch prediction (these should + * be disabled by default on reset) */ + sctlr = read_sctlr(); + sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); + write_sctlr(sctlr); + + armv7_invalidate_caches(); + + /* + * Re-enable caches and branch prediction. MMU will be set up later. + * Note: If booting from USB, we need to disable branch prediction + * before copying from USB into RAM (FIXME: why?) + */ + sctlr = read_sctlr(); + sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I; + write_sctlr(sctlr); if (boot_cpu()) { bootblock_cpu_init(); diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h new file mode 100644 index 0000000..5125b8c --- /dev/null +++ b/src/arch/armv7/include/arch/cache.h @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef ARMV7_CACHE_H +#define ARMV7_CACHE_H + +/* SCTLR bits */ +#define SCTLR_M (1 << 0) /* MMU enable */ +#define SCTLR_A (1 << 1) /* Alignment check enable */ +#define SCTLR_C (1 << 2) /* Data/unified cache enable */ +/* Bits 4:3 are reserved */ +#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */ +/* Bit 6 is reserved */ +#define SCTLR_B (1 << 7) /* Endianness */ +/* Bits 9:8 */ +#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */ +#define SCTLR_Z (1 << 11) /* Branch prediction enable */ +#define SCTLR_I (1 << 12) /* Instruction cache enable */ +#define SCTLR_V (1 << 13) /* Low/high exception vectors */ +#define SCTLR_RR (1 << 14) /* Round Robin select */ +/* Bits 16:15 are reserved */ +#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */ +/* Bit 18 is reserved */ +/* Bits 20:19 reserved virtualization not supported */ +#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ +#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission + implies PL1 XN */ +#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */ +#define SCTLR_U (1 << 22) /* Unaligned access behavior */ +#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */ +#define SCTLR_EE (1 << 25) /* Exception endianness */ +/* Bit 26 is reserved */ +#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */ +#define SCTLR_TRE (1 << 28) /* TEX remap enable */ +#define SCTLR_AFE (1 << 29) /* Access flag enable */ +#define SCTLR_TE (1 << 30) /* Thumb exception enable */ +/* Bit 31 is reserved */ + +/* + * Sync primitives + */ + +/* data memory barrier */ +static inline void dmb(void) +{ + asm volatile ("dmb" : : : "memory"); +} + +/* data sync barrier */ +static inline void dsb(void) +{ + asm volatile ("dsb" : : : "memory"); +} + +/* instruction sync barrier */ +static inline void isb(void) +{ + asm volatile ("isb" : : : "memory"); +} + +/* + * Low-level TLB maintenance operations + */ + +/* invalidate entire data TLB */ +static inline void dtlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); +} + +/* invalidate entire instruction TLB */ +static inline void itlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); +} + +/* invalidate entire unified TLB */ +static inline void tlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); +} + +/* + * Low-level cache maintenance operations + */ + +/* branch predictor invalidate all */ +static inline void bpiall(void) +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); +} + +/* data cache clean and invalidate by MVA to PoC */ +static inline void dccimvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva)); +} + +/* data cache invalidate by set/way */ +static inline void dccisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val)); +} + +/* data cache invalidate by set/way */ +static inline void dcisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); +} + +/* data cache clean by MVA to PoC */ +static inline void dccmvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva)); +} + +/* data cache invalidate by MVA to PoC */ +static inline void dcimvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); +} + +/* instruction cache invalidate all by PoU */ +static inline void iciallu(void) +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); +} + +/* + * Cache co-processor (CP15) access functions + */ + +/* read cache level ID register (CLIDR) */ +static inline uint32_t read_clidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + return val; +} + +/* read cache size ID register register (CCSIDR) */ +static inline uint32_t read_ccsidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +/* read cache size selection register (CSSELR) */ +static inline uint32_t read_csselr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +/* write to cache size selection register (CSSELR) */ +static inline void write_csselr(uint32_t val) +{ + /* + * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd) + * Bit 0 - 0 = data or unified cache, 1 = instruction cache + */ + asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val)); + isb(); /* ISB to sync the change to CCSIDR */ +} + +/* read system control register (SCTLR) */ +static inline unsigned int read_sctlr(void) +{ + unsigned int val; + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "cc"); + return val; +} + +/* write system control register (SCTLR) */ +static inline void write_sctlr(unsigned int val) +{ + asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc"); + isb(); +} + +/* + * Cache maintenance API + */ + +/* invalidate all TLBs */ +void tlb_invalidate_all(void); + +/* clean and invalidate entire dcache on current level (given by CCSELR) */ +void dcache_clean_invalidate_all(void); + +/* invalidate entire dcache on current level (given by CCSELR) */ +void dcache_invalidate_all(void); + +/* invalidate and clean dcache by machine virtual address to PoC */ +void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); + +/* invalidate entire icache on current level (given by CSSELR) */ +void icache_invalidate_all(void); + +/* MMU setup by machine virtual address */ +void mmu_setup_by_mva(unsigned long start, unsigned long size); + +#endif /* ARMV7_CACHE_H */ diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index 3bbd529..623c305 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -21,6 +21,7 @@ #define __ASM_ARM_IO_H #include <types.h> +#include <arch/cache.h> /* for dmb() */ #include <arch/byteorder.h> static inline void sync(void) @@ -96,7 +97,7 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ -#define dmb() __asm__ __volatile__ ("" : : : "memory") +//#define dmb() __asm__ __volatile__ ("" : : : "memory") #define __iormb() dmb() #define __iowmb() dmb() diff --git a/src/arch/armv7/include/cache.h b/src/arch/armv7/include/cache.h deleted file mode 100644 index cf8fb5a..0000000 --- a/src/arch/armv7/include/cache.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -/* - * Invalidate L2 Cache using co-proc instruction - */ -static inline void invalidate_l2_cache(void) -{ - unsigned int val=0; - - asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" - : : "r" (val) : "cc"); - isb(); -} - -void l2_cache_enable(void); -void l2_cache_disable(void); - -/* - * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We - * use that value for aligning DMA buffers unless the board config has specified - * an alternate cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 64 -#endif - -inline void dram_bank_mmu_setup(unsigned long start, unsigned long size); - -#endif /* _ASM_CACHE_H */ diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index 053df8d..f3e9b6b 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -43,13 +43,15 @@ */ #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" -#define isb() __asm__ __volatile__ ("" : : : "memory") +/* FIXME: conflicts with new implementation in cache.c */ +//#define isb() __asm__ __volatile__ ("" : : : "memory") #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #define arch_align_stack(x) (x) #ifndef __ASSEMBLER__ +#include <arch/cache.h> /* for isb() */ static inline unsigned int get_cr(void) { unsigned int val; @@ -97,6 +99,8 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop); void mmu_setup(unsigned long start, unsigned long size); +void v7_inval_tlb(void); + void arm_init_before_mmu(void); /* diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 508f776..c248b9e 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,8 +1,12 @@ +#FIXME: cache_v7 and cache-cp15 will go away eventually + bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c +bootblock-y += cache.c bootblock-y += cache_v7.c bootblock-y += cache-cp15.c +romstage-y += cache.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c @@ -14,7 +18,9 @@ ramstage-y += div0.c #ramstage-y += memcpy.S #ramstage-y += memset.S ramstage-y += syslib.c +ramstage-y += cache.c ramstage-y += cache_v7.c +ramstage-y += cache-cp15.c #FIXME(dhendrix): should this be a config option? romstage-y += eabi_compat.c diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index e08ea57..32f3c79 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -123,8 +123,7 @@ inline void mmu_setup(unsigned long start, unsigned long size_mb) int i; u32 reg; - arm_init_before_mmu(); - +// arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c new file mode 100644 index 0000000..62ae755 --- /dev/null +++ b/src/arch/armv7/lib/cache.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Low-level cache operations for ARMv7 + */ + +#include <types.h> + +#include <arch/cache.h> + +#define bitmask(high, low) ((1UL << (high)) + \ + ((1UL << (high)) - 1) - ((1UL << (low)) - 1)) + +/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */ +/* FIXME: src/include/lib.h is difficult to work with due to romcc */ +static unsigned long log2(unsigned long u) +{ + int i = 0; + + while (u >>= 1) + i++; + + return i; +} + +void tlb_invalidate_all(void) +{ + /* + * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction + * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't + * really seem true for Cortex-A15? + */ + tlbiall(); + dtlbiall(); + itlbiall(); + isb(); + dsb(); +} + +void icache_invalidate_all(void) +{ + /* icache can be entirely invalidated with one operation. + * Note: If branch predictors are architecturally-visible, ICIALLU + * also performs a BPIALL operation (B2-1283 in arch manual) + */ + iciallu(); + isb(); +} + +enum dcache_op { + OP_DCCISW, + OP_DCISW +}; + +/* do a dcache operation on entire cache by set/way */ +static void dcache_op_set_way(enum dcache_op op) +{ + uint32_t ccsidr; + unsigned int associativity, num_sets, linesize_bytes; + unsigned int set, way; + unsigned int level; + + level = (read_csselr() >> 1) & 0x7; + + /* + * dcache must be invalidated by set/way for portability since virtual + * memory mapping is system-defined. The number of sets and + * associativity is given by CCSIDR. We'll use DCISW to invalidate the + * dcache. + */ + ccsidr = read_ccsidr(); + + /* FIXME: rounding up required here? */ + num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1; + associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1; + /* FIXME: do we need to use CTR.DminLine here? */ + linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; + + /* + * Set/way operations require an interesting bit packing. See section + * B4-35 in the ARMv7 Architecture Reference Manual: + * + * A: Log2(associativity) + * B: L+S + * L: Log2(linesize) + * S: Log2(num_sets) + * + * The bits are packed as follows: + * 31 31-A B B-1 L L-1 4 3 1 0 + * |---|-------------|--------|-------|-----|-| + * |Way| zeros | Set | zeros |level|0| + * |---|-------------|--------|-------|-----|-| + */ + for (way = 0; way < associativity; way++) { + for (set = 0; set < num_sets; set++) { + uint32_t val = 0; + val |= way << (32 - log2(associativity)); + val |= set << log2(linesize_bytes); + val |= level << 1; + switch(op) { + case OP_DCCISW: + dccisw(val); + break; + case OP_DCISW: + dcisw(val); + break; + default: + break; + } + } + } + + dsb(); +} + +void dcache_clean_invalidate_all(void) +{ + dcache_op_set_way(OP_DCCISW); +} + +void dcache_invalidate_all(void) +{ + dcache_op_set_way(OP_DCISW); +} + +static unsigned int line_bytes(void) +{ + uint32_t ccsidr; + unsigned int size; + + ccsidr = read_ccsidr(); + /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ + size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + size *= sizeof(unsigned int); /* bytes per line */ + + return size; +} + +void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) +{ + unsigned long line, i; + + line = line_bytes(); + for (i = addr & ~(line - 1); i < addr + len - 1; i += line) + dccimvac(addr); +} + +/* FIXME: wrapper around imported mmu_setup() for now */ +extern void mmu_setup(unsigned long start, unsigned long size); +void mmu_setup_by_mva(unsigned long start, unsigned long size) +{ + mmu_setup(start, size); +} diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c index 31072c7..1764351 100644 --- a/src/arch/armv7/lib/cache_v7.c +++ b/src/arch/armv7/lib/cache_v7.c @@ -226,7 +226,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* Invalidate TLB */ -static void v7_inval_tlb(void) +void v7_inval_tlb(void) { /* Invalidate entire unified TLB */ asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c index c37c1dd..038ed7c 100644 --- a/src/arch/armv7/stages.c +++ b/src/arch/armv7/stages.c @@ -33,6 +33,7 @@ #include <arch/stages.h> #include <arch/armv7/include/common.h> +#include <arch/cache.h> void stage_entry(void) { @@ -50,10 +51,10 @@ void stage_exit(void *addr) /* make sure any code we installed is written to memory. Not all ARM have * unified caches. */ - flush_dcache_all(); + dcache_clean_invalidate_all(); /* Because most stages copy code to memory, it's a safe and hygienic thing * to flush the icache here. */ - invalidate_icache_all(); + icache_invalidate_all(); doit(); } diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 2774b12..961b719 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -30,7 +30,6 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c -ramstage-y += exynos_cache.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index 7f4effe..2cb918d 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -33,17 +33,6 @@ enum l2_cache_params { CACHE_DATA_RAM_LATENCY = (2<<0) }; - -/* FIXME(dhendrix): maybe move this to a romstage-specific file? */ -#ifdef __PRE_RAM__ -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - /* can't use it anyway -- it has dependencies we have to fix. */ - //dcache_enable(); -} -#endif - /* * Set L2 cache parameters */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index ea2feec..bfb4156 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -18,12 +18,12 @@ */ #include <types.h> -#include <system.h> -#include <cache.h> +#include <armv7.h> #include <cbfs.h> #include <common.h> +#include <arch/cache.h> #include <arch/gpio.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -52,20 +52,6 @@ static int board_wakeup_permitted(void) } #endif -/* - * Set/clear program flow prediction and return the previous state. - */ -static int config_branch_prediction(int set_cr_z) -{ - unsigned int cr; - - /* System Control Register: 11th bit Z Branch prediction enable */ - cr = get_cr(); - set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); - - return cr & CR_Z; -} - static void initialize_s5p_mshc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -95,10 +81,6 @@ void main(void) int ret; void *entry; - /* FIXME: if we boot from USB, we need to disable branch prediction - * before copying from USB into RAM */ - config_branch_prediction(1); - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ /* Clock must be initialized before console_init, otherwise you may need @@ -108,7 +90,6 @@ void main(void) system_clock_init(mem, arm_ratios); console_init(); - /* * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. * Also, we should only call power_init() on cold boot. @@ -132,7 +113,8 @@ void main(void) while(1); } - mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + /* Set up MMU and caches */ + mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); initialize_s5p_mshc();

1 0

Patch set updated for coreboot: d08a9b3 google/snow: fix a GPIO array index
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2825 -gerrit commit d08a9b37cd48993e0987ff823abc1fe39efd9e32 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Mar 18 21:54:13 2013 -0700 google/snow: fix a GPIO array index This fixes a trivial error with the recovery mode GPIO index. Change-Id: I7290c1e23cdddaf91c9021d4e4252c0c772b6eab Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 14da49c..1a98244 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -63,7 +63,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: active high */ gpios->gpios[1].port = EXYNOS5_GPY1; gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); + gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); /* Lid: the "switch" comes from the EC */

1 0

Patch set updated for coreboot: 639320f snow: dump cache config in ramstage
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2770 -gerrit commit 639320fd3ab4153a93b1355ae3332b63ab41af1b Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Mar 15 18:30:29 2013 -0700 snow: dump cache config in ramstage ** do not submit** This just prints some cache config info. Change-Id: I103c519bde7cad467f4175c7a1b803d8e1bc0006 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/ramstage.c | 131 +++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index be5216f..e4d53cf 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,12 +23,143 @@ #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/power.h> +#include <system.h> /* FIXME: for testing cache */ +static void cp_delay(void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++) + nop(); + asm volatile("" : : : "memory"); +} + +static inline uint32_t read_clidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + isb(); + return val; +} + +static inline uint32_t read_ccsidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); + isb(); + return val; +} + +static inline uint32_t read_csselr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val)); + isb(); + return val; +} + +/* Write to Cache Size Selection Register (CSSELR) */ +static inline void write_csselr(uint32_t val) +{ + /* + * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd) + * Bit 0 - 0 = data or unified cache, 1 = instruction cache + */ + asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val)); + isb(); +} + +#ifndef __mask +# define __mask(high, low) ((1UL << (high)) + \ + (((1UL << (high)) - 1) - ((1UL << (low)) - 1))) +#endif + +static void foo(void) +{ + uint32_t clidr, ccselr, ccsidr; + int level, assoc, nsets, linesize; + + /* algorithm described by B.2.2.1 in ArmV7 Arch manual */ + clidr = read_clidr(); + printk(BIOS_DEBUG, "%s: clidr: 0x%08x\n", __func__, clidr); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + + ccselr = ccsidr = 0; /* FIXME: paranoia */ + switch(ctype) { + case 0x0: + /* no cache */ + printk(BIOS_DEBUG, "L%d has no cache\n", level + 1); + break; + case 0x1: + /* icache only */ + ccselr = (level << 1) | 1; + write_csselr(ccselr); + ccsidr = read_ccsidr(); + printk(BIOS_DEBUG, "L%d (icache only): 0x%08x\n", level + 1, ccsidr); + nsets = ((ccsidr & __mask(27, 13)) >> 13) + 1; + assoc = ((ccsidr & __mask(12, 3)) >> 3) + 1; + linesize = 2 << ((ccsidr & 0x7) + 2); + printk(BIOS_DEBUG, "\tnsets: %d, assoc: %d, linesize: %d\n", nsets, assoc, linesize); + break; + case 0x2: + /* dcache only */ + ccselr = level << 1; + write_csselr(ccselr); + ccsidr = read_ccsidr(); + printk(BIOS_DEBUG, "L%d (dcache only): 0x%08x\n", level + 1, ccsidr); + nsets = ((ccsidr & __mask(27, 13)) >> 13) + 1; + assoc = ((ccsidr & __mask(12, 3)) >> 3) + 1; + linesize = (1 << ((ccsidr & 0x7) + 2)) * 4; + printk(BIOS_DEBUG, "\tnsets: %d, assoc: %d, linesize: %d\n", nsets, assoc, linesize); + break; + case 0x3: + /* separate icache and dcache */ + ccselr = (level << 1) | 1; + write_csselr(ccselr); + ccsidr = read_ccsidr(); + printk(BIOS_DEBUG, "L%d: icache 0x%08x, ", level + 1, ccsidr); + nsets = ((ccsidr & __mask(27, 13)) >> 13) + 1; + assoc = ((ccsidr & __mask(12, 3)) >> 3) + 1; + linesize = (1 << ((ccsidr & 0x7) + 2)) * 4; + printk(BIOS_DEBUG, "nsets: %d, assoc: %d, linesize: %d\n", nsets, assoc, linesize); + ccselr = ccsidr = 0; /* FIXME: paranoia */ + ccselr = level << 1; + write_csselr(ccselr); + ccsidr = read_ccsidr(); + printk(BIOS_DEBUG, "L%d: dcache 0x%08x, ", level + 1, ccsidr); + nsets = ((ccsidr & __mask(27, 13)) >> 13) + 1; + assoc = ((ccsidr & __mask(12, 3)) >> 3) + 1; + linesize = (1 << ((ccsidr & 0x7) + 2)) * 4; + printk(BIOS_DEBUG, "nsets: %d, assoc: %d, linesize: %d\n", nsets, assoc, linesize); + break; + case 0x4: + /* unified cache */ + ccselr = level << 1; + write_csselr(ccselr); + ccsidr = read_ccsidr(); + printk(BIOS_DEBUG, "L%d: unified cache 0x%08x, ", level + 1, ccsidr); + nsets = ((ccsidr & __mask(27, 13)) >> 13) + 1; + assoc = ((ccsidr & __mask(12, 3)) >> 3) + 1; + linesize = (1 << ((ccsidr & 0x7) + 2)) * 4; + printk(BIOS_DEBUG, "nsets: %d, assoc: %d, linesize: %d\n", nsets, assoc, linesize); + break; + default: + /* reserved */ + printk(BIOS_DEBUG, "L%d has unknown cache\n", level + 1); + break; + } + } +} + void hardwaremain(int boot_complete); void main(void) { console_init(); printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n"); + foo(); + /* this is going to move, but we must have it now and we're not sure where */ exception_init(); /* place at top of physical memory */

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Patch merged into coreboot/master: 633f112 x86: remove stack definition in linker script
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit 633f11274fcbc9442be0be0d0bc531f43a74981b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 6 15:28:40 2013 -0600 x86: remove stack definition in linker script In order to prepare the ramstage to be linked by the rmodule linker the stack needs to be self-contained within the ramstage objects. The reasoning is that the rmodule linker provides a way to define a heap, but it doesn't currently have a region for the stack. The downside to this is that memory footprint of the ramstage can change when compared before this change. The size difference stems from the link ordering of the objects as the stack is now defined within c_start.S. The size fluctuation ranges from 0 to CONFIG_STACK_SIZE - 1 because of the previous behavior or aligning to CONFIG_STACK_SIZE. It should be noted that such an alignment is unnecessary for 32-bit x86 as the alignment requirement for the stacks are 4 byte alignment. Also the memory footprint is still dominated by CONFIG_RAMTOP and CONFIG_RAMBASE. Change-Id: I63a4ddd249104bc27aff2ab6b39fc6db12b54028 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2785 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 19 03:35:58 2013, giving +1 See http://review.coreboot.org/2785 for details. -gerrit

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coreboot March 2013