coreboot March 2013

coreboot@coreboot.org

46 participants
782 discussions

New patch to review for coreboot: fa67c1e haswell: vboot path support in romstage
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2856 -gerrit commit fa67c1eff783c71023ee1e793938feb01ec7f714 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 17:40:49 2013 -0600 haswell: vboot path support in romstage Take the vboot path in romstage. This will complete the haswell support for vboot firmware selection. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: Ie2b0a34e6c5c45e6f0d25f77a5fdbaef0324cb09 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/romstage.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1d58191..54f4a97 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -298,13 +298,11 @@ void romstage_common(const struct romstage_params *params) #endif } -static inline void prepare_for_resume(void) +static inline void prepare_for_resume(struct romstage_handoff *handoff) { /* Only need to save memory when ramstage isn't relocatable. */ #if !CONFIG_RELOCATABLE_RAMSTAGE #if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff = romstage_handoff_find_or_add(); - /* Back up the OS-controlled memory where ramstage will be loaded. */ if (handoff != NULL && handoff->s3_resume) { void *src = (void *)CONFIG_RAMBASE; @@ -318,7 +316,16 @@ static inline void prepare_for_resume(void) void romstage_after_car(void) { - prepare_for_resume(); + struct romstage_handoff *handoff; + + handoff = romstage_handoff_find_or_add(); + + prepare_for_resume(handoff); + +#if CONFIG_VBOOT_VERIFY_FIRMWARE + vboot_verify_firmware(handoff); +#endif + /* Load the ramstage. */ copy_and_run(0); }

1 0

New patch to review for coreboot: 75b919c haswell boards: support added chromeos function
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2855 -gerrit commit 75b919cd8ad04920e753910544cdde08fa5c9c86 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 17:38:59 2013 -0600 haswell boards: support added chromeos function The get_write_protect_state() function was added to the chromeos API that needs to be supported by the boards. Implement this support. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: Ifd213be25304163fc61d153feac4f5a875a40902 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/chromeos.c | 5 +++++ src/mainboard/intel/wtm1/chromeos.c | 6 ++++++ src/mainboard/intel/wtm2/chromeos.c | 6 ++++++ 3 files changed, 17 insertions(+) diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6a1bc26..677f177 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -127,3 +127,8 @@ int get_recovery_mode_switch(void) return (gp_lvl3 >> (69-64)) & 1; } +int get_write_protect_state(void) +{ + return 0; +} + diff --git a/src/mainboard/intel/wtm1/chromeos.c b/src/mainboard/intel/wtm1/chromeos.c index 1864754..c2386a8 100644 --- a/src/mainboard/intel/wtm1/chromeos.c +++ b/src/mainboard/intel/wtm1/chromeos.c @@ -75,3 +75,9 @@ int get_recovery_mode_switch(void) { return 0; // force off } + +int get_write_protect_state(void) +{ + return 0; +} + diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 1864754..c2386a8 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -75,3 +75,9 @@ int get_recovery_mode_switch(void) { return 0; // force off } + +int get_write_protect_state(void) +{ + return 0; +} +

1 0

New patch to review for coreboot: d672fbd romstage: add support for vboot firmware selection
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2854 -gerrit commit d672fbdfe5444c4b77b6c8d3c8e6cc67ddeb2bc6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 17:12:26 2013 -0600 romstage: add support for vboot firmware selection This patch implements support for vboot firmware selection. The vboot support is comprised of the following pieces: 1. vboot_loader.c - this file contains the entry point, vboot_verify_firmware(), for romstage to call in order to perform vboot selection. The loader sets up all the data for the wrapper to use. 2. vboot_wrapper.c - this file contains the implementation calling the vboot API. It calls VbInit() and VbSelectFirmware() with the data supplied by the loader. The vboot wrapper is compiled and linked as an rmodule and placed in cbfs as 'fallback/vboot'. It's loaded into memory and relocated just like the way ramstage would be. After being loaded the loader calls into wrapper. When the wrapper sees that a given piece of firmware has been selected it parses firmware component information for a predetermined number of components. Vboot result information is passed to downstream users by way of the vboot_handoff structure. This structure lives in cbmem and contains the shared data, selected firmware, VbInitParams, and parsed firwmare components. During ramstage there are only 2 changes: 1. Copy the shared vboot data from vboot_handoff to the chromeos acpi table. 2. If a firmware selection was made in romstage the boot loader component is used for the payload. Noteable Information: - no vboot path for S3. - assumes that all RW firmware contains a book keeping header for the components that comprise the signed firmware area. - As sanity check there is a limit to the number of firmware components contained in a signed firmware area. That's so that an errant value doesn't cause the size calculation to erroneously read memory it shouldn't. - RO normal path isn't supported. It's assumed that firmware will always load the verified RW on all boots but recovery. - If vboot requests memory to be cleared it is assumed that the boot loader will take care of that by looking at the out flags in VbInitParams. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: I45de725c44ee5b766f866692a20881c42ee11fa8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 5 +- src/lib/cbfs.c | 15 +- src/southbridge/intel/lynxpoint/spi_loading.c | 15 +- src/vendorcode/google/chromeos/Kconfig | 40 ++++ src/vendorcode/google/chromeos/Makefile.inc | 44 ++++ src/vendorcode/google/chromeos/chromeos.c | 32 +++ src/vendorcode/google/chromeos/chromeos.h | 12 ++ src/vendorcode/google/chromeos/gnvs.c | 18 ++ src/vendorcode/google/chromeos/vbnv.c | 26 ++- src/vendorcode/google/chromeos/vboot_context.h | 48 +++++ src/vendorcode/google/chromeos/vboot_handoff.h | 53 +++++ src/vendorcode/google/chromeos/vboot_loader.c | 280 +++++++++++++++++++++++++ src/vendorcode/google/chromeos/vboot_wrapper.c | 268 +++++++++++++++++++++++ 13 files changed, 847 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index ee956a4..11e52e5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -76,7 +76,7 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB_ELF) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(objcbfs)/coreboot_ap.elf ]; \ @@ -110,6 +110,9 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ $(CBFSTOOL) $@.tmp add -f $(obj)/config.tmp -n config -t raw; rm -f $(obj)/config.tmp ; fi endif +ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) + $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB_ELF) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 48ee86a..a682a81 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -63,6 +63,12 @@ #include "cbfs_core.c" +#if CONFIG_VBOOT_VERIFY_FIRMWARE +#include <vendorcode/google/chromeos/chromeos.h> +#else +static inline void *vboot_get_payload(int *len) { return NULL; } +#endif + #ifndef __SMM__ static inline int tohex4(unsigned int c) { @@ -301,8 +307,15 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name) #if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) { - return (struct cbfs_payload *)cbfs_get_file_content( + struct cbfs_payload *payload; + + payload = vboot_get_payload(NULL); + if (payload != NULL) + return payload; + + payload = (struct cbfs_payload *)cbfs_get_file_content( media, name, CBFS_TYPE_PAYLOAD); + return payload; } #endif diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c index 0445904..7556b34 100644 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ b/src/southbridge/intel/lynxpoint/spi_loading.c @@ -21,9 +21,15 @@ #include <stdlib.h> #include <string.h> #include <arch/byteorder.h> +#include <cbmem.h> #include <cbfs.h> #include <console/console.h> #include <cpu/x86/smm.h> +#if CONFIG_VBOOT_VERIFY_FIRMWARE +#include <vendorcode/google/chromeos/chromeos.h> +#else +static inline void *vboot_get_payload(int *len) { return NULL; } +#endif #define CACHELINE_SIZE 64 #define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) @@ -69,7 +75,14 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) { int file_len; void *file_start; - struct cbfs_file *file = cbfs_get_file(media, name); + struct cbfs_file *file; + + file_start = vboot_get_payload(&file_len); + + if (file_start != NULL) + return spi_mirror(file_start, file_len); + + file = cbfs_get_file(media, name); if (file == NULL) return NULL; diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 31094de..06ed7d3 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -67,6 +67,46 @@ config FLASHMAP_OFFSET endmenu +config VBOOT_VERIFY_FIRMWARE + bool "Verify firmware with vboot." + default n + depends on CHROMEOS + help + Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the ramstage + and boot loader. + +config EC_SOFTWARE_SYNC + bool "Enable EC software sync" + default n + depends on VBOOT_VERIFY_FIRMWARE + help + EC software sync is a mechanism where the AP helps the EC verify its + firmware similar to how vboot verifies the main system firmware. This + option selects whether depthcharge should support EC software sync. + +config VIRTUAL_DEV_SWITCH + bool "Virtual developer switch support" + default n + depends on VBOOT_VERIFY_FIRMWARE + help + Whether this platform has a virtual developer switch. + +config VBOOT_BOOT_LOADER_INDEX + hex "Bootloader component index" + default 0 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the bootloader component in the verified + firmware block. + +config VBOOT_RAMSTAGE_INDEX + hex "Ramstage component index" + default 1 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the ramstage component in the verified + firmware block. + config NO_TPM_RESUME bool default n diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 8ae14fd..9bc4d64 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -30,3 +30,47 @@ ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/chromeos.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c romstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c endif + +ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) +romstage-y += vboot_loader.c +rmodules-y += vboot_wrapper.c + +VB_LIB = $(obj)/external/vboot_reference/vboot_fw.a +VB_FIRMWARE_ARCH := $(ARCHDIR-y) +VB_SOURCE := vboot_reference + +# Add the vboot include paths. +VB_INCLUDES += -I$(VB_SOURCE)/firmware/include +VB_INCLUDES += -I$(VB_SOURCE)/firmware/arch/$(VB_FIRMWARE_ARCH)/include +INCLUDES += $(VB_INCLUDES) + +VBOOT_STUB_ELF = $(obj)/vendorcode/google/chromeos/vbootstub.elf +VBOOT_STUB_DOTO = $(VBOOT_STUB_ELF:.elf=.o) + +# Dependency for the vboot rmodules. Ordering matters. +VBOOT_STUB_DEPS += $(obj)/vendorcode/google/chromeos/vboot_wrapper.rmodules.o +VBOOT_STUB_DEPS += $(obj)/lib/memcmp.rmodules.o +VBOOT_STUB_DEPS += $(obj)/arch/x86/lib/memset.rmodules.o +VBOOT_STUB_DEPS += $(obj)/arch/x86/lib/memcpy.rmodules.o +VBOOT_STUB_DEPS += $(VB_LIB) +# Remove the '-include' option since that will break vboot's build. +VBOOT_CFLAGS += $(filter-out -include $(src)/include/kconfig.h, $(CFLAGS)) +VBOOT_CFLAGS += -DVBOOT_DEBUG + +$(VBOOT_STUB_DOTO): $(VBOOT_STUB_DEPS) + $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ + +# Link the vbootstub module with a 64KiB-byte heap. +$(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000)) + +# Build vboot library without the default includes from coreboot proper. +$(VB_LIB): + @printf " MAKE $(subst $(obj)/,,$(@))\n" + $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ + CFLAGS="$(VBOOT_CFLAGS)" \ + make -C $(VB_SOURCE) \ + BUILD=../$(dir $(VB_LIB)) \ + V=$(V) \ + fwlib + +endif diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index c1c3b38..559f1f0 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -18,7 +18,11 @@ */ #include "chromeos.h" +#if CONFIG_VBOOT_VERIFY_FIRMWARE +#include "vboot_handoff.h" +#endif #include <arch/coreboot_tables.h> +#include <cbmem.h> #include <console/console.h> int developer_mode_enabled(void) @@ -35,3 +39,31 @@ int recovery_mode_enabled(void) return get_recovery_mode_switch() || get_recovery_mode_from_vbnv(); } +#if CONFIG_VBOOT_VERIFY_FIRMWARE +void *vboot_get_payload(int *len) +{ + struct vboot_handoff *vboot_handoff; + struct firmware_component *fwc; + + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vboot_handoff == NULL) + return NULL; + + if (CONFIG_VBOOT_BOOT_LOADER_INDEX >= MAX_PARSED_FW_COMPONENTS) { + printk(BIOS_ERR, "Invalid boot loader index: %d\n", + CONFIG_VBOOT_BOOT_LOADER_INDEX); + return NULL; + } + + fwc = &vboot_handoff->components[CONFIG_VBOOT_BOOT_LOADER_INDEX]; + + if (len != NULL) + *len = fwc->size; + + printk(BIOS_DEBUG, "Booting 0x%x byte payload at 0x%08x.\n", + fwc->size, fwc->address); + + return (void *)fwc->address; +} +#endif diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 37630a6..8410707 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -20,9 +20,12 @@ #ifndef __CHROMEOS_H__ #define __CHROMEOS_H__ +#include <stdint.h> + /* functions implemented per mainboard: */ int get_developer_mode_switch(void); int get_recovery_mode_switch(void); +int get_write_protect_state(void); #ifdef __PRE_RAM__ void save_chromeos_gpios(void); #endif @@ -32,6 +35,9 @@ int get_recovery_mode_from_vbnv(void); int vboot_wants_oprom(void); extern int oprom_is_loaded; +void read_vbnv(uint8_t *vbnv_copy); +void save_vbnv(const uint8_t *vbnv_copy); + /* functions implemented in chromeos.c: */ int developer_mode_enabled(void); int recovery_mode_enabled(void); @@ -39,4 +45,10 @@ int recovery_mode_enabled(void); /* functions implemented in vboot.c */ void init_chromeos(int bootmode); +#if CONFIG_VBOOT_VERIFY_FIRMWARE +struct romstage_handoff; +void vboot_verify_firmware(struct romstage_handoff *handoff); +void *vboot_get_payload(int *len); +#endif + #endif diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 2e9975c..0d40950 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -19,12 +19,17 @@ #include <types.h> #include <string.h> +#include <stdlib.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> #include <elog.h> #include "chromeos.h" #include "gnvs.h" +#if CONFIG_VBOOT_VERIFY_FIRMWARE +#include "vboot_handoff.h" +#endif chromeos_acpi_t *vboot_data = NULL; static u32 me_hash_saved[8]; @@ -36,6 +41,19 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) /* Copy saved ME hash into NVS */ memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh)); +#if CONFIG_VBOOT_VERIFY_FIRMWARE + /* Save the vdat from the vboot handoff structure. Downstream software + * consumes the data located in the ACPI table. Ensure it reflects + * the shared data from VbInit() and VbSelectFirmware(). */ + struct vboot_handoff *vboot_handoff; + + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vboot_handoff != NULL) + memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0], + ARRAY_SIZE(chromeos->vdat)); +#endif + #if CONFIG_ELOG if (developer_mode_enabled() || (vboot_wants_oprom() && !recovery_mode_enabled())) diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c index 3f333f7..2a2faf9 100644 --- a/src/vendorcode/google/chromeos/vbnv.c +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -77,25 +77,39 @@ static uint8_t crc8(const uint8_t * data, int len) return (uint8_t) (crc >> 8); } -static void vbnv_setup(void) +void read_vbnv(uint8_t *vbnv_copy) { int i; for (i = 0; i < CONFIG_VBNV_SIZE; i++) - vbnv[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i); + vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i); /* Check data for consistency */ - if ((HEADER_SIGNATURE != (vbnv[HEADER_OFFSET] & HEADER_MASK)) - || (crc8(vbnv, CRC_OFFSET) != vbnv[CRC_OFFSET])) { + if ((HEADER_SIGNATURE != (vbnv_copy[HEADER_OFFSET] & HEADER_MASK)) + || (crc8(vbnv_copy, CRC_OFFSET) != vbnv_copy[CRC_OFFSET])) { /* Data is inconsistent (bad CRC or header), * so reset to defaults */ - memset(vbnv, 0, VBNV_BLOCK_SIZE); - vbnv[HEADER_OFFSET] = + memset(vbnv_copy, 0, VBNV_BLOCK_SIZE); + vbnv_copy[HEADER_OFFSET] = (HEADER_SIGNATURE | HEADER_FIRMWARE_SETTINGS_RESET | HEADER_KERNEL_SETTINGS_RESET); } +} + +void save_vbnv(const uint8_t *vbnv_copy) +{ + int i; + + for (i = 0; i < CONFIG_VBNV_SIZE; i++) + cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i); +} + + +static void vbnv_setup(void) +{ + read_vbnv(vbnv); vbnv_initialized = 1; } diff --git a/src/vendorcode/google/chromeos/vboot_context.h b/src/vendorcode/google/chromeos/vboot_context.h new file mode 100644 index 0000000..72a0535 --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_context.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef VBOOT_CONTEXT_H +#define VBOOT_CONTEXT_H + +#include <stdint.h> +#include <vboot_api.h> + +/* The vboot context structure provides all the necessary data for invoking + * vboot. The vboot loader sets everything up for vboot module to use. */ + +struct vboot_context { + struct vboot_handoff *handoff; + VbCommonParams *cparams; + VbSelectFirmwareParams *fparams; + uint8_t *fw_a; + uint32_t fw_a_size; + uint8_t *fw_b; + uint32_t fw_b_size; + /* Callback implementations living in romstage. */ + void (*read_vbnv)(uint8_t *vbnv_copy); + void (*save_vbnv)(const uint8_t *vbnv_copy); + int (*tis_init)(void); + int (*tis_open)(void); + int (*tis_close)(void); + int (*tis_sendrecv)(const u8 *sendbuf, size_t send_size, u8 *recvbuf, + size_t *recv_len); + void (*log_msg)(const char *fmt, va_list args); + void (*fatal_error)(void); +}; + +#endif /* VBOOT_CONTEXT_H */ diff --git a/src/vendorcode/google/chromeos/vboot_handoff.h b/src/vendorcode/google/chromeos/vboot_handoff.h new file mode 100644 index 0000000..09c7897 --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_handoff.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef VBOOT_HANDOFF_H +#define VBOOT_HANDOFF_H + +#include <vboot_api.h> + +/* + * The vboot handoff structure keeps track of a maximum number of firmware + * components in the verfieid RW area of flash. This is not a restriction on + * the number of components packed in a firmware block. It's only the maximum + * number of parsed firmware components (address and size) included in the + * handoff structure. + */ + +#define MAX_PARSED_FW_COMPONENTS 5 + +struct firmware_component { + uint32_t address; + uint32_t size; +} __attribute__((packed)); + +/* + * The vboot_handoff structure contains the data to be consumed by downstream + * firmware after firmware selection has been completed. Namely it provides + * vboot shared data as well as the flags from VbInit. As noted above a finite + * number of components are parsed from the verfieid firmare region. + */ +struct vboot_handoff { + VbInitParams init_params; + uint32_t selected_firmware; + struct firmware_component components[MAX_PARSED_FW_COMPONENTS]; + char shared_data[VB_SHARED_DATA_MIN_SIZE]; +} __attribute__((packed)); + + +#endif /* VBOOT_HANDOFF_H */ diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c new file mode 100644 index 0000000..a1a4586 --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stddef.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <console/vtxprintf.h> +#include <pc80/tpm.h> +#include <reset.h> +#include <romstage_handoff.h> +#include <rmodule.h> +#include <string.h> +#include <stdlib.h> +#include <timestamp.h> +#include "chromeos.h" +#include "fmap.h" +#include "vboot_context.h" +#include "vboot_handoff.h" + +static void vboot_run_stub(struct vboot_context *context) +{ + const struct cbmem_entry *vboot_entry; + struct rmodule vbootstub; + struct cbfs_stage *stage; + size_t region_size; + int rmodule_offset; + int load_offset; + char *vboot_region; + void (*entry)(struct vboot_context *context); + + stage = cbfs_find_file(CONFIG_CBFS_PREFIX "/vboot", CBFS_TYPE_STAGE); + + if (stage == NULL) + return; + + rmodule_offset = + rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, + stage->memlen, &region_size, &load_offset); + + vboot_entry = cbmem_entry_add(0xffffffff, region_size); + + if (vboot_entry == NULL) { + printk(BIOS_DEBUG, "Couldn't get region for vboot stub.\n"); + return; + } + + vboot_region = cbmem_entry_start(vboot_entry); + + if (cbfs_decompress(stage->compression, &stage[1], + &vboot_region[rmodule_offset], stage->len)) { + printk(BIOS_DEBUG, "Couldn't decompress vboot stub.\n"); + goto out; + } + + if (rmodule_parse(&vboot_region[rmodule_offset], &vbootstub)) { + printk(BIOS_DEBUG, "Couldn't parse vboot stub rmodule.\n"); + goto out; + } + + if (rmodule_load(&vboot_region[load_offset], &vbootstub)) { + printk(BIOS_DEBUG, "Couldn't load vboot stub.\n"); + goto out; + } + + entry = rmodule_entry(&vbootstub); + + /* Call stub. */ + entry(context); + +out: + /* Tear down the region no longer needed. */ + cbmem_entry_remove(vboot_entry); +} + +/* Helper routines for the vboot stub. */ +static void log_msg(const char *fmt, va_list args) +{ + vtxprintf(console_tx_byte, fmt, args); + console_tx_flush(); +} + +static void fatal_error(void) +{ + printk(BIOS_ERR, "vboot encountered fatal error. Reseting.\n"); + hard_reset(); +} + +static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) +{ + VbCommonParams cparams; + VbSelectFirmwareParams fparams; + struct vboot_context context; + uint32_t *iflags; + + vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; + + memset(&cparams, 0, sizeof(cparams)); + memset(&fparams, 0, sizeof(fparams)); + memset(&context, 0, sizeof(context)); + + iflags = &vboot_handoff->init_params.flags; + if (get_developer_mode_switch()) + *iflags |= VB_INIT_FLAG_DEV_SWITCH_ON; + if (get_recovery_mode_switch()) + *iflags |= VB_INIT_FLAG_REC_BUTTON_PRESSED; + if (get_write_protect_state()) + *iflags |= VB_INIT_FLAG_WP_ENABLED; + if (CONFIG_VIRTUAL_DEV_SWITCH) + *iflags |= VB_INIT_FLAG_VIRTUAL_DEV_SWITCH; + if (CONFIG_EC_SOFTWARE_SYNC) + *iflags |= VB_INIT_FLAG_EC_SOFTWARE_SYNC; + + context.handoff = vboot_handoff; + context.cparams = &cparams; + context.fparams = &fparams; + + cparams.gbb_size = find_fmap_entry("GBB", &cparams.gbb_data); + cparams.shared_data_blob = &vboot_handoff->shared_data[0]; + cparams.shared_data_size = VB_SHARED_DATA_MIN_SIZE; + cparams.caller_context = &context; + + fparams.verification_size_A = + find_fmap_entry("VBLOCK_A", &fparams.verification_block_A); + fparams.verification_size_B = + find_fmap_entry("VBLOCK_B", &fparams.verification_block_B); + + context.fw_a_size = + find_fmap_entry("FW_MAIN_A", (void **)&context.fw_a); + context.fw_b_size = + find_fmap_entry("FW_MAIN_B", (void **)&context.fw_b); + + /* Check all fmap entries. */ + if (context.fw_a == NULL || context.fw_b == NULL || + fparams.verification_block_A == NULL || + fparams.verification_block_B == NULL || + cparams.gbb_data == NULL) { + printk(BIOS_DEBUG, "Not all fmap entries found for vboot.\n"); + return; + } + + /* Initialize callbacks. */ + context.read_vbnv = &read_vbnv; + context.save_vbnv = &save_vbnv; + context.tis_init = &tis_init; + context.tis_open = &tis_open; + context.tis_close = &tis_close; + context.tis_sendrecv = &tis_sendrecv; + context.log_msg = &log_msg; + context.fatal_error = &fatal_error; + + vboot_run_stub(&context); +} + +static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, + struct romstage_handoff *handoff) +{ + struct cbfs_stage *stage; + struct rmodule ramstage; + void *entry_point; + size_t region_size; + char *ramstage_region; + int rmodule_offset; + int load_offset; + const struct cbmem_entry *ramstage_entry; + const struct firmware_component *fwc; + + if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) { + printk(BIOS_ERR, "Invalid ramstage index: %d\n", + CONFIG_VBOOT_RAMSTAGE_INDEX); + return; + } + + /* Check for invalid address. */ + fwc = &vboot_handoff->components[CONFIG_VBOOT_RAMSTAGE_INDEX]; + if (fwc->address == 0) { + printk(BIOS_DEBUG, "RW ramstage image address invalid.\n"); + return; + } + + printk(BIOS_DEBUG, "RW ramstage image at 0x%08x, 0x%08x bytes.\n", + fwc->address, fwc->size); + + stage = (void *)fwc->address; + + rmodule_offset = + rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, + stage->memlen, &region_size, &load_offset); + + ramstage_entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE, region_size); + + if (ramstage_entry == NULL) { + vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; + printk(BIOS_DEBUG, "Could not add ramstage region.\n"); + return; + } + + timestamp_add_now(TS_START_COPYRAM); + + ramstage_region = cbmem_entry_start(ramstage_entry); + + printk(BIOS_DEBUG, "Decompressing ramstage @ 0x%p (%d bytes)\n", + &ramstage_region[rmodule_offset], stage->memlen); + + if (cbfs_decompress(stage->compression, &stage[1], + &ramstage_region[rmodule_offset], stage->len)) + return; + + if (rmodule_parse(&ramstage_region[rmodule_offset], &ramstage)) + return; + + /* The ramstage is responsible for clearing its own bss. */ + if (rmodule_load_no_clear_bss(&ramstage_region[load_offset], &ramstage)) + return; + + entry_point = rmodule_entry(&ramstage); + + cache_loaded_ramstage(handoff, ramstage_entry, entry_point); + + timestamp_add_now(TS_END_COPYRAM); + + __asm__ volatile ( + "movl $0, %%ebp\n" + "jmp *%%edi\n" + :: "D"(entry_point) + ); +} + +void vboot_verify_firmware(struct romstage_handoff *handoff) +{ + struct vboot_handoff *vboot_handoff; + + /* Don't go down verified boot path on S3 resume. */ + if (handoff != NULL && handoff->s3_resume) + return; + + timestamp_add_now(TS_START_VBOOT); + + vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, + sizeof(*vboot_handoff)); + + if (vboot_handoff == NULL) { + printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); + return; + } + + memset(vboot_handoff, 0, sizeof(*vboot_handoff)); + + vboot_invoke_wrapper(vboot_handoff); + + timestamp_add_now(TS_END_VBOOT); + + /* Take RO firmware path since no RW area was selected. */ + if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && + vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { + printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", + vboot_handoff->selected_firmware); + return; + } + + /* Load ramstage from the vboot_handoff structure. */ + vboot_load_ramstage(vboot_handoff, handoff); +} diff --git a/src/vendorcode/google/chromeos/vboot_wrapper.c b/src/vendorcode/google/chromeos/vboot_wrapper.c new file mode 100644 index 0000000..66b7cfb --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_wrapper.c @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/vtxprintf.h> +#include <cpu/x86/tsc.h> +#include <rmodule.h> +#include <stdlib.h> +#include <string.h> +#include "vboot_context.h" +#include "vboot_handoff.h" + +static void vboot_wrapper(struct vboot_context *context); + +DEFINE_RMODULE_HEADER(vboot_wrapper_header, vboot_wrapper, RMODULE_TYPE_VBOOT); + +/* Keep a global context pointer around for the callbacks to use. */ +static struct vboot_context *gcontext; + +/* The FW areas consist of multiple components. At the beginning of + * each area is the number of total compoments as well as the size and + * offset for each component. One needs to caculate the total size of the + * signed firmware region based off of the embedded metadata. */ +#define MAX_NUM_COMPONENTS 20 + +struct component_entry { + uint32_t offset; + uint32_t size; +} __attribute__((packed)); + +struct components { + uint32_t num_components; + struct component_entry entries[0]; +} __attribute__((packed)); + + +static void parse_component(const struct components *components, int num, + struct firmware_component *fw) +{ + const char *base; + + if (num >= components->num_components) + return; + + /* Offsets are relative to the stat of the book keeping structure. */ + base = (void *)components; + + fw->address = (uint32_t)&base[components->entries[num].offset]; + fw->size = (uint32_t)components->entries[num].size; +} + +static void vboot_wrapper(struct vboot_context *context) +{ + int i; + VbError_t res; + const struct components *components; + + gcontext = context; + + VbExDebug("Calling VbInit()\n"); + res = VbInit(context->cparams, &context->handoff->init_params); + VbExDebug("VbInit() returned 0x%08x\n", res); + + if (res != VBERROR_SUCCESS) + return; + + VbExDebug("Calling VbSelectFirmware()\n"); + res = VbSelectFirmware(context->cparams, context->fparams); + VbExDebug("VbSelectFirmware() returned 0x%08x\n", res); + + if (res != VBERROR_SUCCESS) + return; + + /* Fix up the handoff structure. */ + context->handoff->selected_firmware = + context->fparams->selected_firmware; + + /* Parse out the components for downstream consumption. */ + if (context->handoff->selected_firmware == VB_SELECT_FIRMWARE_A) + components = (void *)context->fw_a; + else if (context->handoff->selected_firmware == VB_SELECT_FIRMWARE_B) + components = (void *)context->fw_b; + else + return; + + for (i = 0; i < MAX_PARSED_FW_COMPONENTS; i++) { + parse_component(components, i, + &context->handoff->components[i]); + } +} + +void VbExError(const char *format, ...) +{ + va_list args; + + va_start(args, format); + gcontext->log_msg(format, args); + va_end(args); + + gcontext->fatal_error(); +} + +void VbExDebug(const char *format, ...) +{ + va_list args; + + va_start(args, format); + gcontext->log_msg(format, args); + va_end(args); +} + +uint64_t VbExGetTimer(void) +{ + return rdtscll(); +} + +VbError_t VbExNvStorageRead(uint8_t *buf) +{ + gcontext->read_vbnv(buf); + return VBERROR_SUCCESS; +} + +VbError_t VbExNvStorageWrite(const uint8_t *buf) +{ + gcontext->save_vbnv(buf); + return VBERROR_SUCCESS; +} + +extern char _heap[]; +extern char _eheap[]; +static char *heap_current; +static int heap_size; + +void *VbExMalloc(size_t size) +{ + void *ptr; + + if (heap_current == NULL) { + heap_current = &_heap[0]; + heap_size = &_eheap[0] - &_heap[0]; + VbExDebug("vboot heap: %p 0x%08x bytes\n", + heap_current, heap_size); + } + + if (heap_size < size) { + VbExError("vboot heap request cannot be fulfilled. " + "0x%08x available, 0x%08x requested\n", + heap_size, size); + } + + ptr = heap_current; + heap_size -= size; + heap_current += size; + + return ptr; +} + +void VbExFree(void *ptr) +{ + /* Leak all memory. */ +} + +/* vboot doesn't expose these through the vboot_api.h, but they are needed. + * coreboot requires declarations so provide them to avoid compiler errors. */ +int Memcmp(const void *src1, const void *src2, size_t n); +void *Memcpy(void *dest, const void *src, uint64_t n); +void *Memset(void *dest, const uint8_t c, uint64_t n); + +int Memcmp(const void *src1, const void *src2, size_t n) +{ + return memcmp(src1, src2, n); +} + +void *Memcpy(void *dest, const void *src, uint64_t n) +{ + return memcpy(dest, src, n); +} + +void *Memset(void *dest, const uint8_t c, uint64_t n) +{ + return memset(dest, c, n); +} + +VbError_t VbExHashFirmwareBody(VbCommonParams *cparams, uint32_t firmware_index) +{ + uint8_t *data; + uint32_t size; + uint32_t data_size; + struct components *components; + uint32_t i; + + switch (firmware_index) { + case VB_SELECT_FIRMWARE_A: + data = gcontext->fw_a; + size = gcontext->fw_a_size; + break; + case VB_SELECT_FIRMWARE_B: + data = gcontext->fw_b; + size = gcontext->fw_b_size; + break; + default: + return VBERROR_UNKNOWN; + } + + components = (void *)data; + data_size = sizeof(struct components); + + if (components->num_components > MAX_NUM_COMPONENTS) + return VBERROR_UNKNOWN; + + data_size += + components->num_components * sizeof(struct component_entry); + + for (i = 0; i < components->num_components; i++) + data_size += ALIGN(components->entries[i].size, 4); + + if (size < data_size) + return VBERROR_UNKNOWN; + + VbUpdateFirmwareBodyHash(cparams, data, data_size); + + return VBERROR_SUCCESS; +} + +VbError_t VbExTpmInit(void) +{ + if (gcontext->tis_init()) + return VBERROR_UNKNOWN; + return VbExTpmOpen(); +} + +VbError_t VbExTpmClose(void) +{ + if (gcontext->tis_close()) + return VBERROR_UNKNOWN; + return VBERROR_SUCCESS; +} + +VbError_t VbExTpmOpen(void) +{ + if (gcontext->tis_open()) + return VBERROR_UNKNOWN; + return VBERROR_SUCCESS; +} + +VbError_t VbExTpmSendReceive(const uint8_t *request, uint32_t request_length, + uint8_t *response, uint32_t *response_length) +{ + if (gcontext->tis_sendrecv(request, request_length, + response, response_length)) + return VBERROR_UNKNOWN; + return VBERROR_SUCCESS; +} +

1 0

New patch to review for coreboot: 89c4777 rmodule: add vboot rmodule type
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2853 -gerrit commit 89c477780a65f41b3186487265680863fb21ac47 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 17:10:28 2013 -0600 rmodule: add vboot rmodule type For completeness add a vboot rmodule type since vboot will be built as an rmodule. Change-Id: I4b9b1e6f6077f811cafbb81effd4d082c91d4300 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/rmodule.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/rmodule.h b/src/include/rmodule.h index f46a59d..62c0bf3 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -29,6 +29,7 @@ enum { RMODULE_TYPE_SMM, RMODULE_TYPE_SIPI_VECTOR, RMODULE_TYPE_STAGE, + RMODULE_TYPE_VBOOT, }; struct rmodule;

1 0

New patch to review for coreboot: d05b3e7 timestamp: add vboot check points
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2852 -gerrit commit d05b3e76a69c5ce4047dd6b971945584a5c95e2c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 17:07:51 2013 -0600 timestamp: add vboot check points It's desirable to measure the vboot firmware selection time. Therefore add vboot check points to the timestamp ids. Change-Id: Ib103a9e91652cf96abcacebf0f211300e03f71fd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/timestamp.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/timestamp.h b/src/include/timestamp.h index e76716c..9dd0d0f 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -37,6 +37,8 @@ enum timestamp_id { TS_BEFORE_INITRAM = 2, TS_AFTER_INITRAM = 3, TS_END_ROMSTAGE = 4, + TS_START_VBOOT = 5, + TS_END_VBOOT = 6, TS_START_COPYRAM = 8, TS_END_COPYRAM = 9, TS_START_RAMSTAGE = 10,

1 0

New patch to review for coreboot: a03e4ea cbmem: add vboot cmbem id
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2851 -gerrit commit a03e4ea9450d367decd0fd13cedcc517d344b528 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 13 12:48:33 2013 -0500 cbmem: add vboot cmbem id The vboot firmware selection from romstage will need to pass the resulting vboot data to other consumers. This will be done using a cbmem entry. Change-Id: I497caba53f9f3944513382f3929d21b04bf3ba9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b3d9f86..5b19207 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -67,6 +67,7 @@ #define CBMEM_ID_RAMSTAGE 0x9a357a9e #define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e #define CBMEM_ID_ROOT 0xff4007ff +#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_NONE 0x00000000 #ifndef __ASSEMBLER__ diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index aaf5840..5b02f2d 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -44,6 +44,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, { CBMEM_ID_ROOT, "CBMEM ROOT " }, + { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, }; void cbmem_print_entry(int n, u32 id, u64 base, u64 size)

1 0

New patch to review for coreboot: 1a2ace3 haswell: use dynamic cbmem
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2850 -gerrit commit 1a2ace3096353531ccc8030b658ead50e4407da8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 13 13:51:20 2013 -0500 haswell: use dynamic cbmem Convert the existing haswell code to support reloctable ramstage to use dynamic cbmem. This patch always selects DYNAMIC_CBMEM as this option is a hard requirement for relocatable ramstage. Aside from converting a few new API calls, a cbmem_top() implementation is added which is defined to be at the begining of the TSEG region. Also, use the dynamic cbmem library for allocating a stack in ram for romstage after CAR is torn down. Utilizing dynamic cbmem does mean that the cmem field in the gnvs chromeos acpi table is now 0. Also, the memconsole driver in the kernel won't be able to find the memconsole because the cbmem structure changed. Change-Id: I7cf98d15b97ad82abacfb36ec37b004ce4605c38 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/haswell/romstage.c | 49 ++++++++++++-------------- src/mainboard/intel/baskingridge/acpi_tables.c | 2 +- src/mainboard/intel/wtm1/acpi_tables.c | 2 +- src/mainboard/intel/wtm2/acpi_tables.c | 2 +- src/northbridge/intel/haswell/northbridge.c | 10 ++++++ src/northbridge/intel/haswell/raminit.c | 5 +-- 7 files changed, 39 insertions(+), 32 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index d1f521d..5f27d4c 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select SMM_MODULES select RELOCATABLE_MODULES + select DYNAMIC_CBMEM select CPU_MICROCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4ece6c2..1d58191 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -33,7 +33,6 @@ #include <arch/romcc_io.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <cbmem.h> #include <cbfs.h> #include <romstage_handoff.h> #include <reset.h> @@ -71,13 +70,17 @@ static inline u32 *stack_push(u32 *stack, u32 value) return stack; } +/* Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. */ +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 static unsigned long choose_top_of_stack(void) { unsigned long stack_top; -#if CONFIG_RELOCATABLE_RAMSTAGE - stack_top = (unsigned long)cbmem_add(CBMEM_ID_RESUME_SCRATCH, - CONFIG_HIGH_SCRATCH_MEMORY_SIZE); - stack_top += CONFIG_HIGH_SCRATCH_MEMORY_SIZE; +#if CONFIG_DYNAMIC_CBMEM + /* cbmem_add() does a find() before add(). */ + stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, + ROMSTAGE_RAM_STACK_SIZE); + stack_top += ROMSTAGE_RAM_STACK_SIZE; #else stack_top = ROMSTAGE_STACK; #endif @@ -198,7 +201,6 @@ void romstage_common(const struct romstage_params *params) { int boot_mode; int wake_from_s3; - int cbmem_was_initted; struct romstage_handoff *handoff; #if CONFIG_COLLECT_TIMESTAMPS @@ -266,23 +268,16 @@ void romstage_common(const struct romstage_params *params) quick_ram_check(); post_code(0x3e); -#if CONFIG_EARLY_CBMEM_INIT - cbmem_was_initted = !cbmem_initialize(); -#else - cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - - HIGH_MEMORY_SIZE)); -#endif - - /* Save data returned from MRC on non-S3 resumes. */ - if (!wake_from_s3) + if (!wake_from_s3) { + cbmem_initialize_empty(); + /* Save data returned from MRC on non-S3 resumes. */ save_mrc_data(params->pei_data); - -#if CONFIG_HAVE_ACPI_RESUME - if (wake_from_s3 && !cbmem_was_initted) { + } else if (cbmem_initialize()) { + #if CONFIG_HAVE_ACPI_RESUME /* Failed S3 resume, reset to come up cleanly */ reset_system(); + #endif } -#endif handoff = romstage_handoff_find_or_add(); if (handoff != NULL) @@ -331,11 +326,16 @@ void romstage_after_car(void) #if CONFIG_RELOCATABLE_RAMSTAGE void cache_loaded_ramstage(struct romstage_handoff *handoff, - void *ramstage_base, uint32_t ramstage_size, + const struct cbmem_entry *ramstage, void *entry_point) { struct ramstage_cache *cache; uint32_t total_size; + uint32_t ramstage_size; + void *ramstage_base; + + ramstage_size = cbmem_entry_size(ramstage); + ramstage_base = cbmem_entry_start(ramstage); /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of ram is defined to be the TSEG base address. */ @@ -359,19 +359,14 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, /* Copy over the program. */ memcpy(&cache->program[0], ramstage_base, ramstage_size); - /* Do not update reserve region if the handoff structure is not - * available. Perhaps the ramstage will fix things up for the resume - * path. */ if (handoff == NULL) return; - /* Update entry and reserve region. */ - handoff->reserve_base = (uint32_t)ramstage_base; - handoff->reserve_size = ramstage_size; handoff->ramstage_entry_point = (uint32_t)entry_point; } -void *load_cached_ramstage(struct romstage_handoff *handoff) +void *load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage) { struct ramstage_cache *cache; diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 823abcf..5131ec1 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -87,7 +87,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 1; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = 0; /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/mainboard/intel/wtm1/acpi_tables.c b/src/mainboard/intel/wtm1/acpi_tables.c index 18c9bb2..4232afc 100644 --- a/src/mainboard/intel/wtm1/acpi_tables.c +++ b/src/mainboard/intel/wtm1/acpi_tables.c @@ -84,7 +84,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = 0; /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 18c9bb2..4232afc 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -84,7 +84,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* CBMEM TOC */ - gnvs->cmem = (u32)get_cbmem_toc(); + gnvs->cmem = 0; /* IGD Displays */ gnvs->ndid = 3; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 53c2f36..b57b28e 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -543,6 +543,16 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } +void *cbmem_top(void) +{ + u32 reg; + + /* The top the reserve regions fall just below the TSEG region. */ + reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); + + return (void *)(reg & ~((1 << 20) - 1)); +} + static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1439200..ee21823 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -203,9 +203,10 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } -struct cbmem_entry *get_cbmem_toc(void) +void *cbmem_top(void) { - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); + /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ + return (void *)get_top_of_ram(); } unsigned long get_top_of_ram(void)

1 0

New patch to review for coreboot: 303cd1a coreboot: dynamic cbmem requirement
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2849 -gerrit commit 303cd1af18c44132473a5bfd6fcae353338b0016 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 27 22:50:12 2013 -0600 coreboot: dynamic cbmem requirement Dynamic cbmem is now a requirement for relocatable ramstage. This patch replaces the reserve_* fields in the romstage_handoff structure by using the dynamic cbmem library. The haswell code is not moved over in this commit, but it should be safe because there is a hard requirement for DYNAMIC_CBMEM when using a reloctable ramstage. Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 9 +-- src/arch/x86/boot/coreboot_table.c | 20 ------- src/include/cbfs.h | 21 ++++--- src/include/cbmem.h | 5 -- src/include/rmodule.h | 16 ++--- src/include/romstage_handoff.h | 3 - src/lib/cbfs.c | 91 ++++++++++++++++------------- src/lib/hardwaremain.c | 9 --- src/lib/rmodule.c | 38 ++++++------ src/northbridge/intel/haswell/northbridge.c | 15 ----- 10 files changed, 94 insertions(+), 133 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 0297970..18b5bad 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -315,14 +315,7 @@ config HAVE_INIT_TIMER config HIGH_SCRATCH_MEMORY_SIZE hex - default 0x5000 if RELOCATABLE_RAMSTAGE default 0x0 - help - The amount of extra memory to reserve from the OS. If - RELOCATABLE_RAMSTAGE is enabled a size of 20KiB is reserved. This is - for the use of a stack in romstage after memory has been initialized. - The stack size required in romstage can be large when needing to - decompress the ramstage. config USE_OPTION_TABLE bool @@ -390,7 +383,7 @@ config RELOCATABLE_MODULES loaded anywhere and all the relocations are handled automatically. config RELOCATABLE_RAMSTAGE - depends on RELOCATABLE_MODULES + depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM) bool "Build the ramstage to be relocatable in 32-bit address space." default n help diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 06d3888..3b22569 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -31,7 +31,6 @@ #include <stdlib.h> #include <cbfs.h> #include <cbmem.h> -#include <romstage_handoff.h> #if CONFIG_USE_OPTION_TABLE #include <option_table.h> #endif @@ -596,23 +595,6 @@ static void add_lb_reserved(struct lb_memory *mem) lb_add_rsvd_range, mem); } -static void add_romstage_resources(struct lb_memory *mem) -{ - struct romstage_handoff *handoff; - - /* Reserve memory requested to be reserved from romstage. */ - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) - return; - - if (handoff->reserve_size == 0) - return; - - lb_add_memory_range(mem, LB_MEM_RESERVED, handoff->reserve_base, - handoff->reserve_size); -} - unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) @@ -686,8 +668,6 @@ unsigned long write_coreboot_table( /* Add reserved regions */ add_lb_reserved(mem); - add_romstage_resources(mem); - lb_dump_memory_ranges(mem); /* Note: diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 811df88..ac249aa 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -87,21 +87,24 @@ int init_default_cbfs_media(struct cbfs_media *media); /* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined * to be weak so that board and chipset code may override them. Their job is to * cache and load the ramstage for quick S3 resume. By default a copy of the - * relocated ramstage is saved just below the running ramstage region. These + * relocated ramstage is saved using the cbmem infrastructure. These * functions are only valid during romstage. */ struct romstage_handoff; +struct cbmem_entry; -/* The implementer of cache_loaded_ramstage() needs to ensure that the - * reserve_* fields in in romstage_handoff reflect the memory footprint of the - * ramstage (including cached region). Note that the handoff variable can be - * NULL. */ +/* The implementer of cache_loaded_ramstage() may use the romstage_handoff + * structure to store information, but note that the handoff variable can be + * NULL. The ramstage cbmem_entry represents the region occupied by the loaded + * ramstage. */ void __attribute__((weak)) -cache_loaded_ramstage(struct romstage_handoff *handoff, void *ramstage_base, - uint32_t ramstage_size, void *entry_point); -/* Return NULL on error or entry point on success. */ +cache_loaded_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage, void *entry_point); +/* Return NULL on error or entry point on success. The ramstage cbmem_entry is + * the region where to load the cached contents to. */ void * __attribute__((weak)) -load_cached_ramstage(struct romstage_handoff *handoff); +load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage); #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 41f5971..b3d9f86 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -131,11 +131,6 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; -#if CONFIG_EARLY_CBMEM_INIT -/* Return 0 on success, < 0 on error. */ -int __attribute__((weak)) cbmem_get_table_location(uint64_t *tables_base, - uint64_t *tables_size); -#endif void set_cbmem_toc(struct cbmem_entry *); #endif diff --git a/src/include/rmodule.h b/src/include/rmodule.h index e8e7636..f46a59d 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -42,13 +42,15 @@ int rmodule_memory_size(const struct rmodule *m); int rmodule_load(void *loc, struct rmodule *m); int rmodule_load_no_clear_bss(void *base, struct rmodule *m); int rmodule_load_alignment(const struct rmodule *m); -/* Returns the an aligned pointer that reflects a region used below addr - * based on the rmodule_size. i.e. the returned pointer up to addr is memory - * that may be utilized by the rmodule. program_start and rmodule_start - * are pointers updated to reflect where the rmodule program starts and where - * the rmodule (including header) should be placed respectively. */ -void *rmodule_find_region_below(void *addr, size_t rmodule_size, - void **program_start, void **rmodule_start); +/* rmodule_calc_region() calculates the region size, offset to place an + * rmodule in memory, and load address offset based off of a region allocator + * with an alignment of region_alignment. This function helps place an rmodule + * in the same location in ram it will run from. The offset to place the + * rmodule into the region allocated of size region_size is returned. The + * load_offset is the address to load and relocate the rmodule. + * region_alignment must be a power of 2. */ +int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, + size_t *region_size, int *load_offset); #define FIELD_ENTRY(x_) ((u32)&x_) #define RMODULE_HEADER(entry_, type_) \ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 4150e8e..3152fb2 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -28,9 +28,6 @@ * using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber * fields it doesn't own. */ struct romstage_handoff { - /* This indicates to the ramstage to reserve a chunk of memory. */ - uint32_t reserve_base; - uint32_t reserve_size; /* Inidicate if the current boot is an S3 resume. If * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is * responsible for initializing this variable. Otherwise, ramstage diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 8bcb000..48ee86a 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -120,41 +120,48 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, #include <rmodule.h> #include <romstage_handoff.h> /* When CONFIG_RELOCATABLE_RAMSTAGE is enabled and this file is being compiled - * for the romstage, the rmodule loader is used. The ramstage is placed just - * below the cbmem location. */ - + * for the romstage, the rmodule loader is used. */ void __attribute__((weak)) -cache_loaded_ramstage(struct romstage_handoff *handoff, void *ramstage_base, - uint32_t ramstage_size, void *entry_point) +cache_loaded_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage, void *entry_point) { + uint32_t ramstage_size; + const struct cbmem_entry *entry; + if (handoff == NULL) return; - /* Cache the loaded ramstage just below the to-be-run ramstage. Then - * save the base, size, and entry point in the handoff area. */ - handoff->reserve_base = (uint32_t)ramstage_base - ramstage_size; - handoff->reserve_size = ramstage_size; - handoff->ramstage_entry_point = (uint32_t)entry_point; + ramstage_size = cbmem_entry_size(ramstage); + /* cbmem_entry_add() does a find() before add(). */ + entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE_CACHE, ramstage_size); - memcpy((void *)handoff->reserve_base, ramstage_base, ramstage_size); + if (entry == NULL) + return; + + /* Keep track of the entry point in the handoff structure. */ + handoff->ramstage_entry_point = (uint32_t)entry_point; - /* Update the reserve region by 2x in order to store the cached copy. */ - handoff->reserve_size += handoff->reserve_size; + memcpy(cbmem_entry_start(entry), cbmem_entry_start(ramstage), + ramstage_size); } void * __attribute__((weak)) -load_cached_ramstage(struct romstage_handoff *handoff) +load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage) { - uint32_t ramstage_size; + const struct cbmem_entry *entry_cache; if (handoff == NULL) return NULL; - /* Load the cached ramstage copy into the to-be-run region. It is just - * above the cached copy. */ - ramstage_size = handoff->reserve_size / 2; - memcpy((void *)(handoff->reserve_base + ramstage_size), - (void *)handoff->reserve_base, ramstage_size); + entry_cache = cbmem_entry_find(CBMEM_ID_RAMSTAGE_CACHE); + + if (entry_cache == NULL) + return NULL; + + /* Load the cached ramstage copy into the to-be-run region. */ + memcpy(cbmem_entry_start(ramstage), cbmem_entry_start(entry_cache), + cbmem_entry_size(ramstage)); return (void *)handoff->ramstage_entry_point; } @@ -164,12 +171,12 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, { struct cbfs_stage *stage; struct rmodule ramstage; - char *cbmem_base; - char *ramstage_base; - void *decompression_loc; - void *ramstage_loc; void *entry_point; - uint32_t ramstage_size; + size_t region_size; + char *ramstage_region; + int rmodule_offset; + int load_offset; + const struct cbmem_entry *ramstage_entry; stage = (struct cbfs_stage *) cbfs_get_file_content(media, name, CBFS_TYPE_STAGE); @@ -177,34 +184,34 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, if (stage == NULL) return (void *) -1; - cbmem_base = (void *)get_cbmem_toc(); - if (cbmem_base == NULL) + rmodule_offset = + rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, + stage->memlen, &region_size, &load_offset); + + ramstage_entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE, region_size); + + if (ramstage_entry == NULL) return (void *) -1; - ramstage_base = - rmodule_find_region_below(cbmem_base, stage->memlen, - &ramstage_loc, - &decompression_loc); + ramstage_region = cbmem_entry_start(ramstage_entry); LOG("Decompressing stage %s @ 0x%p (%d bytes)\n", - name, decompression_loc, stage->memlen); + name, &ramstage_region[rmodule_offset], stage->memlen); if (cbfs_decompress(stage->compression, &stage[1], - decompression_loc, stage->len)) + &ramstage_region[rmodule_offset], stage->len)) return (void *) -1; - if (rmodule_parse(decompression_loc, &ramstage)) + if (rmodule_parse(&ramstage_region[rmodule_offset], &ramstage)) return (void *) -1; /* The ramstage is responsible for clearing its own bss. */ - if (rmodule_load_no_clear_bss(ramstage_loc, &ramstage)) + if (rmodule_load_no_clear_bss(&ramstage_region[load_offset], &ramstage)) return (void *) -1; entry_point = rmodule_entry(&ramstage); - ramstage_size = cbmem_base - ramstage_base; - cache_loaded_ramstage(handoff, ramstage_base, ramstage_size, - entry_point); + cache_loaded_ramstage(handoff, ramstage_entry, entry_point); return entry_point; } @@ -212,6 +219,7 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct romstage_handoff *handoff; + const struct cbmem_entry *ramstage; void *entry; handoff = romstage_handoff_find_or_add(); @@ -222,9 +230,14 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) } else if (!handoff->s3_resume) return load_stage_from_cbfs(media, name, handoff); + ramstage = cbmem_entry_find(CBMEM_ID_RAMSTAGE); + + if (ramstage == NULL) + return load_stage_from_cbfs(name, handoff); + /* S3 resume path. Load a cached copy of the loaded ramstage. If * return value is NULL load from cbfs. */ - entry = load_cached_ramstage(handoff); + entry = load_cached_ramstage(handoff, ramstage); if (entry == NULL) return load_stage_from_cbfs(name, handoff); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index bc18989..a3ee10b 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -85,15 +85,6 @@ void hardwaremain(int boot_complete) /* FIXME: Is there a better way to handle this? */ init_timer(); - /* CONFIG_EARLY_CBMEM_INIT indicates that romstage initialized - * the cbmem area. Therefore the table location can be initialized - * early in ramstage if cbmem_get_table_location() is implemented. - */ -#if CONFIG_EARLY_CBMEM_INIT - if (cbmem_get_table_location != NULL && - !cbmem_get_table_location(&high_tables_base, &high_tables_size)) - cbmem_initialize(); -#endif init_cbmem_pre_device(); timestamp_stash(TS_DEVICE_ENUMERATE); diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index d36f9f3..3dd90d8 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -16,6 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <assert.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -265,16 +266,22 @@ int rmodule_load_no_clear_bss(void *base, struct rmodule *module) return __rmodule_load(base, module, 0); } -void *rmodule_find_region_below(void *addr, size_t rmodule_size, - void **program_start, void **rmodule_start) +int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, + size_t *region_size, int *load_offset) { - unsigned long ceiling; - unsigned long program_base; - unsigned long placement_loc; - unsigned long program_begin; + /* region_alignment must be a power of 2. */ + if (region_alignment & (region_alignment - 1)) + BUG(); - ceiling = (unsigned long)addr; - /* Place the rmodule just under the ceiling. The rmodule files + if (region_alignment < 4096) + region_alignment = 4096; + + /* Sanity check rmodule_header size. The code below assumes it is less + * than the minimum alignment required. */ + if (region_alignment < sizeof(struct rmodule_header)) + BUG(); + + /* Place the rmodule according to alignment. The rmodule files * themselves are packed as a header and a payload, however the rmodule * itself is linked along with the header. The header starts at address * 0. Immediately following the header in the file is the program, @@ -284,13 +291,13 @@ void *rmodule_find_region_below(void *addr, size_t rmodule_size, * to place the rmodule so that the prgoram falls on the aligned * address with the header just before it. Therefore, we need at least * a page to account for the size of the header. */ - program_base = ALIGN((ceiling - (rmodule_size + 4096)), 4096); + *region_size = ALIGN(rmodule_size + region_alignment, 4096); /* The program starts immediately after the header. However, * it needs to be aligned to a 4KiB boundary. Therefore, adjust the * program location so that the program lands on a page boundary. The * layout looks like the following: * - * +--------------------------------+ ceiling + * +--------------------------------+ region_alignment + region_size * | >= 0 bytes from alignment | * +--------------------------------+ program end (4KiB aligned) * | program size | @@ -298,14 +305,9 @@ void *rmodule_find_region_below(void *addr, size_t rmodule_size, * | sizeof(struct rmodule_header) | * +--------------------------------+ rmodule header start * | >= 0 bytes from alignment | - * +--------------------------------+ program_base (4KiB aligned) + * +--------------------------------+ region_alignment */ - placement_loc = ALIGN(program_base + sizeof(struct rmodule_header), - 4096) - sizeof(struct rmodule_header); - program_begin = placement_loc + sizeof(struct rmodule_header); - - *program_start = (void *)program_begin; - *rmodule_start = (void *)placement_loc; + *load_offset = region_alignment; - return (void *)program_base; + return region_alignment - sizeof(struct rmodule_header); } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8708138..53c2f36 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -543,21 +543,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -#if CONFIG_EARLY_CBMEM_INIT -int cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size) -{ - uint32_t tseg; - - /* Put the CBMEM location just below TSEG. */ - *tables_size = HIGH_MEMORY_SIZE; - tseg = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), - TSEG) & ~((1 << 20) - 1)) - HIGH_MEMORY_SIZE; - *tables_base = tseg; - - return 0; -} -#endif - static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME

1 0

New patch to review for coreboot: 5e9b74e cbmem: dynamic cbmem support
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2848 -gerrit commit 5e9b74eb4a2de4175aea8df89947ffaff8d52722 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 13 12:41:44 2013 -0500 cbmem: dynamic cbmem support This patch adds a parallel implementation of cbmem that supports dynamic sizing. The original implementation relied on reserving a fixed-size block of memory for adding cbmem entries. In order to allow for more flexibility for adding cbmem allocations the dynamic cbmem infrastructure was developed as an alternative to the fixed block approach. Also, the amount of memory to reserve for cbmem allocations does not need to be known prior to the first allocation. The dynamic cbmem code implements the same API as the existing cbmem code except for cbmem_init() and cbmem_reinit(). The add and find routines behave the same way. The dynamic cbmem infrastructure uses a top down allocator that starts allocating from a board/chipset defined function cbmem_top(). A root pointer lives just below cbmem_top(). In turn that pointer points to the root block which contains the entries for all the large alloctations. The corresponding block for each large allocation falls just below the previous entry. It should be noted that this implementation rounds all allocations up to a 4096 byte granularity. Though a packing allocator could be written for small allocations it was deemed OK to just fragment the memory as there shouldn't be that many small allocations. The result is less code with a tradeoff of some wasted memory. +----------------------+ <- cbmem_top() | +----| root pointer | | | +----------------------+ | | | |--------+ | +--->| root block |-----+ | | +----------------------+ | | | | | | | | | | | | | | alloc N |<----+ | | +----------------------+ | | | | | | | | | \|/ | alloc N + 1 |<-------+ v +----------------------+ In addition to preserving the previous cbmem API, the dynamic cbmem API allows for removing blocks from cbmem. This allows for the boot process to allocate memory that can be discarded after it's been used for performing more complex boot tasks in romstage. In order to plumb this support in there were some issues to work around regarding writing of coreboot tables. There were a few assumptions to how cbmem was layed out which dictated some ifdef guarding and other runtime checks so as not to incorrectly tag the e820 and coreboot memory tables. The example shown below is using dynamic cbmem infrastructure. The reserved memory for cbmem is less than 512KiB. coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000002ffff: RAM 2. 0000000000030000-000000000003ffff: RESERVED 3. 0000000000040000-000000000009ffff: RAM 4. 00000000000a0000-00000000000fffff: RESERVED 5. 0000000000100000-0000000000efffff: RAM 6. 0000000000f00000-0000000000ffffff: RESERVED 7. 0000000001000000-000000007bf80fff: RAM 8. 000000007bf81000-000000007bffffff: CONFIGURATION TABLES 9. 000000007c000000-000000007e9fffff: RESERVED 10. 00000000f0000000-00000000f3ffffff: RESERVED 11. 00000000fed10000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-00000001005fffff: RAM Wrote coreboot table at: 7bf81000, 0x39c bytes, checksum f5bf coreboot table: 948 bytes. CBMEM ROOT 0. 7bfff000 00001000 MRC DATA 1. 7bffe000 00001000 ROMSTAGE 2. 7bffd000 00001000 TIME STAMP 3. 7bffc000 00001000 ROMSTG STCK 4. 7bff7000 00005000 CONSOLE 5. 7bfe7000 00010000 VBOOT 6. 7bfe6000 00001000 RAMSTAGE 7. 7bf98000 0004e000 GDT 8. 7bf97000 00001000 ACPI 9. 7bf8b000 0000c000 ACPI GNVS 10. 7bf8a000 00001000 SMBIOS 11. 7bf89000 00001000 COREBOOT 12. 7bf81000 00008000 And the corresponding e820 entries: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 BIOS-e820: [mem 0x0000000000001000-0x000000000002ffff] usable BIOS-e820: [mem 0x0000000000030000-0x000000000003ffff] reserved BIOS-e820: [mem 0x0000000000040000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x0000000000efffff] usable BIOS-e820: [mem 0x0000000000f00000-0x0000000000ffffff] reserved BIOS-e820: [mem 0x0000000001000000-0x000000007bf80fff] usable BIOS-e820: [mem 0x000000007bf81000-0x000000007bffffff] type 16 BIOS-e820: [mem 0x000000007c000000-0x000000007e9fffff] reserved BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved BIOS-e820: [mem 0x00000000fed10000-0x00000000fed19fff] reserved BIOS-e820: [mem 0x00000000fed84000-0x00000000fed84fff] reserved BIOS-e820: [mem 0x0000000100000000-0x00000001005fffff] usable Change-Id: Ie3bca52211800a8652a77ca684140cfc9b3b9a6b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 8 + src/arch/x86/boot/coreboot_table.c | 22 +- src/arch/x86/boot/tables.c | 2 + src/include/cbmem.h | 104 ++++++++- src/lib/Makefile.inc | 12 +- src/lib/cbmem.c | 38 ++-- src/lib/cbmem_info.c | 69 ++++++ src/lib/dynamic_cbmem.c | 452 +++++++++++++++++++++++++++++++++++++ src/lib/hardwaremain.c | 7 +- 9 files changed, 671 insertions(+), 43 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7a8985c..0297970 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -179,6 +179,14 @@ config EARLY_CBMEM_INIT some, for instance, execution timestamps. It needs support in romstage.c and should be enabled by the board's Kconfig. +config DYNAMIC_CBMEM + bool "The CBMEM space is dynamically grown." + default n + help + Instead of reserving a static amount of CBMEM space the CBMEM + area grows dynamically. CBMEM can be used both in romstage (after + memory initialization) and ramstage. + config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" depends on EARLY_CBMEM_INIT diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 463f723..06d3888 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -355,6 +355,9 @@ static void lb_memory_range(struct lb_memory *mem, static void lb_reserve_table_memory(struct lb_header *head) { +/* Dynamic cbmem has already reserved the memory where the coreboot tables + * reside. Therefore, there is nothing to fix up. */ +#if !CONFIG_DYNAMIC_CBMEM struct lb_record *last_rec; struct lb_memory *mem; uint64_t start; @@ -383,6 +386,7 @@ static void lb_reserve_table_memory(struct lb_header *head) mem->map[i].size = pack_lb64(map_end - end); } } +#endif } static unsigned long lb_table_fini(struct lb_header *head, int fixup) @@ -664,14 +668,20 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, low_table_start, low_table_end - low_table_start); - /* Record the pirq table, acpi tables, and maybe the mptable */ - lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, rom_table_end-rom_table_start); - - printk(BIOS_DEBUG, "Adding high table area\n"); - // should this be LB_MEM_ACPI? + /* Record the pirq table, acpi tables, and maybe the mptable. However, + * these only need to be added when the rom_table is sitting below + * 1MiB. If it isn't that means high tables are being written. + * The code below handles high tables correctly. */ + if (rom_table_end <= (1 << 20)) + lb_add_memory_range(mem, LB_MEM_TABLE, + rom_table_start, rom_table_end-rom_table_start); + +#if CONFIG_DYNAMIC_CBMEM + cbmem_add_lb_mem(mem); +#else /* CONFIG_DYNAMIC_CBMEM */ lb_add_memory_range(mem, LB_MEM_TABLE, high_tables_base, high_tables_size); +#endif /* CONFIG_DYNAMIC_CBMEM */ /* Add reserved regions */ add_lb_reserved(mem); diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 294a10c..d842e73 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -53,6 +53,7 @@ struct lb_memory *write_tables(void) */ unsigned long high_table_pointer; +#if !CONFIG_DYNAMIC_CBMEM if (!high_tables_base) { printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); // Are there any boards without? @@ -60,6 +61,7 @@ struct lb_memory *write_tables(void) } printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); +#endif rom_table_start = 0xf0000; rom_table_end = 0xf0000; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 1212cb2..41f5971 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -62,9 +63,72 @@ #define CBMEM_ID_ELOG 0x454c4f47 #define CBMEM_ID_COVERAGE 0x47434f56 #define CBMEM_ID_ROMSTAGE_INFO 0x47545352 +#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4 +#define CBMEM_ID_RAMSTAGE 0x9a357a9e +#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e +#define CBMEM_ID_ROOT 0xff4007ff #define CBMEM_ID_NONE 0x00000000 #ifndef __ASSEMBLER__ +#include <stdint.h> + +struct cbmem_entry; + +#if CONFIG_DYNAMIC_CBMEM + +/* + * The dynamic cbmem infrastructure allows for growing cbmem dynamically as + * things are added. It requires an external function, cbmem_top(), to be + * implemented by the board or chipset to define the upper address where + * cbmem lives. This address is required to be a 32-bit address. Additionally, + * the address needs to be consistent in both romstage and ramstage. The + * dynamic cbmem infrasturue allocates new regions below the last allocated + * region. Regions are defined by a cbmem_entry struct that is opaque. Regions + * may be removed, but the last one added is the only that can be removed. + * + * Dynamic cbmem has two allocators within it. All allocators use a top down + * allocation scheme. However, there are 2 modes for each allocation depending + * on the requested size. There are large allocations and small allocations. + * An allocation is considered to be small when it is less than or equal to + * DYN_CBMEM_ALIGN_SIZE / 2. The smaller allocations are fit into a larger + * allocation region. + */ + +#define DYN_CBMEM_ALIGN_SIZE (4096) + +/* Initialze cbmem to be empty. */ +void cbmem_initialize_empty(void); + +/* Return the top address for dynamic cbmem. The address returned needs to + * be consistent across romstage and ramstage, and it is required to be + * below 4GiB. */ +void *cbmem_top(void); + +/* Add a cbmem entry of a given size and id. These return NULL on failure. The + * add function performs a find first and do not check against the original + * size. */ +const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size); + +/* Find a cbmem entry of a given id. These return NULL on failure. */ +const struct cbmem_entry *cbmem_entry_find(u32 id); + +/* Remove a region defined by a cbmem_entry. Returns 0 on success, < 0 on + * error. Note: A cbmem_entry cannot be removed unless it was the last one + * added. */ +int cbmem_entry_remove(const struct cbmem_entry *entry); + +/* cbmem_entry accessors to get pointer and size of a cbmem_entry. */ +void *cbmem_entry_start(const struct cbmem_entry *entry); +u64 cbmem_entry_size(const struct cbmem_entry *entry); + +#ifndef __PRE_RAM__ +/* Add the cbmem memory used to the memory tables. */ +struct lb_memory; +void cbmem_add_lb_mem(struct lb_memory *mem); +#endif /* __PRE_RAM__ */ + +#else /* !CONFIG_DYNAMIC_CBMEM */ + #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; #if CONFIG_EARLY_CBMEM_INIT @@ -72,22 +136,44 @@ extern uint64_t high_tables_base, high_tables_size; int __attribute__((weak)) cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size); #endif +void set_cbmem_toc(struct cbmem_entry *); #endif -int cbmem_initialize(void); - void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); + +extern struct cbmem_entry *get_cbmem_toc(void); + +#endif /* CONFIG_DYNAMIC_CBMEM */ + +/* Common API between cbmem and dynamic cbmem. */ + +/* By default cbmem is attempted to be recovered. Returns 0 if cbmem was + * recovered or 1 if cbmem had to be reinitialized. */ +int cbmem_initialize(void); +/* Add a cbmem entry of a given size and id. These return NULL on failure. The + * add function performs a find first and do not check against the original + * size. */ void *cbmem_add(u32 id, u64 size); +/* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); + +#ifndef __PRE_RAM__ +/* Ramstage only functions. */ void cbmem_list(void); void cbmem_arch_init(void); +void __attribute__((weak)) cbmem_post_handling(void); +void cbmem_print_entry(int n, u32 id, u64 start, u64 size); +/* The pre|post device cbmem initialization functions are for the + * ramstage main to call. When cbmem is actually initialized depends on + * the cbmem implementation. */ +void init_cbmem_pre_device(void); +void init_cbmem_post_device(void); +#else +static inline void cbmem_arch_init(void) {} +#endif /* __PRE_RAM__ */ -extern struct cbmem_entry *get_cbmem_toc(void); +#endif /* __ASSEMBLER__ */ -#ifndef __PRE_RAM__ -void set_cbmem_toc(struct cbmem_entry *); -void __attribute__((weak)) cbmem_post_handling(void); -#endif -#endif -#endif + +#endif /* _CBMEM_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index fe57f9f..c0372c5 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -42,7 +42,6 @@ romstage-y += cbfs.c romstage-y += lzma.c #romstage-y += lzmadecode.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c -romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -76,7 +75,6 @@ ramstage-y += lzma.c ramstage-y += stack.c ramstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += clog2.c -ramstage-y += cbmem.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -86,6 +84,16 @@ ramstage-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c +# The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM. +ifeq ($(CONFIG_DYNAMIC_CBMEM),y) +ramstage-y += dynamic_cbmem.c +romstage-y += dynamic_cbmem.c +else +ramstage-y += cbmem.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c +endif # CONFIG_DYNAMIC_CBMEM +ramstage-y += cbmem_info.c + ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 5663cc8..f4fd3b6 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -232,6 +232,20 @@ int cbmem_initialize(void) #endif #ifndef __PRE_RAM__ +/* cbmem cannot be initialized before device drivers, but it can be initialized + * after the drivers have run when CONFIG_WRITE_HIGH_TABLES is enabled. */ +void init_cbmem_pre_device(void) {} + +void init_cbmem_post_device(void) +{ +#if CONFIG_WRITE_HIGH_TABLES + cbmem_initialize(); +#if CONFIG_CONSOLE_CBMEM + cbmemc_reinit(); +#endif +#endif +} + void cbmem_list(void) { struct cbmem_entry *cbmem_toc; @@ -245,28 +259,8 @@ void cbmem_list(void) if (cbmem_toc[i].magic != CBMEM_MAGIC) continue; - printk(BIOS_DEBUG, "%2d. ", i); - switch (cbmem_toc[i].id) { - case CBMEM_ID_FREESPACE: printk(BIOS_DEBUG, "FREE SPACE "); break; - case CBMEM_ID_GDT: printk(BIOS_DEBUG, "GDT "); break; - case CBMEM_ID_ACPI: printk(BIOS_DEBUG, "ACPI "); break; - case CBMEM_ID_CBTABLE: printk(BIOS_DEBUG, "COREBOOT "); break; - case CBMEM_ID_PIRQ: printk(BIOS_DEBUG, "IRQ TABLE "); break; - case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break; - case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; - case CBMEM_ID_RESUME_SCRATCH: printk(BIOS_DEBUG, "ACPISCRATCH"); break; - case CBMEM_ID_ACPI_GNVS: printk(BIOS_DEBUG, "ACPI GNVS "); break; - case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; - case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; - case CBMEM_ID_MRCDATA: printk(BIOS_DEBUG, "MRC DATA "); break; - case CBMEM_ID_CONSOLE: printk(BIOS_DEBUG, "CONSOLE "); break; - case CBMEM_ID_ELOG: printk(BIOS_DEBUG, "ELOG "); break; - case CBMEM_ID_COVERAGE: printk(BIOS_DEBUG, "COVERAGE "); break; - case CBMEM_ID_ROMSTAGE_INFO: printk(BIOS_DEBUG, "ROMSTAGE "); break; - default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); - } - printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base); - printk(BIOS_DEBUG, "%08llx\n", cbmem_toc[i].size); + cbmem_print_entry(i, cbmem_toc[i].id, cbmem_toc[i].base, + cbmem_toc[i].size); } } #endif diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c new file mode 100644 index 0000000..aaf5840 --- /dev/null +++ b/src/lib/cbmem_info.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <cbmem.h> +#include <stdlib.h> + +static struct cbmem_id_to_name { + u32 id; + const char *name; +} cbmem_ids[] = { + { CBMEM_ID_FREESPACE, "FREE SPACE " }, + { CBMEM_ID_GDT, "GDT " }, + { CBMEM_ID_ACPI, "ACPI " }, + { CBMEM_ID_CBTABLE, "COREBOOT " }, + { CBMEM_ID_PIRQ, "IRQ TABLE " }, + { CBMEM_ID_MPTABLE, "SMP TABLE " }, + { CBMEM_ID_RESUME, "ACPI RESUME" }, + { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, + { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, + { CBMEM_ID_SMBIOS, "SMBIOS " }, + { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, + { CBMEM_ID_MRCDATA, "MRC DATA " }, + { CBMEM_ID_CONSOLE, "CONSOLE " }, + { CBMEM_ID_ELOG, "ELOG " }, + { CBMEM_ID_COVERAGE, "COVERAGE " }, + { CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, + { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, + { CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, + { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, + { CBMEM_ID_ROOT, "CBMEM ROOT " }, +}; + +void cbmem_print_entry(int n, u32 id, u64 base, u64 size) +{ + int i; + const char *name; + + name = NULL; + for (i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { + if (cbmem_ids[i].id == id) { + name = cbmem_ids[i].name; + break; + } + } + + if (name == NULL) + printk(BIOS_DEBUG, "%08x ", id); + else + printk(BIOS_DEBUG, "%s", name); + printk(BIOS_DEBUG, "%2d. ", n); + printk(BIOS_DEBUG, "%08llx ", base); + printk(BIOS_DEBUG, "%08llx\n", size); +} diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c new file mode 100644 index 0000000..ae6c87a --- /dev/null +++ b/src/lib/dynamic_cbmem.c @@ -0,0 +1,452 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/tables.h> +#include <console/console.h> +#include <cbmem.h> +#include <string.h> +#include <stdlib.h> +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) +#include <arch/acpi.h> +#endif + +#ifndef UINT_MAX +#define UINT_MAX 4294967295U +#endif + +/* ACPI resume needs to be cleared in the fail-to-recover case, but that + * condition is only handled during ramstage. */ +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) +static inline void cbmem_handle_acpi_resume(void) +{ + /* Something went wrong, our high memory area got wiped */ + if (acpi_slp_type == 3 || acpi_slp_type == 2) + acpi_slp_type = 0; +} +#else +static inline void cbmem_handle_acpi_resume(void) {} +#endif + +/* + * The dynamic cbmem code uses a root region. The root region boundary + * addresses are determined by cbmem_top() and ROOT_MIN_SIZE. Just below + * the address returned by cbmem_top() is a pointer that points to the + * root data structure. The root data structure provides the book keeping + * for each large entry. + */ + +/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ +#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE +#define CBMEM_POINTER_MAGIC 0xc0389479 +#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC) + +/* The cbmem_root_pointer structure lives just below address returned + * from cbmem_top(). It points to the root data structure that + * maintains the entries. */ +struct cbmem_root_pointer { + u32 magic; + u32 root; +} __attribute__((packed)); + +struct cbmem_entry { + u32 magic; + u32 start; + u32 size; + u32 id; +} __attribute__((packed)); + +struct cbmem_root { + u32 max_entries; + u32 num_entries; + u32 locked; + u32 size; + struct cbmem_entry entries[0]; +} __attribute__((packed)); + + +static inline void *cbmem_top_cached(void) +{ +#if !defined(__PRE_RAM__) + static void *cached_cbmem_top; + + if (cached_cbmem_top == NULL) + cached_cbmem_top = cbmem_top(); + + return cached_cbmem_top; +#else + return cbmem_top(); +#endif +} + +static inline void *get_top_aligned(void) +{ + unsigned long top; + + /* Align down what is returned from cbmem_top(). */ + top = (unsigned long)cbmem_top_cached(); + top &= ~(DYN_CBMEM_ALIGN_SIZE - 1); + + return (void *)top; +} + +static inline void *get_root(void) +{ + unsigned long pointer_addr; + struct cbmem_root_pointer *pointer; + + pointer_addr = (unsigned long)get_top_aligned(); + pointer_addr -= sizeof(struct cbmem_root_pointer); + + pointer = (void *)pointer_addr; + if (pointer->magic != CBMEM_POINTER_MAGIC) + return NULL; + + return (void *)pointer->root; +} + +static inline void cbmem_entry_assign(struct cbmem_entry *entry, + u32 id, u32 start, u32 size) +{ + entry->magic = CBMEM_ENTRY_MAGIC; + entry->start = start; + entry->size = size; + entry->id = id; +} + +static inline const struct cbmem_entry * +cbmem_entry_append(struct cbmem_root *root, u32 id, u32 start, u32 size) +{ + struct cbmem_entry *cbmem_entry; + + cbmem_entry = &root->entries[root->num_entries]; + root->num_entries++; + + cbmem_entry_assign(cbmem_entry, id, start, size); + + return cbmem_entry; +} + +void cbmem_initialize_empty(void) +{ + unsigned long pointer_addr; + unsigned long root_addr; + unsigned long max_entries; + struct cbmem_root *root; + struct cbmem_root_pointer *pointer; + + /* Place the root pointer and the root. The number of entries is + * dictated by difference between the root address and the pointer + * where the root address is aligned down to + * DYN_CBMEM_ALIGN_SIZE. The pointer falls just below the + * address returned by get_top_aligned(). */ + pointer_addr = (unsigned long)get_top_aligned(); + root_addr = pointer_addr - ROOT_MIN_SIZE; + root_addr &= ~(DYN_CBMEM_ALIGN_SIZE - 1); + pointer_addr -= sizeof(struct cbmem_root_pointer); + + max_entries = (pointer_addr - (root_addr + sizeof(*root))) / + sizeof(struct cbmem_entry); + + pointer = (void *)pointer_addr; + pointer->magic = CBMEM_POINTER_MAGIC; + pointer->root = root_addr; + + root = (void *)root_addr; + root->max_entries = max_entries; + root->num_entries = 0; + root->locked = 0; + root->size = pointer_addr - root_addr + + sizeof(struct cbmem_root_pointer); + + /* Add an entry covering the root region. */ + cbmem_entry_append(root, CBMEM_ID_ROOT, root_addr, root->size); + + printk(BIOS_DEBUG, "CBMEM: root @ %p %d entries.\n", + root, root->max_entries); + + cbmem_arch_init(); +} + +static inline int cbmem_fail_recovery(void) +{ + cbmem_initialize_empty(); + cbmem_handle_acpi_resume(); + return 1; +} + +static int validate_entries(struct cbmem_root *root) +{ + unsigned int i; + u32 current_end; + + current_end = (u32)get_top_aligned(); + + printk(BIOS_DEBUG, "CBMEM: recovering %d/%d entries from root @ %p\n", + root->num_entries, root->max_entries, root); + + /* Check that all regions are properly aligned and are just below + * the previous entry */ + for (i = 0; i < root->num_entries; i++) { + struct cbmem_entry *entry = &root->entries[i]; + + if (entry->magic != CBMEM_ENTRY_MAGIC) + return -1; + + if (entry->start & (DYN_CBMEM_ALIGN_SIZE - 1)) + return -1; + + if (entry->start + entry->size != current_end) + return -1; + + current_end = entry->start; + } + + return 0; +} + +int cbmem_initialize(void) +{ + struct cbmem_root *root; + void *top_according_to_root; + + root = get_root(); + + /* No recovery possible since root couldn't be recovered. */ + if (root == NULL) + return cbmem_fail_recovery(); + + /* Sanity check the root. */ + top_according_to_root = (void *)(root->size + (unsigned long)root); + if (get_top_aligned() != top_according_to_root) + return cbmem_fail_recovery(); + + if (root->num_entries > root->max_entries) + return cbmem_fail_recovery(); + + if ((root->max_entries * sizeof(struct cbmem_entry)) > + (root->size - sizeof(struct cbmem_root_pointer) - sizeof(*root))) + return cbmem_fail_recovery(); + + /* Validate current entries. */ + if (validate_entries(root)) + return cbmem_fail_recovery(); + +#if defined(__PRE_RAM__) + /* Lock the root in the romstage on a recovery. The assumption is that + * recovery is called during romstage on the S3 resume path. */ + root->locked = 1; +#endif + + cbmem_arch_init(); + + /* Recovery successful. */ + return 0; +} + +static void *cbmem_base(void) +{ + struct cbmem_root *root; + u32 low_addr; + + root = get_root(); + + if (root == NULL) + return NULL; + + low_addr = (u32)root; + + /* Assume the lowest address is the last one added. */ + if (root->num_entries > 0) { + low_addr = root->entries[root->num_entries - 1].start; + } + + return (void *)low_addr; +} + + +const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) +{ + struct cbmem_root *root; + const struct cbmem_entry *entry; + unsigned long base;; + u32 size; + u32 aligned_size; + + entry = cbmem_entry_find(id); + + if (entry != NULL) + return entry; + + /* Only handle sizes <= UINT_MAX internally. */ + if (size64 > (u64)UINT_MAX) + return NULL; + + size = size64; + + root = get_root(); + + if (root == NULL) + return NULL; + + /* Nothing can be added once it is locked down. */ + if (root->locked) + return NULL; + + if (root->max_entries == root->num_entries) + return NULL; + + aligned_size = ALIGN(size, DYN_CBMEM_ALIGN_SIZE); + base = (unsigned long)cbmem_base(); + base -= aligned_size; + + return cbmem_entry_append(root, id, base, aligned_size); +} + +void *cbmem_add(u32 id, u64 size) +{ + const struct cbmem_entry *entry; + + entry = cbmem_entry_add(id, size); + + if (entry == NULL) + return NULL; + + return cbmem_entry_start(entry); +} + +/* Retrieve a region provided a given id. */ +const struct cbmem_entry *cbmem_entry_find(u32 id) +{ + struct cbmem_root *root; + const struct cbmem_entry *entry; + unsigned int i; + + root = get_root(); + + if (root == NULL) + return NULL; + + entry = NULL; + + for (i = 0; i < root->num_entries; i++) { + if (root->entries[i].id == id) { + entry = &root->entries[i]; + break; + } + } + + return entry; +} + +void *cbmem_find(u32 id) +{ + const struct cbmem_entry *entry; + + entry = cbmem_entry_find(id); + + if (entry == NULL) + return NULL; + + return cbmem_entry_start(entry); +} + +/* Remove a reserved region. Returns 0 on success, < 0 on error. Note: A region + * cannot be removed unless it was the last one added. */ +int cbmem_entry_remove(const struct cbmem_entry *entry) +{ + unsigned long entry_num; + struct cbmem_root *root; + + root = get_root(); + + if (root == NULL) + return -1; + + if (root->num_entries == 0) + return -1; + + /* Nothing can be removed. */ + if (root->locked) + return -1; + + entry_num = entry - &root->entries[0]; + + /* If the entry is the last one in the root it can be removed. */ + if (entry_num == (root->num_entries - 1)) { + root->num_entries--; + return 0; + } + + return -1; +} + +u64 cbmem_entry_size(const struct cbmem_entry *entry) +{ + return entry->size; +} + +void *cbmem_entry_start(const struct cbmem_entry *entry) +{ + return (void *)entry->start; +} + + +#if !defined(__PRE_RAM__) +/* selected cbmem can be initialized early in ramstage. Additionally, that + * means cbmem console can be reinitialized early as well. The post_device + * function is empty since cbmem was initialized early in ramstage. */ +void init_cbmem_pre_device(void) +{ + cbmem_initialize(); +#if CONFIG_CONSOLE_CBMEM + cbmemc_reinit(); +#endif /* CONFIG_CONSOLE_CBMEM */ +} + +void init_cbmem_post_device(void) {} + +void cbmem_add_lb_mem(struct lb_memory *mem) +{ + unsigned long base; + unsigned long top; + + base = (unsigned long)cbmem_base(); + top = (unsigned long)get_top_aligned(); + lb_add_memory_range(mem, LB_MEM_TABLE, base, top - base); +} + +void cbmem_list(void) +{ + unsigned int i; + struct cbmem_root *root; + + root = get_root(); + + if (root == NULL) + return; + + for (i = 0; i < root->num_entries; i++) { + struct cbmem_entry *entry; + + entry = &root->entries[i]; + + cbmem_print_entry(i, entry->id, entry->start, entry->size); + } +} +#endif /* __PRE_RAM__ */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index b29cc93..bc18989 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -94,6 +94,7 @@ void hardwaremain(int boot_complete) !cbmem_get_table_location(&high_tables_base, &high_tables_size)) cbmem_initialize(); #endif + init_cbmem_pre_device(); timestamp_stash(TS_DEVICE_ENUMERATE); @@ -121,10 +122,8 @@ void hardwaremain(int boot_complete) timestamp_stash(TS_DEVICE_DONE); - cbmem_initialize(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif + init_cbmem_post_device(); + timestamp_sync(); #if CONFIG_HAVE_ACPI_RESUME

1 0

New patch to review for coreboot: 715c6e8 haswell: drop memory reservation for sandybridge GPU bug
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2847 -gerrit commit 715c6e8a6b6b8e158b8ac5635800af31163c3205 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Mar 7 14:20:13 2013 -0800 haswell: drop memory reservation for sandybridge GPU bug This is not needed in haswell. Change-Id: I23817c2e01be33855f9d5a5e389e8ccb7954c0e2 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/haswell/acpi/haswell.asl | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 49d55e7..1634fe3 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -42,11 +42,6 @@ Device (PDRC) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif - - /* Required for SandyBridge sighting 3715511 */ - /* FIXME: Is this still required? */ - Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) - Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) }) // Current Resource Settings

1 0

← Newer
1
...
5
6
7
8
9
10
11
...
79
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2013