the following patch was just integrated into master:
commit 665e3d23f0ca5bfac0d1ad9b7a8cde383ec56289
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Wed Feb 27 09:54:47 2013 -0800
link/graphics: add functions to support aux channel communications
For full integration of FUI into coreboot, we need aux channel
communcations. The intel_dp.c is a file taken from Linux and is
used for aux channel comms. This file has been cut down to work
with coreboot. For now it is associated with the link mainboard
until we get a better handle on how this all fits together. This
code is almost certainly usable on other platforms in the long term.
But one step at a time.
Change-Id: I7be4c56e0a7903f3901ac86e12b28f3bdc0f7947
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Reviewed-on: http://review.coreboot.org/2834
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 22:32:59 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Mar 19 22:42:39 2013, giving +2
See http://review.coreboot.org/2834 for details.
-gerrit
the following patch was just integrated into master:
commit bba809042191bd3e421bdec0b974ce697e85bcba
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Mar 14 15:24:57 2013 -0700
armv7/exynos/snow: new cache maintenance API
This adds a new API for cache maintenance operations. The idea is
to be more explicit about operations that are going on so it's easier
to manage branch predictor, cache, and TLB cleans and invalidations.
Also, this adds some operations that were missing but required early
on, such as branch predictor invalidation. Instruction and sync
barriers were wrong earlier as well since the imported API assumed
we compield with -march=armv5 (which we don't) and was missing
wrappers for the native ARMv7 ISB/DSB/DMB instructions.
For now, this is a start and it gives us something we can easily use
in libpayload for doing things like cleaning and invalidating dcache
when doing DMA transfers.
TODO:
- Set cache policy explicitly before re-enabling. Right now it's left
at default.
- Finish deprecating old cache maintenance API.
- We do an extra icache/dcache flush when going from bootblock to
romstage.
Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2729
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 20:03:30 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Mar 19 22:23:45 2013, giving +2
See http://review.coreboot.org/2729 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2842
-gerrit
commit 87885b4f74dfcddfc4a3cc25b3898b98d2608ba1
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Mar 19 13:20:47 2013 -0700
Intel: Update CPU microcode script
for latest URL of their microcode tar ball
Change-Id: I3da2bdac4b2ca7d3f48b20ed389f6a47275d24fe
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
---
src/cpu/intel/microcode/update-microcodes.sh | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel/microcode/update-microcodes.sh b/src/cpu/intel/microcode/update-microcodes.sh
index 8bdf0e7..febf6f9 100755
--- a/src/cpu/intel/microcode/update-microcodes.sh
+++ b/src/cpu/intel/microcode/update-microcodes.sh
@@ -18,10 +18,10 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-MICROCODE_VERSION=20111110
+MICROCODE_VERSION=20130222
MICROCODE_ARCHIVE=microcode-$MICROCODE_VERSION.tgz
MICROCODE_FILE=microcode.dat
-INTEL_MICROCODE=http://downloadmirror.intel.com/20728/eng/$MICROCODE_ARCHIVE
+INTEL_MICROCODE=http://downloadmirror.intel.com/22508/eng/$MICROCODE_ARCHIVE
#
# Getting Intel(R) Microcode