coreboot March 2013

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Patch set updated for coreboot: 7ccda20 cbfstool locate: Rename -a align switch to -P for page size
by Hung-Te Lin 19 Mar '13

19 Mar '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2730 -gerrit commit 7ccda20c9471ada13b333e6f9e52483c1db0894e Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Mar 19 12:17:12 2013 +0800 cbfstool locate: Rename -a align switch to -P for page size cbfstool usage change: The "-a" parameter for "cbfstool locate" has changed to "-P/--page-size". The "locate" command was used to find a place to store ELF stage image in one memory page. Its argument "-a (alignment)" was actually specifying the page size instead of doing memory address alignment. This can be confusing when people are trying to put a blob in aligned location (ex, microcode needs to be aligned in 0x10), and see this: cbfstool coreboot.rom locate -f test.bin -n test -a 0x40000 # output: 0x44, which does not look like aligned to 0x40000. To prevent confusion, it's now renamed to "-P/--page-size". Verified by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731 --- src/arch/armv7/Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 2 +- util/cbfstool/cbfstool.c | 15 ++++++++++----- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 39c115e..8601112 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -282,7 +282,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin @printf " generating base_xip.txt\n" rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cc7bfc2..433b434 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -393,7 +393,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 97fd88d..e918d89 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -50,6 +50,7 @@ static struct param { uint32_t entrypoint; uint32_t size; uint32_t alignment; + uint32_t pagesize; uint32_t offset; uint32_t top_aligned; comp_algo algo; @@ -355,12 +356,12 @@ static int cbfs_locate(void) } address = cbfs_locate_entry(&image, param.name, buffer.size, - param.alignment); + param.pagesize); buffer_delete(&buffer); if (address == -1) { - ERROR("'%s' can't fit in CBFS for align 0x%x.\n", - param.name, param.alignment); + ERROR("'%s' can't fit in CBFS for page-size %#x.\n", + param.name, param.pagesize); cbfs_image_delete(&image); return 1; } @@ -421,7 +422,7 @@ static const struct command commands[] = { {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"remove", "n:vh?", cbfs_remove}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, - {"locate", "f:n:a:Tvh?", cbfs_locate}, + {"locate", "f:n:P:Tvh?", cbfs_locate}, {"print", "vh?", cbfs_print}, {"extract", "n:f:vh?", cbfs_extract}, }; @@ -437,6 +438,7 @@ static struct option long_options[] = { {"size", required_argument, 0, 's' }, {"bootblock", required_argument, 0, 'B' }, {"alignment", required_argument, 0, 'a' }, + {"page-size", required_argument, 0, 'P' }, {"offset", required_argument, 0, 'o' }, {"file", required_argument, 0, 'f' }, {"arch", required_argument, 0, 'm' }, @@ -468,7 +470,7 @@ static void usage(char *name) "Remove a component\n" " create -s size -B bootblock -m ARCH [-a align] [-o offset] " "Create a ROM file\n" - " locate -f FILE -n NAME [-a align] [-T] " + " locate -f FILE -n NAME [-P page-size] [-T] " "Find a place for a file of that size\n" " print " "Show the contents of the ROM\n" @@ -572,6 +574,9 @@ int main(int argc, char **argv) case 'a': param.alignment = strtoul(optarg, NULL, 0); break; + case 'P': + param.pagesize = strtoul(optarg, NULL, 0); + break; case 'o': param.offset = strtoul(optarg, NULL, 0); break;

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Patch merged into coreboot/master: e29e2ff Include byteorder.h for the definition of ntohl in romstage.c
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit e29e2ff8e8fb919c1074e3d31076f83b0a1aac45 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Jan 18 16:50:25 2013 +0800 Include byteorder.h for the definition of ntohl in romstage.c A fix to eliminate warnings when building romstage files with ChromeOS compilers Change-Id: Ia5d7bbdde3aa3439fd493f5795f2cc2bf4c4c187 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2781 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 19 02:42:29 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Mar 19 05:26:28 2013, giving +2 See http://review.coreboot.org/2781 for details. -gerrit

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Patch merged into coreboot/master: 8c20399 haswell: wait 10ms after INIT IPI
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit 8c20399a42a6bb76f537042b4d7ba725ac78f10c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 17 11:13:46 2013 -0600 haswell: wait 10ms after INIT IPI There should be a fixed 10ms wait after sending an INIT IPI. The previous implementation was just waiting up to 10ms for the IPI to complete the send. That is not correct. The 10ms is unconditional according to the documentation. No ill effects were observed with the previous behavior, but it's important to follow the documentation. Change-Id: Ib31d49ac74808f6eb512310e9f54a8f4abc3bfd7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2780 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 19 02:31:25 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Mar 19 05:26:12 2013, giving +2 See http://review.coreboot.org/2780 for details. -gerrit

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Patch merged into coreboot/master: 305b1f0 haswell: Parallel AP bringup
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit 305b1f0d30b68c310d4dfa7e1a5f432769a65b31 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 15 08:27:05 2013 -0600 haswell: Parallel AP bringup This patch parallelizes the AP startup for Haswell-based devices. It does not touch the generic secondary startup code. Instead it provides its own MP support matching up with the Haswell BWG. It seemed to be too much trouble to support the old startup way and this new way. Because of that parallel loading is the only thing supported. A couple of things to note: 1. Micrcode needs to be loaded twice. Once before MTRR and caching is enabled. And a second time after SMM relocation. 2. The sipi_vector is entirely self-contained. Once it is loaded and written back to RAM the APs do not access memory outside of the sipi_vector load location until a sync up in ramstage. 3. SMM relocation is kicked off by an IPI to self w/ SMI set as the destination mode. The following are timings from cbmem with dev mode disabled and recovery mode enabled to boot directly into the kernel. This was done on the baskingridge CRB with a 4-core 8-thread CPU and 2 DIMMs 1GiB each. The kernel has console enabled on the serial port. Entry 70 is the device initialization, and that is where the APs are brought up. With these two examples it looks to shave off ~200 ms of boot time. Before: 1:55,382 2:57,606 (2,223) 3:3,108,983 (3,051,377) 4:3,110,084 (1,101) 8:3,113,109 (3,024) 9:3,156,694 (43,585) 10:3,156,815 (120) 30:3,157,110 (295) 40:3,158,180 (1,069) 50:3,160,157 (1,977) 60:3,160,366 (208) 70:4,221,044 (1,060,677) 75:4,221,062 (18) 80:4,227,185 (6,122) 90:4,227,669 (484) 99:4,265,596 (37,927) 1000:4,267,822 (2,225) 1001:4,268,507 (685) 1002:4,268,780 (272) 1003:4,398,676 (129,896) 1004:4,398,979 (303) 1100:7,477,601 (3,078,621) 1101:7,480,210 (2,608) After: 1:49,518 2:51,778 (2,259) 3:3,081,186 (3,029,407) 4:3,082,252 (1,066) 8:3,085,137 (2,884) 9:3,130,339 (45,202) 10:3,130,518 (178) 30:3,130,544 (26) 40:3,131,125 (580) 50:3,133,023 (1,897) 60:3,133,278 (255) 70:4,009,259 (875,980) 75:4,009,273 (13) 80:4,015,947 (6,674) 90:4,016,430 (482) 99:4,056,265 (39,835) 1000:4,058,492 (2,226) 1001:4,059,176 (684) 1002:4,059,450 (273) 1003:4,189,333 (129,883) 1004:4,189,770 (436) 1100:7,262,358 (3,072,588) 1101:7,263,926 (1,567) Booted the baskingridge board as noted above. Also analyzed serial messages with pcserial enabled. Change-Id: Ifedc7f787953647c228b11afdb725686e38c4098 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 19 02:20:03 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Mar 19 05:15:22 2013, giving +2 See http://review.coreboot.org/2779 for details. -gerrit

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Patch merged into coreboot/master: 98ffb42 intel microcode: split up microcode loading stages
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit 98ffb426f40593f930388c006f8058c199defff4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 15 15:15:32 2013 -0600 intel microcode: split up microcode loading stages This patch only applies to CONFIG_MICROCODE_IN_CBFS. The intel microcode update routine would always walk the CBFS for the microcode file. Then it would loop through the whole file looking for a match then load the microcode. This process was maintained for intel_update_microcode_from_cbfs(), however 2 new functions were exported: 1. const void *intel_microcode_find(void) 2. void intel_microcode_load_unlocked(const void *microcode_patch) The first locates a matching microcode while the second loads that mircocode. These new functions can then be used to cache the found microcode blob w/o having to re-walk the CBFS. Booted baskingridge board to Linux and noted that all microcode revisions match on all the CPUs. Change-Id: Ifde3f3e5c100911c4f984dd56d36664a8acdf7d5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2778 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 19 02:09:13 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Mar 19 05:11:50 2013, giving +2 See http://review.coreboot.org/2778 for details. -gerrit

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Patch set updated for coreboot: 5748b46 armv7/exynos/snow: set up caches properly
by David Hendricks 19 Mar '13

19 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2729 -gerrit commit 5748b462f1c22cd5ba41d8c09563fa2d872ef909 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 14 15:24:57 2013 -0700 armv7/exynos/snow: set up caches properly ** do not submit ** This (hopefully) sets up caches more carefully than we were doing before. This patch needs a bit more testing before going in. TODO: - Get rid of imported CP15ISB and isb() macros. They are wrong for ARMv7 -- it was assumed in u-boot that the code would be compiled with -march=armv5 (see comment in armv7.h). - Clean up. Most of this is now done in a generic manner in bootblock_simple, so a lot of earlier code can go away. - Set cache policy explicitly before re-enabling - Replace imported cache routines (and use BSD license to match libpayload?) Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 71 +++++++++++++++++++++++++++++++ src/arch/armv7/include/arch/io.h | 3 +- src/arch/armv7/include/cache.h | 56 ------------------------ src/arch/armv7/include/system.h | 8 +++- src/arch/armv7/lib/Makefile.inc | 6 +++ src/arch/armv7/lib/cache-cp15.c | 3 +- src/arch/armv7/lib/cache_v7.c | 2 +- src/cpu/samsung/exynos5250/Makefile.inc | 1 - src/cpu/samsung/exynos5250/bootblock.c | 2 + src/cpu/samsung/exynos5250/exynos_cache.c | 8 +--- src/mainboard/google/snow/ramstage.c | 15 ------- src/mainboard/google/snow/romstage.c | 37 +++++----------- 12 files changed, 101 insertions(+), 111 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 0132b87..7012e17 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -20,6 +20,7 @@ */ #include <bootblock_common.h> +#include <arch/cache.h> #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> @@ -27,6 +28,58 @@ #include "stages.c" +static void armv7_invalidate_caches(void) +{ + uint32_t clidr; + int level; + + /* Invalidate branch predictor */ + bpiall(); + + /* Iterate thru each cache identified in CLIDR and invalidate */ + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x0: + /* no cache */ + break; + case 0x1: + /* icache only */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + break; + case 0x2: + case 0x4: + /* dcache only or unified cache */ + dcache_invalidate_all(); + break; + case 0x3: + /* separate icache and dcache */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + + csselr = level < 1; + write_csselr(csselr); + dcache_invalidate_all(); + break; + default: + /* reserved */ + break; + } + } + + /* Invalidate TLB */ + /* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction + * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't + * really seem true for Cortex-A15? */ + tlb_invalidate_all(); +} + static int boot_cpu(void) { /* @@ -41,6 +94,24 @@ void main(void) { const char *stage_name = "fallback/romstage"; void *entry; + uint32_t sctlr; + + /* Globally disable MMU, caches, and branch prediction (these should + * be disabled by default on reset) */ + sctlr = read_sctlr(); + sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); + write_sctlr(sctlr); + + armv7_invalidate_caches(); + + /* + * Re-enable caches and branch prediction. MMU will be set up later. + * Note: If booting from USB, we need to disable branch prediction + * before copying from USB into RAM (FIXME: why?) + */ + sctlr = read_sctlr(); + sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I; + write_sctlr(sctlr); if (boot_cpu()) { bootblock_cpu_init(); diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index 3bbd529..623c305 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -21,6 +21,7 @@ #define __ASM_ARM_IO_H #include <types.h> +#include <arch/cache.h> /* for dmb() */ #include <arch/byteorder.h> static inline void sync(void) @@ -96,7 +97,7 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ -#define dmb() __asm__ __volatile__ ("" : : : "memory") +//#define dmb() __asm__ __volatile__ ("" : : : "memory") #define __iormb() dmb() #define __iowmb() dmb() diff --git a/src/arch/armv7/include/cache.h b/src/arch/armv7/include/cache.h deleted file mode 100644 index cf8fb5a..0000000 --- a/src/arch/armv7/include/cache.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -/* - * Invalidate L2 Cache using co-proc instruction - */ -static inline void invalidate_l2_cache(void) -{ - unsigned int val=0; - - asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" - : : "r" (val) : "cc"); - isb(); -} - -void l2_cache_enable(void); -void l2_cache_disable(void); - -/* - * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We - * use that value for aligning DMA buffers unless the board config has specified - * an alternate cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 64 -#endif - -inline void dram_bank_mmu_setup(unsigned long start, unsigned long size); - -#endif /* _ASM_CACHE_H */ diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index 053df8d..d4e778d 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -43,13 +43,15 @@ */ #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" -#define isb() __asm__ __volatile__ ("" : : : "memory") +/* FIXME: conflicts with new implementation in cache.c */ +//#define isb() __asm__ __volatile__ ("" : : : "memory") #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #define arch_align_stack(x) (x) #ifndef __ASSEMBLER__ +#include <arch/cache.h> /* for isb() */ static inline unsigned int get_cr(void) { unsigned int val; @@ -61,7 +63,7 @@ static inline void set_cr(unsigned int val) { asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : : "r" (val) : "cc"); - isb(); + isb(); /* ref: B3.10.2 of ARM Arch Ref. Manual for ARMv7 */ } /* options available for data cache on each page */ @@ -97,6 +99,8 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop); void mmu_setup(unsigned long start, unsigned long size); +void v7_inval_tlb(void); + void arm_init_before_mmu(void); /* diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 508f776..0741afa 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,8 +1,12 @@ +#FIXME: cache_v7 and cache-cp15 will go away eventually + bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c +bootblock-y += cache.c bootblock-y += cache_v7.c bootblock-y += cache-cp15.c +romstage-y += cache.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c @@ -14,6 +18,8 @@ ramstage-y += div0.c #ramstage-y += memcpy.S #ramstage-y += memset.S ramstage-y += syslib.c +ramstage-y += cache.c +ramstage-y += cache-cp15.c ramstage-y += cache_v7.c #FIXME(dhendrix): should this be a config option? diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index e08ea57..32f3c79 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -123,8 +123,7 @@ inline void mmu_setup(unsigned long start, unsigned long size_mb) int i; u32 reg; - arm_init_before_mmu(); - +// arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c index 31072c7..1764351 100644 --- a/src/arch/armv7/lib/cache_v7.c +++ b/src/arch/armv7/lib/cache_v7.c @@ -226,7 +226,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* Invalidate TLB */ -static void v7_inval_tlb(void) +void v7_inval_tlb(void) { /* Invalidate entire unified TLB */ asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 2774b12..961b719 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -30,7 +30,6 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c -ramstage-y += exynos_cache.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c index 949468f..4995dc2 100644 --- a/src/cpu/samsung/exynos5250/bootblock.c +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <armv7.h> + void bootblock_cpu_init(void); void bootblock_cpu_init(void) { diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index 7f4effe..87eded5 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -34,15 +34,11 @@ enum l2_cache_params { }; -/* FIXME(dhendrix): maybe move this to a romstage-specific file? */ -#ifdef __PRE_RAM__ void enable_caches(void) { - /* Enable D-cache. I-cache is already enabled in start.S */ - /* can't use it anyway -- it has dependencies we have to fix. */ - //dcache_enable(); + icache_enable(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + dcache_enable(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); } -#endif /* * Set L2 cache parameters diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index e4d53cf..687f9b1 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,22 +23,10 @@ #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/power.h> -#include <system.h> /* FIXME: for testing cache */ -static void cp_delay(void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - static inline uint32_t read_clidr(void) { uint32_t val = 0; asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); - isb(); return val; } @@ -46,7 +34,6 @@ static inline uint32_t read_ccsidr(void) { uint32_t val = 0; asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); - isb(); return val; } @@ -54,7 +41,6 @@ static inline uint32_t read_csselr(void) { uint32_t val = 0; asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val)); - isb(); return val; } @@ -66,7 +52,6 @@ static inline void write_csselr(uint32_t val) * Bit 0 - 0 = data or unified cache, 1 = instruction cache */ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val)); - isb(); } #ifndef __mask diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index ea2feec..c90be6e 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -18,12 +18,12 @@ */ #include <types.h> -#include <system.h> -#include <cache.h> +#include <armv7.h> #include <cbfs.h> #include <common.h> +#include <arch/cache.h> #include <arch/gpio.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -52,20 +52,6 @@ static int board_wakeup_permitted(void) } #endif -/* - * Set/clear program flow prediction and return the previous state. - */ -static int config_branch_prediction(int set_cr_z) -{ - unsigned int cr; - - /* System Control Register: 11th bit Z Branch prediction enable */ - cr = get_cr(); - set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); - - return cr & CR_Z; -} - static void initialize_s5p_mshc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -95,12 +81,14 @@ void main(void) int ret; void *entry; - /* FIXME: if we boot from USB, we need to disable branch prediction - * before copying from USB into RAM */ - config_branch_prediction(1); - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* + * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. + * Also, we should only call power_init() on cold boot. + */ + power_init(); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = get_mem_timings(); @@ -109,12 +97,6 @@ void main(void) console_init(); - /* - * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. - * Also, we should only call power_init() on cold boot. - */ - power_init(); - if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); while(1); @@ -132,7 +114,8 @@ void main(void) while(1); } - mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + /* Set up MMU and caches */ + mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); initialize_s5p_mshc();

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New patch to review for coreboot: fde3707 Butterfly, Stout: Force SATA link speed to 3 Gbps
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2823 -gerrit commit fde3707653bd57ea896df6e6da7497ab48339e33 Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Thu Mar 14 11:03:59 2013 -0700 Butterfly, Stout: Force SATA link speed to 3 Gbps Force link speed on these platforms to 3 Gbps to defeat buggy SATA drives. Change-Id: Ia38a7c486fb1f4469cd67ca5244bbf61f877d556 Signed-off-by: Shawn Nematbakhsh <shawnn(a)google.com> --- src/mainboard/google/butterfly/devicetree.cb | 5 ++++- src/mainboard/google/stout/devicetree.cb | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index ca8118a..e7a50c0 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -58,7 +58,10 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" - register "sata_port_map" = "0x3" #enable SATA ports 0 & 1 + # Enable SATA ports 0 & 1 + register "sata_port_map" = "0x3" + # Set max SATA speed to 3.0 Gb/s + register "sata_interface_speed_support" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index c58a8d6..6e02020 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -60,6 +60,8 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" + # Set max SATA speed to 3.0 Gb/s + register "sata_interface_speed_support" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069"

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New patch to review for coreboot: 0f23c9c rmodule: correct ordering of bss clearing
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2822 -gerrit commit 0f23c9c1655b2adc7c7a248c7fa4942683d78060 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 17:00:39 2013 -0600 rmodule: correct ordering of bss clearing This patch fixes an issue for rmodules which are copied into memory at the final load/link location. If the bss section is cleared for that rmodule the relocation could not take place properly since the relocation information was wiped by act of clearing the bss. The reason is that the relocation information resides at the same address as the bss section. Correct this issue by performing the relocation before clearing the bss. Change-Id: I01a124a8201321a9eaf6144c743fa818c0f004b4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/rmodule.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 60c89f0..d36f9f3 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -241,14 +241,18 @@ static int __rmodule_load(void *base, struct rmodule *module, int clear_bss) * In order to load the module at a given address, the following steps * take place: * 1. Copy payload to base address. - * 2. Clear the bss segment. - * 3. Adjust relocations within the module to new base address. + * 2. Adjust relocations within the module to new base address. + * 3. Clear the bss segment last since the relocations live where + * the bss is. If an rmodule is being loaded from its load + * address the relocations need to be processed before the bss. */ module->location = base; rmodule_copy_payload(module); + if (rmodule_relocate(module)) + return -1; if (clear_bss) rmodule_clear_bss(module); - return rmodule_relocate(module); + return 0; } int rmodule_load(void *base, struct rmodule *module)

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New patch to review for coreboot: b61b3eb rmodule: add string functions to rmodules class
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2821 -gerrit commit b61b3ebb726a956c987c311129c23ae076657733 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 1 16:56:34 2013 -0600 rmodule: add string functions to rmodules class The standard string functions memcmp(), memset(), and memcpy() are needed by most programs. The rmodules class provides a way to build objects for the rmodules class. Those programs most likely need the string functions. Therefore provide those standard functions to be used by any generic rmodule program. Change-Id: I2737633f03894d54229c7fa7250c818bf78ee4b7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/lib/Makefile.inc | 3 +++ src/lib/Makefile.inc | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 49d7e9e..82f4e62 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -20,4 +20,7 @@ smm-y += memset.c smm-y += memcpy.c smm-y += rom_media.c +rmodules-y += memset.c +rmodules-y += memcpy.c + $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index fe04e43..fe57f9f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -29,12 +29,15 @@ bootblock-y += memcmp.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c +rmodules-y += memset.c endif romstage-y += memchr.c ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) romstage-y += memcpy.c +rmodules-y += memcpy.c endif romstage-y += memcmp.c +rmodules-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c #romstage-y += lzmadecode.c @@ -126,3 +129,4 @@ $(strip $(1)): $(strip $(2)) $$(RMODULE_LDSCRIPT) $$(obj)/ldoptions endef endif +

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New patch to review for coreboot: b2f33e2 lynxpoint: fix build failure on non-LP boards
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2820 -gerrit commit b2f33e24bf34b5c86b63b5d3a4206af8c541e3d5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 13 14:13:14 2013 -0500 lynxpoint: fix build failure on non-LP boards There were definitions being used from lp_gpio.h in pmutil.c that caused a build failure for non-LP boards since lp_gpio.h was not being included. We could potentially fix this by including lp_gpio.h unconditionally, but that adds the risk of re-defining macros previously defined from other includes. Instead just move the 2 definitions required directly in pmutil.c. Change-Id: I363441839353c6ce6bb56d346b87710332763cf5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/lp_gpio.h | 2 -- src/southbridge/intel/lynxpoint/pmutil.c | 6 ++++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 067b6e2..9666adc 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -28,8 +28,6 @@ #define GPIO_SER_BLINK_CS 0x20 #define GPIO_SER_BLINK_DATA 0x24 #define GPIO_ROUTE(set) (0x30 + ((set) * 4)) -#define GPIO_ALT_GPI_SMI_STS 0x50 -#define GPIO_ALT_GPI_SMI_EN 0x54 #define GPIO_RESET(set) (0x60 + ((set) * 4)) #define GPIO_GLOBAL_CONFIG 0x7c #define GPIO_IRQ_IS(set) (0x80 + ((set) * 4)) diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 64fc585..a103667 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -40,6 +40,12 @@ #include "lp_gpio.h" #endif +/* These defines are here to handle the LP variant code dynamically. If these + * values are defined in lp_gpio.h but a non-LP board is being built, the build + * will fail. */ +#define GPIO_ALT_GPI_SMI_STS 0x50 +#define GPIO_ALT_GPI_SMI_EN 0x54 + /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) {

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coreboot March 2013