coreboot March 2013

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New patch to review for coreboot: 767cd48 Tyan S8226: Use SPD read code from F15 wrapper
by Kimarie Hoot 19 Mar '13

19 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2827 -gerrit commit 767cd48350b117a7f3624b9fc36bbff3fb281df0 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Fri Mar 8 15:31:49 2013 -0700 Tyan S8226: Use SPD read code from F15 wrapper Changes: - Get rid of the s8226 mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. - s8226_select_socket() and s8226_restore_socket() started by duplicating sp5100_set_gpio() and sp5100_restore_gpio(), which were in dimmSpd.c. In addition to renaming the functions to more specifically state their purpose, some cleanup and magic number reduction was done. Change-Id: I1eaf64986ef4fa3f89aed2b69d3f9c8c913f726f Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/mainboard/tyan/s8226/BiosCallOuts.c | 73 ++++++++++- src/mainboard/tyan/s8226/Makefile.inc | 2 - src/mainboard/tyan/s8226/devicetree.cb | 6 + src/mainboard/tyan/s8226/dimmSpd.c | 222 -------------------------------- 4 files changed, 76 insertions(+), 227 deletions(-) diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 1499d54..394eccb 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -23,6 +23,62 @@ #include "Ids.h" #include "OptionsIds.h" #include "heapManager.h" +#include <northbridge/amd/agesa/family15/dimmSpd.h> +#include <arch/io.h> +#include <arch/romcc_io.h> + +#ifdef __PRE_RAM__ +/* These defines are used to select the appropriate socket for the SPD read + * because this is a multi-socket design. + */ +#define PCI_REG_GPIO_48_47_46_37_CNTRL (0xA6) +#define PCI_REG_GPIO_52_to_49_CNTRL (0x50) +#define GPIO_OUT_BIT_GPIO48 (BIT3) +#define GPIO_OUT_BIT_GPIO49 (BIT0) +#define GPIO_OUT_ENABLE_BIT_GPIO48 (BIT7) +#define GPIO_OUT_ENABLE_BIT_GPIO49 (BIT4) + +static UINT8 s8226_select_socket(UINT8 socket_id) +{ + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + UINT8 value = 0; + UINT8 gpio52_to_49 = 0; + + /* Configure GPIO49,48 to select the desired socket + * GPIO49,48 control the IDTQS3253 S1,S0 + * S1 S0 true table + * 0 0 channel 0 + * 0 1 channel 1 + * 1 0 channel 2 - Socket 0 + * 1 1 channel 3 - Socket 1 + * Note: Above is abstracted from Schematic. But actually it seems to be other way. + * 1 0 channel 2 - Socket 1 + * 1 1 channel 3 - Socket 0 + * Note: The DIMMs need to be plugged in from the farthest slot for each channel. + */ + gpio52_to_49 = pci_read_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL); + value = gpio52_to_49 | GPIO_OUT_BIT_GPIO49; // Output of GPIO49 is always forced to "1" + value &= ~(GPIO_OUT_ENABLE_BIT_GPIO49); // 0=Output Enabled, 1=Tristate + pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, value); + + value = pci_read_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL); + value &= ~(GPIO_OUT_BIT_GPIO48); + value |= (~(socket_id & 1)) << 3; // Output of GPIO48 is inverse of SocketId + value &= ~(GPIO_OUT_ENABLE_BIT_GPIO48); // 0=Output Enabled, 1=Tristate + pci_write_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL, value); + + return gpio52_to_49; +} + +static void s8226_restore_socket(UINT8 original_value) +{ + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, original_value); + + // TODO: Restore previous GPIO48 configurations? + //pci_write_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL, gpio48_47_46_37_save); +} +#endif STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -81,8 +137,6 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = }, }; -extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); - AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { UINTN i; @@ -487,7 +541,20 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); +#ifdef __PRE_RAM__ + UINT8 original_value = 0; + + if (ConfigPtr == NULL) + return AGESA_ERROR; + + original_value = s8226_select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId); + + Status = agesa_ReadSPD (Func, Data, ConfigPtr); + + s8226_restore_socket(original_value); +#else + Status = AGESA_UNSUPPORTED; +#endif return Status; } diff --git a/src/mainboard/tyan/s8226/Makefile.inc b/src/mainboard/tyan/s8226/Makefile.inc index 2aae4c0..cd56c47 100644 --- a/src/mainboard/tyan/s8226/Makefile.inc +++ b/src/mainboard/tyan/s8226/Makefile.inc @@ -22,7 +22,6 @@ romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += platform_oem.c @@ -31,7 +30,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += platform_oem.c diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb index 420e52f..f879ec5 100644 --- a/src/mainboard/tyan/s8226/devicetree.cb +++ b/src/mainboard/tyan/s8226/devicetree.cb @@ -121,6 +121,12 @@ chip northbridge/amd/agesa/family15/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end #f15 + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 + { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 + }" end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family15/root_complex diff --git a/src/mainboard/tyan/s8226/dimmSpd.c b/src/mainboard/tyan/s8226/dimmSpd.c deleted file mode 100644 index dc47674..0000000 --- a/src/mainboard/tyan/s8226/dimmSpd.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_ids.h> - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/* SP5100 GPIO 49-52 contoled by SMBUS PCI_Reg 0x52 */ -#define SP5100_GPIO37_46_47_48 0xA6 -#define SP5100_GPIO49_52 0x50 - -/** - * TODO not support all GPIO yet - * @param reg -GPIO Cntrl Register - * @param out -GPIO bitmap - * @param out -GPIO enable bitmap - * @return old setting - */ -static u8 sp5100_set_gpio(u8 reg, u8 out, u8 enable) -{ - u8 value, ret; - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS - - value = pci_read_config8(sm_dev, reg); - ret = value; - value &= ~(enable); - value |= out; - value &= ~(enable << 4); - pci_write_config8(sm_dev, reg, value); - - return ret; -} - -static void sp5100_restore_gpio(u8 reg, u8 value) -{ - device_t sm_dev = PCI_DEV(0, 0x14, 0); - pci_write_config8(sm_dev, reg, value); -} - -/*----------------------------------------------------------------------------- - * - * SPD address table - porting required - */ -static const UINT8 spdAddressLookup [2] [2] [3] = { // socket, channel, dimm - /* socket 0 */ - { - {0xA0, 0xA4, 0xA8}, - {0xA2, 0xA6, 0xAA}, - }, - /* socket 1 */ - { - {0xA0, 0xA4, 0xA8}, - {0xA2, 0xA6, 0xAA}, - }, -}; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) -{ - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - outb(0xFF, iobase + 0); // clear error status - outb(0x1F, iobase + 1); // clear error status - outb(offset, iobase + 3); // offset in eeprom - outb(address, iobase + 4); // slave address and read bit - outb(0x48, iobase + 2); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = inb(iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = inb(iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) -{ - unsigned int status; - UINT64 limit; - - outb(0xFF, iobase + 0); // clear error status - outb(0x44, iobase + 2); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = inb(iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = inb(iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) -{ - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) { - return error; - } - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, buffer + index); - if (error) - return error; - } - - return 0; -} - -static void setupFch (int ioBase) -{ - outb(66000000 / 400000 / 4, ioBase + 0x0E); /* set SMBus clock to 400 KHz */ -} - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) -{ - AGESA_STATUS status; - int spdAddress, ioBase; - u8 i2c_channel; - u8 backup; - device_t sm_dev; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - i2c_channel = (UINT8) info->SocketId; - - /* set IDTQS3253 i2c channel - * GPIO49,48 control the S1,S0 - * S1 S0 true table - * 0 0 channel 0 - * 0 1 channel 1 - * 1 0 channel 2 - Socket 0 - * 1 1 channel 3 - Socket 1 - * Note: Above is abstracted from Schemetic. But actually it seems to be other way. - * 1 0 channel 2 - Socket 1 - * 1 1 channel 3 - Socket 0 - * Note: The DIMMs need to be plugged in from the farthest slot for each channel. - */ - backup = sp5100_set_gpio(SP5100_GPIO49_52, 0x1, 0x1); - sp5100_set_gpio(SP5100_GPIO37_46_47_48, (~i2c_channel & 1) << 3, 0x1 << 3); - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) - return AGESA_ERROR; - - /* - * SMBus Base Address was set during southbridge early setup. - * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000, CIMX using 0xB00 as default - */ - sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0); - ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0); - setupFch(ioBase); - - status = readspd(ioBase, spdAddress, (void *)info->Buffer, 256); - sp5100_restore_gpio(SP5100_GPIO49_52, backup); - - return status; -}

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Patch merged into coreboot/master: fa91819 AMD Fam15: Add SPD read functions to wrapper code
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit fa91819e898b6df59fbff44c0f4dfccf2fee6e48 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Thu Mar 7 16:42:09 2013 -0700 AMD Fam15: Add SPD read functions to wrapper code Change: This is the initial step for moving the AMD F15 & HUDSON1,2,3 SPD-read callout out of the mainboard directories and into the wrapper. The next step is to update the platforms to use this routine in BiosCallouts.c and to delete the code from the mainboard directories. The DIMM addresses should be moved into devicetree.cb. If there are significant differences or reasons that the mainboard needs to override this code, it's perfectly reasonable to keep using the version in the mainboard, but this allows us to remove duplicated code and simplify the mainboard directories. Notes: This started by duplicating what was in Dinar, and was changed to use the devicetree.cb structures. Significant cleanup and magic number reduction was done as well. It is intended that this file will not be included in ramstage as the DIMM init is all done in romstage. This is similar to what was done for Parmer/Thatcher in commit 7fb692bd - http://review.coreboot.org/#/c/2190/ Fam15tn: Move SPD read from mainboards into wrapper Yes, it would make sense to split this into two separate files and move the SMBus initialization and access into the southbridge wrapper. Maybe that can come next. Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2777 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Mon Mar 18 23:05:21 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Tue Mar 19 17:08:10 2013, giving +2 See http://review.coreboot.org/2777 for details. -gerrit

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Patch merged into coreboot/master: e919837 cbfstool locate: Rename -a align switch to -P for page size
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit e91983767c64f5541bae44d3b95fa2646bc1a311 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Mar 19 12:17:12 2013 +0800 cbfstool locate: Rename -a align switch to -P for page size cbfstool usage change: The "-a" parameter for "cbfstool locate" is switched to "-P/--page-size". The "locate" command was used to find a place to store ELF stage image in one memory page. Its argument "-a (alignment)" was actually specifying the page size instead of doing memory address alignment. This can be confusing when people are trying to put a blob in aligned location (ex, microcode needs to be aligned in 0x10), and see this: cbfstool coreboot.rom locate -f test.bin -n test -a 0x40000 # output: 0x44, which does not look like aligned to 0x40000. To prevent confusion, it's now switched to "-P/--page-size". Verified by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731 Reviewed-on: http://review.coreboot.org/2730 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Mar 19 11:10:49 2013, giving +1 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Tue Mar 19 10:13:12 2013, giving +2 See http://review.coreboot.org/2730 for details. -gerrit

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New patch to review for coreboot: 6fcc378 google/snow: workaround a buggy recovery mode GPIO reading
by David Hendricks 19 Mar '13

19 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2826 -gerrit commit 6fcc378179b076a2899e3ba8462b17abf1c93800 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Mar 18 23:27:09 2013 -0700 google/snow: workaround a buggy recovery mode GPIO reading We don't really have a recovery mode GPIO. Instead it's fed into the SoC by another chip. And for whatever reason we're reading a weird value. Hard-code as a workaround. Change-Id: I02703e80c953d463706757c9398b6afda4941f8d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 1a98244..6694b59 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -63,7 +63,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: active high */ gpios->gpios[1].port = EXYNOS5_GPY1; gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); +// gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); + gpios->gpios[1].value = 0; strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); /* Lid: the "switch" comes from the EC */

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Patch set updated for coreboot: 5694e98 armv7/exynos/snow: new cache maintenance API
by David Hendricks 19 Mar '13

19 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2729 -gerrit commit 5694e98e7788aa5cfb16cb316b7fc1ea39a261cd Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 14 15:24:57 2013 -0700 armv7/exynos/snow: new cache maintenance API This adds a new API for cache maintenance operations. The idea is to be more explicit about operations that are going on so it's easier to manage branch predictor, cache, and TLB cleans and invalidations. Also, this adds some operations that were missing but required early on, such as branch predictor invalidation. Instruction and sync barriers were wrong earlier as well since the imported API assumed we compield with -march=armv5 (which we don't) and was missing wrappers for the native ARMv7 ISB/DSB/DMB instructions. For now, this is a start and it gives us something we can easily use in libpayload for doing things like cleaning and invalidating dcache when doing DMA transfers. TODO: - Set cache policy explicitly before re-enabling. Right now it's left at default. - Finish deprecating old cache maintenance API. - We do an extra icache/dcache flush when going from bootblock to romstage. Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 71 +++++++++ src/arch/armv7/include/arch/cache.h | 231 ++++++++++++++++++++++++++++++ src/arch/armv7/include/arch/io.h | 3 +- src/arch/armv7/include/cache.h | 56 -------- src/arch/armv7/include/system.h | 6 +- src/arch/armv7/lib/Makefile.inc | 6 + src/arch/armv7/lib/cache-cp15.c | 3 +- src/arch/armv7/lib/cache.c | 178 +++++++++++++++++++++++ src/arch/armv7/lib/cache_v7.c | 2 +- src/arch/armv7/stages.c | 5 +- src/cpu/samsung/exynos5250/Makefile.inc | 1 - src/cpu/samsung/exynos5250/exynos_cache.c | 11 -- src/mainboard/google/snow/romstage.c | 26 +--- 13 files changed, 502 insertions(+), 97 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 0132b87..7012e17 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -20,6 +20,7 @@ */ #include <bootblock_common.h> +#include <arch/cache.h> #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> @@ -27,6 +28,58 @@ #include "stages.c" +static void armv7_invalidate_caches(void) +{ + uint32_t clidr; + int level; + + /* Invalidate branch predictor */ + bpiall(); + + /* Iterate thru each cache identified in CLIDR and invalidate */ + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x0: + /* no cache */ + break; + case 0x1: + /* icache only */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + break; + case 0x2: + case 0x4: + /* dcache only or unified cache */ + dcache_invalidate_all(); + break; + case 0x3: + /* separate icache and dcache */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + + csselr = level < 1; + write_csselr(csselr); + dcache_invalidate_all(); + break; + default: + /* reserved */ + break; + } + } + + /* Invalidate TLB */ + /* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction + * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't + * really seem true for Cortex-A15? */ + tlb_invalidate_all(); +} + static int boot_cpu(void) { /* @@ -41,6 +94,24 @@ void main(void) { const char *stage_name = "fallback/romstage"; void *entry; + uint32_t sctlr; + + /* Globally disable MMU, caches, and branch prediction (these should + * be disabled by default on reset) */ + sctlr = read_sctlr(); + sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); + write_sctlr(sctlr); + + armv7_invalidate_caches(); + + /* + * Re-enable caches and branch prediction. MMU will be set up later. + * Note: If booting from USB, we need to disable branch prediction + * before copying from USB into RAM (FIXME: why?) + */ + sctlr = read_sctlr(); + sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I; + write_sctlr(sctlr); if (boot_cpu()) { bootblock_cpu_init(); diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h new file mode 100644 index 0000000..5125b8c --- /dev/null +++ b/src/arch/armv7/include/arch/cache.h @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef ARMV7_CACHE_H +#define ARMV7_CACHE_H + +/* SCTLR bits */ +#define SCTLR_M (1 << 0) /* MMU enable */ +#define SCTLR_A (1 << 1) /* Alignment check enable */ +#define SCTLR_C (1 << 2) /* Data/unified cache enable */ +/* Bits 4:3 are reserved */ +#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */ +/* Bit 6 is reserved */ +#define SCTLR_B (1 << 7) /* Endianness */ +/* Bits 9:8 */ +#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */ +#define SCTLR_Z (1 << 11) /* Branch prediction enable */ +#define SCTLR_I (1 << 12) /* Instruction cache enable */ +#define SCTLR_V (1 << 13) /* Low/high exception vectors */ +#define SCTLR_RR (1 << 14) /* Round Robin select */ +/* Bits 16:15 are reserved */ +#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */ +/* Bit 18 is reserved */ +/* Bits 20:19 reserved virtualization not supported */ +#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ +#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission + implies PL1 XN */ +#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */ +#define SCTLR_U (1 << 22) /* Unaligned access behavior */ +#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */ +#define SCTLR_EE (1 << 25) /* Exception endianness */ +/* Bit 26 is reserved */ +#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */ +#define SCTLR_TRE (1 << 28) /* TEX remap enable */ +#define SCTLR_AFE (1 << 29) /* Access flag enable */ +#define SCTLR_TE (1 << 30) /* Thumb exception enable */ +/* Bit 31 is reserved */ + +/* + * Sync primitives + */ + +/* data memory barrier */ +static inline void dmb(void) +{ + asm volatile ("dmb" : : : "memory"); +} + +/* data sync barrier */ +static inline void dsb(void) +{ + asm volatile ("dsb" : : : "memory"); +} + +/* instruction sync barrier */ +static inline void isb(void) +{ + asm volatile ("isb" : : : "memory"); +} + +/* + * Low-level TLB maintenance operations + */ + +/* invalidate entire data TLB */ +static inline void dtlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); +} + +/* invalidate entire instruction TLB */ +static inline void itlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); +} + +/* invalidate entire unified TLB */ +static inline void tlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); +} + +/* + * Low-level cache maintenance operations + */ + +/* branch predictor invalidate all */ +static inline void bpiall(void) +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); +} + +/* data cache clean and invalidate by MVA to PoC */ +static inline void dccimvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva)); +} + +/* data cache invalidate by set/way */ +static inline void dccisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val)); +} + +/* data cache invalidate by set/way */ +static inline void dcisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); +} + +/* data cache clean by MVA to PoC */ +static inline void dccmvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva)); +} + +/* data cache invalidate by MVA to PoC */ +static inline void dcimvac(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); +} + +/* instruction cache invalidate all by PoU */ +static inline void iciallu(void) +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); +} + +/* + * Cache co-processor (CP15) access functions + */ + +/* read cache level ID register (CLIDR) */ +static inline uint32_t read_clidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + return val; +} + +/* read cache size ID register register (CCSIDR) */ +static inline uint32_t read_ccsidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +/* read cache size selection register (CSSELR) */ +static inline uint32_t read_csselr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +/* write to cache size selection register (CSSELR) */ +static inline void write_csselr(uint32_t val) +{ + /* + * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd) + * Bit 0 - 0 = data or unified cache, 1 = instruction cache + */ + asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val)); + isb(); /* ISB to sync the change to CCSIDR */ +} + +/* read system control register (SCTLR) */ +static inline unsigned int read_sctlr(void) +{ + unsigned int val; + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "cc"); + return val; +} + +/* write system control register (SCTLR) */ +static inline void write_sctlr(unsigned int val) +{ + asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc"); + isb(); +} + +/* + * Cache maintenance API + */ + +/* invalidate all TLBs */ +void tlb_invalidate_all(void); + +/* clean and invalidate entire dcache on current level (given by CCSELR) */ +void dcache_clean_invalidate_all(void); + +/* invalidate entire dcache on current level (given by CCSELR) */ +void dcache_invalidate_all(void); + +/* invalidate and clean dcache by machine virtual address to PoC */ +void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); + +/* invalidate entire icache on current level (given by CSSELR) */ +void icache_invalidate_all(void); + +/* MMU setup by machine virtual address */ +void mmu_setup_by_mva(unsigned long start, unsigned long size); + +#endif /* ARMV7_CACHE_H */ diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index 3bbd529..623c305 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -21,6 +21,7 @@ #define __ASM_ARM_IO_H #include <types.h> +#include <arch/cache.h> /* for dmb() */ #include <arch/byteorder.h> static inline void sync(void) @@ -96,7 +97,7 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ -#define dmb() __asm__ __volatile__ ("" : : : "memory") +//#define dmb() __asm__ __volatile__ ("" : : : "memory") #define __iormb() dmb() #define __iowmb() dmb() diff --git a/src/arch/armv7/include/cache.h b/src/arch/armv7/include/cache.h deleted file mode 100644 index cf8fb5a..0000000 --- a/src/arch/armv7/include/cache.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -/* - * Invalidate L2 Cache using co-proc instruction - */ -static inline void invalidate_l2_cache(void) -{ - unsigned int val=0; - - asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" - : : "r" (val) : "cc"); - isb(); -} - -void l2_cache_enable(void); -void l2_cache_disable(void); - -/* - * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We - * use that value for aligning DMA buffers unless the board config has specified - * an alternate cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 64 -#endif - -inline void dram_bank_mmu_setup(unsigned long start, unsigned long size); - -#endif /* _ASM_CACHE_H */ diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index 053df8d..f3e9b6b 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -43,13 +43,15 @@ */ #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" -#define isb() __asm__ __volatile__ ("" : : : "memory") +/* FIXME: conflicts with new implementation in cache.c */ +//#define isb() __asm__ __volatile__ ("" : : : "memory") #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #define arch_align_stack(x) (x) #ifndef __ASSEMBLER__ +#include <arch/cache.h> /* for isb() */ static inline unsigned int get_cr(void) { unsigned int val; @@ -97,6 +99,8 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop); void mmu_setup(unsigned long start, unsigned long size); +void v7_inval_tlb(void); + void arm_init_before_mmu(void); /* diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 508f776..c248b9e 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,8 +1,12 @@ +#FIXME: cache_v7 and cache-cp15 will go away eventually + bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c +bootblock-y += cache.c bootblock-y += cache_v7.c bootblock-y += cache-cp15.c +romstage-y += cache.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c @@ -14,7 +18,9 @@ ramstage-y += div0.c #ramstage-y += memcpy.S #ramstage-y += memset.S ramstage-y += syslib.c +ramstage-y += cache.c ramstage-y += cache_v7.c +ramstage-y += cache-cp15.c #FIXME(dhendrix): should this be a config option? romstage-y += eabi_compat.c diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index e08ea57..32f3c79 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -123,8 +123,7 @@ inline void mmu_setup(unsigned long start, unsigned long size_mb) int i; u32 reg; - arm_init_before_mmu(); - +// arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c new file mode 100644 index 0000000..62ae755 --- /dev/null +++ b/src/arch/armv7/lib/cache.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Low-level cache operations for ARMv7 + */ + +#include <types.h> + +#include <arch/cache.h> + +#define bitmask(high, low) ((1UL << (high)) + \ + ((1UL << (high)) - 1) - ((1UL << (low)) - 1)) + +/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */ +/* FIXME: src/include/lib.h is difficult to work with due to romcc */ +static unsigned long log2(unsigned long u) +{ + int i = 0; + + while (u >>= 1) + i++; + + return i; +} + +void tlb_invalidate_all(void) +{ + /* + * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction + * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't + * really seem true for Cortex-A15? + */ + tlbiall(); + dtlbiall(); + itlbiall(); + isb(); + dsb(); +} + +void icache_invalidate_all(void) +{ + /* icache can be entirely invalidated with one operation. + * Note: If branch predictors are architecturally-visible, ICIALLU + * also performs a BPIALL operation (B2-1283 in arch manual) + */ + iciallu(); + isb(); +} + +enum dcache_op { + OP_DCCISW, + OP_DCISW +}; + +/* do a dcache operation on entire cache by set/way */ +static void dcache_op_set_way(enum dcache_op op) +{ + uint32_t ccsidr; + unsigned int associativity, num_sets, linesize_bytes; + unsigned int set, way; + unsigned int level; + + level = (read_csselr() >> 1) & 0x7; + + /* + * dcache must be invalidated by set/way for portability since virtual + * memory mapping is system-defined. The number of sets and + * associativity is given by CCSIDR. We'll use DCISW to invalidate the + * dcache. + */ + ccsidr = read_ccsidr(); + + /* FIXME: rounding up required here? */ + num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1; + associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1; + /* FIXME: do we need to use CTR.DminLine here? */ + linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; + + /* + * Set/way operations require an interesting bit packing. See section + * B4-35 in the ARMv7 Architecture Reference Manual: + * + * A: Log2(associativity) + * B: L+S + * L: Log2(linesize) + * S: Log2(num_sets) + * + * The bits are packed as follows: + * 31 31-A B B-1 L L-1 4 3 1 0 + * |---|-------------|--------|-------|-----|-| + * |Way| zeros | Set | zeros |level|0| + * |---|-------------|--------|-------|-----|-| + */ + for (way = 0; way < associativity; way++) { + for (set = 0; set < num_sets; set++) { + uint32_t val = 0; + val |= way << (32 - log2(associativity)); + val |= set << log2(linesize_bytes); + val |= level << 1; + switch(op) { + case OP_DCCISW: + dccisw(val); + break; + case OP_DCISW: + dcisw(val); + break; + default: + break; + } + } + } + + dsb(); +} + +void dcache_clean_invalidate_all(void) +{ + dcache_op_set_way(OP_DCCISW); +} + +void dcache_invalidate_all(void) +{ + dcache_op_set_way(OP_DCISW); +} + +static unsigned int line_bytes(void) +{ + uint32_t ccsidr; + unsigned int size; + + ccsidr = read_ccsidr(); + /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ + size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + size *= sizeof(unsigned int); /* bytes per line */ + + return size; +} + +void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) +{ + unsigned long line, i; + + line = line_bytes(); + for (i = addr & ~(line - 1); i < addr + len - 1; i += line) + dccimvac(addr); +} + +/* FIXME: wrapper around imported mmu_setup() for now */ +extern void mmu_setup(unsigned long start, unsigned long size); +void mmu_setup_by_mva(unsigned long start, unsigned long size) +{ + mmu_setup(start, size); +} diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c index 31072c7..1764351 100644 --- a/src/arch/armv7/lib/cache_v7.c +++ b/src/arch/armv7/lib/cache_v7.c @@ -226,7 +226,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* Invalidate TLB */ -static void v7_inval_tlb(void) +void v7_inval_tlb(void) { /* Invalidate entire unified TLB */ asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c index c37c1dd..038ed7c 100644 --- a/src/arch/armv7/stages.c +++ b/src/arch/armv7/stages.c @@ -33,6 +33,7 @@ #include <arch/stages.h> #include <arch/armv7/include/common.h> +#include <arch/cache.h> void stage_entry(void) { @@ -50,10 +51,10 @@ void stage_exit(void *addr) /* make sure any code we installed is written to memory. Not all ARM have * unified caches. */ - flush_dcache_all(); + dcache_clean_invalidate_all(); /* Because most stages copy code to memory, it's a safe and hygienic thing * to flush the icache here. */ - invalidate_icache_all(); + icache_invalidate_all(); doit(); } diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 2774b12..961b719 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -30,7 +30,6 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c -ramstage-y += exynos_cache.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index 7f4effe..2cb918d 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -33,17 +33,6 @@ enum l2_cache_params { CACHE_DATA_RAM_LATENCY = (2<<0) }; - -/* FIXME(dhendrix): maybe move this to a romstage-specific file? */ -#ifdef __PRE_RAM__ -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - /* can't use it anyway -- it has dependencies we have to fix. */ - //dcache_enable(); -} -#endif - /* * Set L2 cache parameters */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index ea2feec..bfb4156 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -18,12 +18,12 @@ */ #include <types.h> -#include <system.h> -#include <cache.h> +#include <armv7.h> #include <cbfs.h> #include <common.h> +#include <arch/cache.h> #include <arch/gpio.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -52,20 +52,6 @@ static int board_wakeup_permitted(void) } #endif -/* - * Set/clear program flow prediction and return the previous state. - */ -static int config_branch_prediction(int set_cr_z) -{ - unsigned int cr; - - /* System Control Register: 11th bit Z Branch prediction enable */ - cr = get_cr(); - set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); - - return cr & CR_Z; -} - static void initialize_s5p_mshc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -95,10 +81,6 @@ void main(void) int ret; void *entry; - /* FIXME: if we boot from USB, we need to disable branch prediction - * before copying from USB into RAM */ - config_branch_prediction(1); - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ /* Clock must be initialized before console_init, otherwise you may need @@ -108,7 +90,6 @@ void main(void) system_clock_init(mem, arm_ratios); console_init(); - /* * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. * Also, we should only call power_init() on cold boot. @@ -132,7 +113,8 @@ void main(void) while(1); } - mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + /* Set up MMU and caches */ + mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); initialize_s5p_mshc();

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Patch set updated for coreboot: dc5ec51 google/snow: fix a GPIO array index
by David Hendricks 19 Mar '13

19 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2825 -gerrit commit dc5ec5116cc8d1dfc7de6cd93eb5f72c1c0dd8a7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Mar 18 21:54:13 2013 -0700 google/snow: fix a GPIO array index This fixes a trivial error with the recovery mode GPIO index. Change-Id: I7290c1e23cdddaf91c9021d4e4252c0c772b6eab Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 14da49c..1a98244 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -63,7 +63,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: active high */ gpios->gpios[1].port = EXYNOS5_GPY1; gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); + gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); /* Lid: the "switch" comes from the EC */

1 0

New patch to review for coreboot: b9c7f9d snow: fix a GPIO array index
by David Hendricks 19 Mar '13

19 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2825 -gerrit commit b9c7f9d745f5ce18307a29c4a5e23436f3632ab4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Mar 18 21:54:13 2013 -0700 snow: fix a GPIO array index This fixes a trivial error with the recovery mode GPIO index. Change-Id: I7290c1e23cdddaf91c9021d4e4252c0c772b6eab Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 14da49c..1a98244 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -63,7 +63,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: active high */ gpios->gpios[1].port = EXYNOS5_GPY1; gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); + gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); /* Lid: the "switch" comes from the EC */

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Patch set updated for coreboot: 898bf71 cbfstool locate: Implement alignment switch --align/-a
by Hung-Te Lin 19 Mar '13

19 Mar '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2824 -gerrit commit 898bf71872716695d3fc9164ccce698c03087df4 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Mar 19 12:24:43 2013 +0800 cbfstool locate: Implement alignment switch --align/-a cbfstool usage change: "-a" for "cbfstool locate" can specify base address alignment. To support putting a blob in aligned location (ex, microcode needs to be aligned in 0x10), alignment (-a) is implemented into "locate" command. Verified by manually testing a file (324 bytes) with alignment=0x10: cbfstool coreboot.rom locate -f test -n test -a 0x10 # output: 0x71fdd0 cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0 cbfstool coreboot.rom print -v -v # output: test 0x71fd80 raw 324 # output: cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144 Also verified to be compatible with old behavior by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30 # output: 0x60 Change-Id: I78b549fe6097ce5cb6162b09f064853827069637 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- util/cbfstool/cbfs_image.c | 71 ++++++++++++++++++++++++++++++++-------------- util/cbfstool/cbfs_image.h | 6 ++-- util/cbfstool/cbfstool.c | 10 +++---- 3 files changed, 58 insertions(+), 29 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2cdbf23..63d6f78 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -773,7 +773,7 @@ int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, return 0; } -/* Finds a place to hold whole stage data in same memory page. +/* Finds a place to hold whole data in same memory page. */ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { if (!page) @@ -781,24 +781,44 @@ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { return (start / page) == (start + size - 1) / page; } +/* Tests if data can fit in a range by given offset: + * start ->| header_len | offset (+ size) |<- end + */ +static int is_in_range(uint32_t start, uint32_t end, uint32_t header_len, + uint32_t offset, uint32_t size) { + return (offset >= start + header_len && offset + size <= end); +} + int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size) { + uint32_t size, uint32_t page_size, uint32_t align) { struct cbfs_file *entry; size_t need_len; - uint32_t addr, addr_next, addr2, addr3, header_len; - assert(size < page_size); + uint32_t addr, addr_next, addr2, addr3, offset, header_len; + + /* Default values: allow fitting anywhere in ROM. */ + if (!page_size) + page_size = ntohl(image->header->romsize); + if (!align) + align = 1; + + if (size > page_size) + ERROR("Input file size (%d) greater than page size (%d).\n", + size, page_size); if (page_size % ntohl(image->header->align)) - WARN("locate_entry: page does not align with CBFS image.\n"); + WARN("%s: Page size (%#x) not aligned with CBFS image (%#x).\n", + __func__, page_size, ntohl(image->header->align)); /* TODO Old cbfstool always assume input is a stage file (and adding * sizeof(cbfs_stage) for header. We should fix that by adding "-t" - * (type) param in future. For right now, follow old behavior. */ + * (type) param in future. For right now, we assume cbfs_stage is the + * largest structure and add it into header size. */ + assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload)); header_len = (cbfs_calculate_file_header_size(name) + sizeof(struct cbfs_stage)); need_len = header_len + size; - // Merge empty entries to build get max available pages. + // Merge empty entries to build get max available space. cbfs_walk(image, cbfs_merge_empty_entry, NULL); /* Three cases of content location on memory page: @@ -812,14 +832,15 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, * shift-> | <header>|<content> | at starting of PAGE 2. * * case 3. (large content filling whole page) - * | PAGE 1 | PAGE 2 | PAGE 3| - * | <header>< content > | | Can't fit. If we shift content to - * | { free space . } PAGE 2, header can't fit in free - * | shift-> <header><content> space, so we must use PAGE 3. + * | PAGE 1 | PAGE 2 | PAGE 3 | + * | <header>< content > | Can't fit. If we shift content to + * |trial-> <header>< content > | PAGE 2, header can't fit in free + * | shift-> <header><content> space, so we must use PAGE 3. * - * The returned address will be used to re-link stage file, and then - * assigned to add-stage command (-b), which will be then re-calculated - * by ELF loader and positioned by cbfs_add_entry. + * The returned address can be then used as "base-address" (-b) in add-* + * commands (will be re-calculated and positioned by cbfs_add_entry_at). + * For stage targets, the address is also used to re-link stage before + * being added into CBFS. */ for (entry = cbfs_find_first_entry(image); entry && cbfs_is_valid_entry(image, entry); @@ -834,23 +855,29 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, image, entry)); if (addr_next - addr < need_len) continue; - if (is_in_same_page(addr + header_len, size, page_size)) { + + offset = align_up(addr + header_len, align); + if (is_in_same_page(offset, size, page_size) && + is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1)."); - return addr + header_len; + return offset; } addr2 = align_up(addr, page_size); - if (addr2 < addr_next && addr_next - addr2 >= size && - addr2 - addr >= header_len) { + offset = align_up(addr2, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); - return addr2; + return offset; } + /* Assume page_size >= header_len so adding one page will + * definitely provide the space for header. */ + assert(page_size >= header_len); addr3 = addr2 + page_size; - if (addr3 < addr_next && addr_next - addr3 >= size && - addr3 - addr >= header_len) { + offset = align_up(addr3, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); - return addr3; + return offset; } } return -1; diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 57bbfa1..7ad418a 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -76,10 +76,12 @@ int cbfs_remove_entry(struct cbfs_image *image, const char *name); int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, size_t len, const char *name); -/* Finds a location to put given content in same memory page. +/* Finds a location to put given content by specified criteria: + * "page_size" limits the content to fit on same memory page, and + * "align" specifies starting address alignment. * Returns a valid offset, or -1 on failure. */ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size); + uint32_t size, uint32_t page_size, uint32_t align); /* Callback function used by cbfs_walk. * Returns 0 on success, or non-zero to stop further iteration. */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index e918d89..eeb6936 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -356,12 +356,12 @@ static int cbfs_locate(void) } address = cbfs_locate_entry(&image, param.name, buffer.size, - param.pagesize); + param.pagesize, param.alignment); buffer_delete(&buffer); if (address == -1) { - ERROR("'%s' can't fit in CBFS for page-size %#x.\n", - param.name, param.pagesize); + ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, param.pagesize, param.alignment); cbfs_image_delete(&image); return 1; } @@ -422,7 +422,7 @@ static const struct command commands[] = { {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"remove", "n:vh?", cbfs_remove}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, - {"locate", "f:n:P:Tvh?", cbfs_locate}, + {"locate", "f:n:P:a:Tvh?", cbfs_locate}, {"print", "vh?", cbfs_print}, {"extract", "n:f:vh?", cbfs_extract}, }; @@ -470,7 +470,7 @@ static void usage(char *name) "Remove a component\n" " create -s size -B bootblock -m ARCH [-a align] [-o offset] " "Create a ROM file\n" - " locate -f FILE -n NAME [-P page-size] [-T] " + " locate -f FILE -n NAME [-P page-size] [-a align] [-T] " "Find a place for a file of that size\n" " print " "Show the contents of the ROM\n"

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Patch set updated for coreboot: c7c825b cbfstool locate: Rename -a align switch to -P for page size
by Hung-Te Lin 19 Mar '13

19 Mar '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2730 -gerrit commit c7c825b2d6e1f50aacb7214b0fe1343fa5c83364 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Mar 19 12:17:12 2013 +0800 cbfstool locate: Rename -a align switch to -P for page size cbfstool usage change: The "-a" parameter for "cbfstool locate" is switched to "-P/--page-size". The "locate" command was used to find a place to store ELF stage image in one memory page. Its argument "-a (alignment)" was actually specifying the page size instead of doing memory address alignment. This can be confusing when people are trying to put a blob in aligned location (ex, microcode needs to be aligned in 0x10), and see this: cbfstool coreboot.rom locate -f test.bin -n test -a 0x40000 # output: 0x44, which does not look like aligned to 0x40000. To prevent confusion, it's now switched to "-P/--page-size". Verified by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731 --- src/arch/armv7/Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 2 +- util/cbfstool/cbfstool.c | 15 ++++++++++----- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 39c115e..8601112 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -282,7 +282,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin @printf " generating base_xip.txt\n" rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cc7bfc2..433b434 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -393,7 +393,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 97fd88d..e918d89 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -50,6 +50,7 @@ static struct param { uint32_t entrypoint; uint32_t size; uint32_t alignment; + uint32_t pagesize; uint32_t offset; uint32_t top_aligned; comp_algo algo; @@ -355,12 +356,12 @@ static int cbfs_locate(void) } address = cbfs_locate_entry(&image, param.name, buffer.size, - param.alignment); + param.pagesize); buffer_delete(&buffer); if (address == -1) { - ERROR("'%s' can't fit in CBFS for align 0x%x.\n", - param.name, param.alignment); + ERROR("'%s' can't fit in CBFS for page-size %#x.\n", + param.name, param.pagesize); cbfs_image_delete(&image); return 1; } @@ -421,7 +422,7 @@ static const struct command commands[] = { {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"remove", "n:vh?", cbfs_remove}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, - {"locate", "f:n:a:Tvh?", cbfs_locate}, + {"locate", "f:n:P:Tvh?", cbfs_locate}, {"print", "vh?", cbfs_print}, {"extract", "n:f:vh?", cbfs_extract}, }; @@ -437,6 +438,7 @@ static struct option long_options[] = { {"size", required_argument, 0, 's' }, {"bootblock", required_argument, 0, 'B' }, {"alignment", required_argument, 0, 'a' }, + {"page-size", required_argument, 0, 'P' }, {"offset", required_argument, 0, 'o' }, {"file", required_argument, 0, 'f' }, {"arch", required_argument, 0, 'm' }, @@ -468,7 +470,7 @@ static void usage(char *name) "Remove a component\n" " create -s size -B bootblock -m ARCH [-a align] [-o offset] " "Create a ROM file\n" - " locate -f FILE -n NAME [-a align] [-T] " + " locate -f FILE -n NAME [-P page-size] [-T] " "Find a place for a file of that size\n" " print " "Show the contents of the ROM\n" @@ -572,6 +574,9 @@ int main(int argc, char **argv) case 'a': param.alignment = strtoul(optarg, NULL, 0); break; + case 'P': + param.pagesize = strtoul(optarg, NULL, 0); + break; case 'o': param.offset = strtoul(optarg, NULL, 0); break;

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New patch to review for coreboot: ed1cc91 cbfstool locate: Implement alignment switch --align/-a
by Hung-Te Lin 19 Mar '13

19 Mar '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2824 -gerrit commit ed1cc917a69a8b46dc9a895ac17bacf2f3802655 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Mar 19 12:24:43 2013 +0800 cbfstool locate: Implement alignment switch --align/-a cbfstool usage change: "-a" for "cbfstool locate" can specify base address alignment. To support putting a blob in aligned location (ex, microcode needs to be aligned in 0x10), alignment (-a) is implemented into "locate" command. Verified by manually testing a file (324 bytes) with alignment=0x10: cbfstool coreboot.rom locate -f test -n test -a 0x10 # output: 0x71fdd0 cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0 cbfstool coreboot.rom print -v -v # output: test 0x71fd80 raw 324 # output: cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144 Also verified to be compatible with old behavior by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30 # output: 0x60 Change-Id: I78b549fe6097ce5cb6162b09f064853827069637 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- util/cbfstool/cbfs_image.c | 71 ++++++++++++++++++++++++++++++++-------------- util/cbfstool/cbfs_image.h | 6 ++-- util/cbfstool/cbfstool.c | 10 +++---- 3 files changed, 58 insertions(+), 29 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2cdbf23..63d6f78 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -773,7 +773,7 @@ int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, return 0; } -/* Finds a place to hold whole stage data in same memory page. +/* Finds a place to hold whole data in same memory page. */ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { if (!page) @@ -781,24 +781,44 @@ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { return (start / page) == (start + size - 1) / page; } +/* Tests if data can fit in a range by given offset: + * start ->| header_len | offset (+ size) |<- end + */ +static int is_in_range(uint32_t start, uint32_t end, uint32_t header_len, + uint32_t offset, uint32_t size) { + return (offset >= start + header_len && offset + size <= end); +} + int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size) { + uint32_t size, uint32_t page_size, uint32_t align) { struct cbfs_file *entry; size_t need_len; - uint32_t addr, addr_next, addr2, addr3, header_len; - assert(size < page_size); + uint32_t addr, addr_next, addr2, addr3, offset, header_len; + + /* Default values: allow fitting anywhere in ROM. */ + if (!page_size) + page_size = ntohl(image->header->romsize); + if (!align) + align = 1; + + if (size > page_size) + ERROR("Input file size (%d) greater than page size (%d).\n", + size, page_size); if (page_size % ntohl(image->header->align)) - WARN("locate_entry: page does not align with CBFS image.\n"); + WARN("%s: Page size (%#x) not aligned with CBFS image (%#x).\n", + __func__, page_size, ntohl(image->header->align)); /* TODO Old cbfstool always assume input is a stage file (and adding * sizeof(cbfs_stage) for header. We should fix that by adding "-t" - * (type) param in future. For right now, follow old behavior. */ + * (type) param in future. For right now, we assume cbfs_stage is the + * largest structure and add it into header size. */ + assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload)); header_len = (cbfs_calculate_file_header_size(name) + sizeof(struct cbfs_stage)); need_len = header_len + size; - // Merge empty entries to build get max available pages. + // Merge empty entries to build get max available space. cbfs_walk(image, cbfs_merge_empty_entry, NULL); /* Three cases of content location on memory page: @@ -812,14 +832,15 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, * shift-> | <header>|<content> | at starting of PAGE 2. * * case 3. (large content filling whole page) - * | PAGE 1 | PAGE 2 | PAGE 3| - * | <header>< content > | | Can't fit. If we shift content to - * | { free space . } PAGE 2, header can't fit in free - * | shift-> <header><content> space, so we must use PAGE 3. + * | PAGE 1 | PAGE 2 | PAGE 3 | + * | <header>< content > | Can't fit. If we shift content to + * |trial-> <header>< content > | PAGE 2, header can't fit in free + * | shift-> <header><content> space, so we must use PAGE 3. * - * The returned address will be used to re-link stage file, and then - * assigned to add-stage command (-b), which will be then re-calculated - * by ELF loader and positioned by cbfs_add_entry. + * The returned address can be then used as "base-address" (-b) in add-* + * commands (will be re-calculated and positioned by cbfs_add_entry_at). + * For stage targets, the address is also used to re-link stage before + * being added into CBFS. */ for (entry = cbfs_find_first_entry(image); entry && cbfs_is_valid_entry(image, entry); @@ -834,23 +855,29 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, image, entry)); if (addr_next - addr < need_len) continue; - if (is_in_same_page(addr + header_len, size, page_size)) { + + offset = align_up(addr + header_len, align); + if (is_in_same_page(offset, size, page_size) && + is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1)."); - return addr + header_len; + return offset; } addr2 = align_up(addr, page_size); - if (addr2 < addr_next && addr_next - addr2 >= size && - addr2 - addr >= header_len) { + offset = align_up(addr2, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); - return addr2; + return offset; } + /* Assume page_size >= header_len so adding one page will + * definitely provide the space for header. */ + assert(page_size >= header_len); addr3 = addr2 + page_size; - if (addr3 < addr_next && addr_next - addr3 >= size && - addr3 - addr >= header_len) { + offset = align_up(addr3, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); - return addr3; + return offset; } } return -1; diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 57bbfa1..7ad418a 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -76,10 +76,12 @@ int cbfs_remove_entry(struct cbfs_image *image, const char *name); int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, size_t len, const char *name); -/* Finds a location to put given content in same memory page. +/* Finds a location to put given content by specified criteria: + * "page_size" limits the content to fit on same memory page, and + * "align" specifies starting address alignment. * Returns a valid offset, or -1 on failure. */ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size); + uint32_t size, uint32_t page_size, uint32_t align); /* Callback function used by cbfs_walk. * Returns 0 on success, or non-zero to stop further iteration. */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index e918d89..eeb6936 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -356,12 +356,12 @@ static int cbfs_locate(void) } address = cbfs_locate_entry(&image, param.name, buffer.size, - param.pagesize); + param.pagesize, param.alignment); buffer_delete(&buffer); if (address == -1) { - ERROR("'%s' can't fit in CBFS for page-size %#x.\n", - param.name, param.pagesize); + ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, param.pagesize, param.alignment); cbfs_image_delete(&image); return 1; } @@ -422,7 +422,7 @@ static const struct command commands[] = { {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"remove", "n:vh?", cbfs_remove}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, - {"locate", "f:n:P:Tvh?", cbfs_locate}, + {"locate", "f:n:P:a:Tvh?", cbfs_locate}, {"print", "vh?", cbfs_print}, {"extract", "n:f:vh?", cbfs_extract}, }; @@ -470,7 +470,7 @@ static void usage(char *name) "Remove a component\n" " create -s size -B bootblock -m ARCH [-a align] [-o offset] " "Create a ROM file\n" - " locate -f FILE -n NAME [-P page-size] [-T] " + " locate -f FILE -n NAME [-P page-size] [-a align] [-T] " "Find a place for a file of that size\n" " print " "Show the contents of the ROM\n"

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coreboot March 2013