coreboot March 2013

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New patch to review for coreboot: 3e014d1 lynxpoint: Fix up handling for LynxPoint-LP chipsets
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2819 -gerrit commit 3e014d1dad9a67c6b1c9c940a977abcbddc771b6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 8 17:22:37 2013 -0800 lynxpoint: Fix up handling for LynxPoint-LP chipsets This configures power management registers according to the 1.2.0 reference code drop. There are many inconsistencies with the documentation and I tried to note those with ?. This does not do the same for LynxPoint-H yet. Change-Id: I9b8f5c24a8b0931075a44398571c9b0d54cce6a6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 198 +++++++++++++++++++++------------- 1 file changed, 121 insertions(+), 77 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a943ca7..6b01489 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -307,49 +307,96 @@ static void pch_rtc_init(struct device *dev) rtc_init(rtc_failed); } -/* CougarPoint PCH Power Management init */ -#if 0 -static void cpt_pm_init(struct device *dev) +/* LynxPoint PCH Power Management init */ +static void lpt_pm_init(struct device *dev) { - printk(BIOS_DEBUG, "CougarPoint PM init\n"); - pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0)); - RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); - RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); - RCBA32(0x2304) = 0xc0388400; - RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); - RCBA32_AND_OR(0x3314, ~0x1f, 0xf); - RCBA32(0x3318) = 0x050f0000; - RCBA32(0x3324) = 0x04000000; - RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); - RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)); - RCBA32(0x3360) = 0x0001c000; - RCBA32(0x3368) = 0x00061100; - RCBA32(0x3378) = 0x7f8fdfff; - RCBA32(0x337c) = 0x000003fc; - RCBA32(0x3388) = 0x00001000; - RCBA32(0x3390) = 0x0001c000; - RCBA32(0x33a0) = 0x00000800; - RCBA32(0x33b0) = 0x00001000; - RCBA32(0x33c0) = 0x00093900; - RCBA32(0x33cc) = 0x24653002; - RCBA32(0x33d0) = 0x062108fe; - RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); - RCBA32(0x3a28) = 0x01010000; - RCBA32(0x3a2c) = 0x01010404; - RCBA32(0x3a80) = 0x01041041; - RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); - RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ - RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ - RCBA32(0x3a6c) = 0x00000001; - RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); - RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); - RCBA32(0x33c8) = 0; - RCBA32_AND_OR(0x21b0, ~0UL, 0xf); + printk(BIOS_DEBUG, "LynxPoint PM init\n"); +} + +const struct rcba_config_instruction lpt_lp_pm_rcba[] = { + RCBA_RMW_REG_32(0x232c, ~1, 0x00000000), /* 4 */ + RCBA_RMW_REG_32(0x1100, ~0, 0x0000c000), /* 5 */ + RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), /* 6 */ + RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), /* 7 */ + RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), /* 8? */ + RCBA_RMW_REG_32(0x3314, 0, 0x00012fff), /* 9? */ + RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400), /* 10? */ + RCBA_RMW_REG_32(0x3324, 0, 0x04000000), /* 11 */ + RCBA_RMW_REG_32(0x3368, 0, 0x00041400), /* 12? */ + RCBA_RMW_REG_32(0x3388, 0, 0x3f8ddbff), /* 13? */ + RCBA_RMW_REG_32(0x33ac, 0, 0x00007001), /* 14? */ + RCBA_RMW_REG_32(0x33b0, 0, 0x00181900), /* 15? */ + RCBA_RMW_REG_32(0x33c0, 0, 0x00060A00), /* 16? */ + RCBA_RMW_REG_32(0x33d0, 0, 0x06200840), /* 17? */ + RCBA_RMW_REG_32(0x3a28, 0, 0x01010101), /* 19 */ + RCBA_RMW_REG_32(0x3a2c, 0, 0x04040404), /* 20 */ + RCBA_RMW_REG_32(0x2b1c, 0, 0x03808033), /* 23? */ + RCBA_RMW_REG_32(0x2b34, 0, 0x80000008), /* 24 */ + RCBA_RMW_REG_32(0x3348, 0, 0x022ddfff), /* 25? */ + RCBA_RMW_REG_32(0x334c, 0, 0x00000001), /* 26 */ + RCBA_RMW_REG_32(0x3358, 0, 0x0001c000), /* 27 */ + RCBA_RMW_REG_32(0x3380, 0, 0x3f8ddbff), /* 28 */ + RCBA_RMW_REG_32(0x3384, 0, 0x0001c7e1), /* 29 */ + RCBA_RMW_REG_32(0x338c, 0, 0x0001c7e1), /* ? */ + RCBA_RMW_REG_32(0x3398, 0, 0x0001c000), /* 30 */ + RCBA_RMW_REG_32(0x33a8, 0, 0x00181900), /* 31? */ + RCBA_RMW_REG_32(0x33dc, 0, 0x00080000), /* 32 */ + RCBA_RMW_REG_32(0x33e0, 0, 0x00000001), /* 33 */ + RCBA_RMW_REG_32(0x3a20, 0, 0x00000404), /* 34 */ + RCBA_RMW_REG_32(0x3a24, 0, 0x01010101), /* 35 */ + RCBA_RMW_REG_32(0x3a30, 0, 0x01010101), /* 36 */ + RCBA_RMW_REG_32(0x0410, ~0, 0x00000003), /* 42 */ + RCBA_RMW_REG_32(0x2618, ~0, 0x08000000), /* 43 */ + RCBA_RMW_REG_32(0x2600, ~0, 0x00000008), /* 44 */ + RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), /* 46? */ + RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), /* 47? */ + RCBA_RMW_REG_32(0x3354, 0, 0x00000001), /* ? */ + RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ + RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */ + RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ + RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4610), /* Power Optimizer */ + RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ + RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ + RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), /* 21? */ + RCBA_END_CONFIG +}; + +/* LynxPoint LP PCH Power Management init */ +static void lpt_lp_pm_init(struct device *dev) +{ + struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + u32 data; + + printk(BIOS_DEBUG, "LynxPoint LP PM init\n"); + + pci_write_config8(dev, 0xa9, 0x46); + + pch_config_rcba(lpt_lp_pm_rcba); + + pci_write_config32(dev, 0xac, + pci_read_config32(dev, 0xac) | (1 << 21)); + + pch_iobp_update(0xCA000000, ~0UL, 0x00000009); + + /* Set RCBA CIR28 0x3A84 based on SATA port enables */ + data = 0x00001005; + /* Port 3 and 2 disabled */ + if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) + data |= (1 << 24) | (1 << 26); + /* Port 1 and 0 disabled */ + if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) + data |= (1 << 20) | (1 << 18); + RCBA32(0x3a84) = data; + + /* Lock */ + RCBA32_OR(0x3a6c, 0x00000001); + + /* Set RCBA 0x33D4 after other setup */ + RCBA32_OR(0x33d4, 0x2fff2fb1); + + /* Set RCBA 0x33C8[15]=1 as last step */ + RCBA32_OR(0x33c8, (1 << 15)); } -#endif static void enable_hpet(void) { @@ -366,7 +413,31 @@ static void enable_hpet(void) static void enable_clock_gating(device_t dev) { -#if CONFIG_INTEL_LYNXPOINT_LP + /* LynxPoint Mobile */ + u32 reg32; + u16 reg16; + + /* DMI */ + RCBA32_AND_OR(0x2234, ~0UL, 0xf); + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 |= (1 << 11) | (1 << 12) | (1 << 14); + reg16 |= (1 << 2); // PCI CLKRUN# Enable + pci_write_config16(dev, GEN_PMCON_1, reg16); + RCBA32_OR(0x900, (1 << 14)); + + reg32 = RCBA32(CG); + reg32 |= (1 << 22); // HDA Dynamic + reg32 |= (1 << 31); // LPC Dynamic + reg32 |= (1 << 16); // PCIe Dynamic + reg32 |= (1 << 27); // HPET Dynamic + reg32 |= (1 << 28); // GPIO Dynamic + RCBA32(CG) = reg32; + + RCBA32_OR(0x38c0, 0x7); // SPI Dynamic +} + +static void enable_lp_clock_gating(device_t dev) +{ /* LynxPoint LP */ u32 reg32; u16 reg16; @@ -383,7 +454,7 @@ static void enable_clock_gating(device_t dev) reg32 |= (1 << 6); pci_write_config32(dev, 0x64, reg32); - RCBA32_AND_OR(0x2614, 0x8fffffff, 0x0f006500); + RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); RCBA32_OR(0x900, 0x0000031f); reg32 = RCBA32(CG); @@ -398,35 +469,12 @@ static void enable_clock_gating(device_t dev) RCBA32_OR(0x3434, 0x7); // LP LPC - RCBA32_AND_OR(0x333c, 0xff0fffff, 0x00800000); // SATA + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic pch_iobp_update(0xCF000000, ~0UL, 0x00007001); pch_iobp_update(0xCE00C000, ~0UL, 0x00000001); -#else - /* LynxPoint Mobile */ - u32 reg32; - u16 reg16; - - /* DMI */ - RCBA32_AND_OR(0x2234, ~0UL, 0xf); - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 |= (1 << 11) | (1 << 12) | (1 << 14); - reg16 |= (1 << 2); // PCI CLKRUN# Enable - pci_write_config16(dev, GEN_PMCON_1, reg16); - RCBA32_OR(0x900, (1 << 14)); - - reg32 = RCBA32(CG); - reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1 << 31); // LPC Dynamic - reg32 |= (1 << 16); // PCIe Dynamic - reg32 |= (1 << 27); // HPET Dynamic - reg32 |= (1 << 28); // GPIO Dynamic - RCBA32(CG) = reg32; - - RCBA32_OR(0x38c0, 0x7); // SPI Dynamic -#endif } static void pch_set_acpi_mode(void) @@ -504,14 +552,14 @@ static void lpc_init(struct device *dev) pch_power_options(dev); /* Initialize power management */ - switch (pch_silicon_type()) { - default: - printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); + if (pch_is_lp()) { + lpt_lp_pm_init(dev); + enable_lp_clock_gating(dev); + } else { + lpt_pm_init(dev); + enable_clock_gating(dev); } - /* Set the state of the GPIO lines. */ - //gpio_init(dev); - /* Initialize the real time clock. */ pch_rtc_init(dev); @@ -521,12 +569,8 @@ static void lpc_init(struct device *dev) /* Initialize the High Precision Event Timers, if present. */ enable_hpet(); - /* Initialize Clock Gating */ - enable_clock_gating(dev); - setup_i8259(); - /* The OS should do this? */ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1);

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New patch to review for coreboot: fd62953 lynxpoint: Change sata.c to get rid of #if
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2818 -gerrit commit fd62953d05b09fa14cdf35e82f3def27ba2ebb88 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 8 17:17:33 2013 -0800 lynxpoint: Change sata.c to get rid of #if This uses the new helper function added earlier. Change-Id: Icdb5d5c51f70eeb7e39e11062276ceb3eb3d9473 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/sata.c | 41 ++++++++++++++++------------------ 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 25eb94f..8912865 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -137,11 +137,11 @@ static void sata_init(struct device *dev) reg32 |= 1 << 5; /* BWG step 9 */ reg32 |= 1 << 18; /* BWG step 10 */ reg32 |= 1 << 29; /* BWG step 11 */ -#if CONFIG_INTEL_LYNXPOINT_LP - reg32 &= ~((1 << 31) | (1 << 30)); - reg32 |= 1 << 23; - reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ -#endif + if (pch_is_lp()) { + reg32 &= ~((1 << 31) | (1 << 30)); + reg32 |= 1 << 23; + reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ + } pci_write_config32(dev, 0x98, reg32); /* Setup register 9Ch */ @@ -162,9 +162,8 @@ static void sata_init(struct device *dev) reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS -#if CONFIG_INTEL_LYNXPOINT_LP - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY -#endif + if (pch_is_lp()) + reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); @@ -172,12 +171,11 @@ static void sata_init(struct device *dev) (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); -#if CONFIG_INTEL_LYNXPOINT_LP /* Enable DEVSLP */ - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); -#else - reg32 &= ~0x00000002; -#endif + if (pch_is_lp()) + reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + else + reg32 &= ~0x00000002; write32(abar + 0x24, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); @@ -239,11 +237,10 @@ static void sata_init(struct device *dev) /* Power Optimizer */ /* Step 1 */ -#if CONFIG_INTEL_LYNXPOINT_LP - sir_write(dev, 0x64, 0x883c9003); -#else - sir_write(dev, 0x64, 0x883c9001); -#endif + if (pch_is_lp()) + sir_write(dev, 0x64, 0x883c9003); + else + sir_write(dev, 0x64, 0x883c9001); /* Step 2: SIR 68h[15:0] = 880Ah */ reg32 = sir_read(dev, 0x68); @@ -268,10 +265,10 @@ static void sata_init(struct device *dev) /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); -#if CONFIG_INTEL_LYNXPOINT_LP - sir_write(dev, 0x54, 0xcf000f0f); - sir_write(dev, 0x58, 0x00190000); -#endif + if (pch_is_lp()) { + sir_write(dev, 0x54, 0xcf000f0f); + sir_write(dev, 0x58, 0x00190000); + } reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16);

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New patch to review for coreboot: 210d4c7 lynxpoint: Fix ELOG logging of power management events
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2817 -gerrit commit 210d4c7d5d67cb040bb3adfd7f47f96468659464 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 8 17:16:37 2013 -0800 lynxpoint: Fix ELOG logging of power management events This is updated to handle LynxPoint-H and LynxPoint-LP and a new wake event is added for the power button. Boot, suspend/resume, reboot, etc on WTM2 and then check the event log to see if expected events have been added. Change-Id: I15cbc3901d81f4fd77cc04de37ff5fa048f9d3e8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/elog.h | 1 + src/southbridge/intel/lynxpoint/elog.c | 119 ++++++++++++++++++++++++++------- 2 files changed, 97 insertions(+), 23 deletions(-) diff --git a/src/include/elog.h b/src/include/elog.h index a5b5a77..a65893c 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -113,6 +113,7 @@ #define ELOG_WAKE_SOURCE_RTC 0x03 #define ELOG_WAKE_SOURCE_GPIO 0x04 #define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 struct elog_event_data_wake { u8 source; u32 instance; diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 09dfcdb..9ba3a98 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -28,20 +28,101 @@ #include <elog.h> #include "pch.h" +static void pch_log_standard_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg) +{ + u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); + u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en; + + /* PME (TODO: determine wake device) */ + if (gpe0_sts & (1 << 11)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME (TODO: determine wake device) */ + if (gpe0_sts & (1 << 13)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + /* SMBUS Wake */ + if (gpe0_sts & (1 << 7)) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); +} + +static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start) +{ + /* GPE Bank 1 is GPIO 0-31 */ + u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); + u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en; + int i; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_gpe(void) +{ + int i; + u16 pmbase = get_pmbase(); + u32 gpe0_sts, gpe0_en; + int gpe0_high_gpios[] = { + [0] = 27, + [24] = 17, + [25] = 19, + [26] = 21, + [27] = 22, + [28] = 43, + [29] = 56, + [30] = 57, + [31] = 60 + }; + + pch_log_standard_gpe(GPE0_EN, GPE0_STS); + + /* GPIO 0-15 */ + gpe0_en = inw(pmbase + GPE0_EN + 2); + gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en; + for (i = 0; i <= 15; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + } + + /* + * Now check and log upper status bits + */ + + gpe0_en = inl(pmbase + GPE0_EN_2); + gpe0_sts = inl(pmbase + GPE0_STS_2) & gpe0_en; + + for (i = 0; i <= 31; i++) { + if (!gpe0_high_gpios[i]) + continue; + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, + gpe0_high_gpios[i]); + } +} + +static void pch_lp_log_gpe(void) +{ + /* Standard GPE are in GPE set 4 */ + pch_log_standard_gpe(LP_GPE0_STS_4, LP_GPE0_EN_4); + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(LP_GPE0_STS_1, LP_GPE0_EN_1, 0); + pch_log_gpio_gpe(LP_GPE0_STS_2, LP_GPE0_EN_2, 32); + pch_log_gpio_gpe(LP_GPE0_STS_3, LP_GPE0_EN_3, 64); +} + void pch_log_state(void) { u16 pm1_sts, gen_pmcon_3, tco2_sts; - u32 gpe0_sts, gpe0_en; u8 gen_pmcon_2; - int i; struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!lpc) return; - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); - gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); - tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); + pm1_sts = inw(get_pmbase() + PM1_STS); + tco2_sts = inw(get_pmbase() + TCO2_STS); gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); @@ -86,6 +167,10 @@ void pch_log_state(void) * Wake sources */ + /* Power Button */ + if (pm1_sts & (1 << 8)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + /* RTC */ if (pm1_sts & (1 << 10)) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); @@ -94,21 +179,9 @@ void pch_log_state(void) if (pm1_sts & (1 << 14)) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - /* PME (TODO: determine wake device) */ - if (gpe0_sts & (1 << 13)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - - /* Internal PME (TODO: determine wake device) */ - if (gpe0_sts & (1 << 13)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - - /* GPIO 0-15 */ - for (i = 0; i < 16; i++) { - if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i)))) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); - } - - /* SMBUS Wake */ - if (gpe0_sts & (1 << 7)) - elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + /* GPE */ + if (pch_is_lp()) + pch_lp_log_gpe(); + else + pch_log_gpe(); }

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New patch to review for coreboot: 07a8a42 haswell/lynxpoint: Use new PCH/PM helper functions
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2816 -gerrit commit 07a8a422ceeb1d5109f46f55a589e7334ec930e3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 8 17:00:37 2013 -0800 haswell/lynxpoint: Use new PCH/PM helper functions This makes use of the new functions from pmutil.c that take care of the differences between -H and -LP chipsets. It also adds support for the LynxPoint-LP GPE0 register block and the SMI/SCI routing differences. The FADT is updated to report the new 256 byte GPE0 block on wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address block so that part is zeroed to prevent IASL and the kernel from complaining about a mismatch. This was tested on WTM2. Unfortunately I am still unable to get an SCI delivered from the EC but I suspect that is due to a magic command needed to put the EC in ACPI mode. Instead I verified that all of the power management and GPIO registers were set to expected values. I also tested transitions into S3 and S5 from both the kernel and by pressing the power button at the developer mode screen and they all function as expected. Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/baskingridge/devicetree.cb | 2 +- src/mainboard/intel/wtm1/devicetree.cb | 9 +- src/mainboard/intel/wtm1/fadt.c | 14 +- src/mainboard/intel/wtm2/devicetree.cb | 9 +- src/mainboard/intel/wtm2/fadt.c | 14 +- src/northbridge/intel/haswell/acpi.c | 13 +- src/southbridge/intel/lynxpoint/chip.h | 9 +- src/southbridge/intel/lynxpoint/lpc.c | 21 +- src/southbridge/intel/lynxpoint/smi.c | 250 ++-------------------- src/southbridge/intel/lynxpoint/smihandler.c | 279 +++++-------------------- 10 files changed, 111 insertions(+), 509 deletions(-) diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index c74767a..fa3f3e7 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -48,7 +48,7 @@ chip northbridge/intel/haswell register "gpi1_routing" = "1" register "gpi14_routing" = "2" register "alt_gp_smi_en" = "0x0000" - register "gpe0_en" = "0x4000" + register "gpe0_en_1" = "0x4000" register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" diff --git a/src/mainboard/intel/wtm1/devicetree.cb b/src/mainboard/intel/wtm1/devicetree.cb index db7c998..be4fe51 100644 --- a/src/mainboard/intel/wtm1/devicetree.cb +++ b/src/mainboard/intel/wtm1/devicetree.cb @@ -41,12 +41,11 @@ chip northbridge/intel/haswell register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" - register "gpe0_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" diff --git a/src/mainboard/intel/wtm1/fadt.c b/src/mainboard/intel/wtm1/fadt.c index 510b765..7afbbfa 100644 --- a/src/mainboard/intel/wtm1/fadt.c +++ b/src/mainboard/intel/wtm1/fadt.c @@ -21,12 +21,12 @@ #include <device/pci.h> #include <arch/acpi.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/pch.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; + u16 pmbase = get_pmbase(); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); @@ -55,14 +55,14 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + 0x50; fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe0_blk = pmbase + 0x80; fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; + fadt->gpe0_blk_len = 32; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; fadt->cst_cnt = 0; @@ -137,11 +137,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrl = 0; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index db7c998..80c8627 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -41,12 +41,11 @@ chip northbridge/intel/haswell register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" - register "gpe0_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 510b765..7afbbfa 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -21,12 +21,12 @@ #include <device/pci.h> #include <arch/acpi.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/pch.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; + u16 pmbase = get_pmbase(); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); @@ -55,14 +55,14 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + 0x50; fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe0_blk = pmbase + 0x80; fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; + fadt->gpe0_blk_len = 32; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; fadt->cst_cnt = 0; @@ -137,11 +137,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrl = 0; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index e4d86be..81da086 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -182,17 +182,12 @@ int init_igd_opregion(igd_opregion_t *opregion) pci_write_config16(igd, SWSCI, reg16); /* clear dmisci status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); + reg16 = inw(get_pmbase() + TCO1_STS); reg16 |= DMISCI_STS; // reference code does an &= - outw(DEFAULT_PMBASE + TCO1_STS, reg16); + outw(get_pmbase() + TCO1_STS, reg16); - /* clear acpi tco status */ - outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); - - /* enable acpi tco scis */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(DEFAULT_PMBASE + GPE0_EN, reg16); + /* clear and enable ACPI TCO SCI */ + enable_tco_sci(); return 0; } diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index ffeb977..95bd087 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -35,7 +35,7 @@ struct southbridge_intel_lynxpoint_config { uint8_t pirqh_routing; /** - * GPI Routing configuration + * GPI Routing configuration for LynxPoint-H * * Only the lower two bits have a meaning: * 00: No effect @@ -60,8 +60,11 @@ struct southbridge_intel_lynxpoint_config { uint8_t gpi14_routing; uint8_t gpi15_routing; - uint32_t gpe0_en; - uint16_t alt_gp_smi_en; + uint32_t gpe0_en_1; + uint32_t gpe0_en_2; + uint32_t gpe0_en_3; + uint32_t gpe0_en_4; + uint32_t alt_gp_smi_en; /* IDE configuration */ uint32_t ide_legacy_combined; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 89d7350..a943ca7 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -184,12 +185,12 @@ static void pch_gpi_routing(device_t dev) static void pch_power_options(device_t dev) { u8 reg8; - u16 reg16, pmbase; + u16 reg16; u32 reg32; const char *state; /* Get the chip configuration */ config_t *config = dev->chip_info; - + u16 pmbase = get_pmbase(); int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; int nmi_option; @@ -257,13 +258,19 @@ static void pch_power_options(device_t dev) reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME pci_write_config16(dev, GEN_PMCON_1, reg16); - // Set the board's GPI routing. - pch_gpi_routing(dev); + /* + * Set the board's GPI routing on LynxPoint-H. + * This is done as part of GPIO configuration on LynxPoint-LP. + */ + if (pch_is_lp()) + pch_gpi_routing(dev); - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + /* GPE setup based on device tree configuration */ + enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, + config->gpe0_en_3, config->gpe0_en_4); - outl(config->gpe0_en, pmbase + GPE0_EN); - outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + /* SMI setup based on device tree configuration */ + enable_alt_smi(config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index a3354b8..176d400 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -30,240 +30,34 @@ #include <string.h> #include "pch.h" -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_DEBUG, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i<= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear ALT_GP_SMI_STS - * @return ALT_GP_SMI_STS register - */ -static u16 reset_alt_gp_smi_status(void) -{ - u16 reg16; - - reg16 = inl(pmbase + ALT_GP_SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg16, pmbase + ALT_GP_SMI_STS); - - return reg16; -} - -static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) -{ - int i; - printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); - for (i=15; i<= 0; i--) { - if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16)); - } - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief Set the EOS bit - */ -static void smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - void southbridge_smm_init(void) { u32 smi_en; - u16 pm1_en; - u32 gpe0_en; #if CONFIG_ELOG /* Log events from chipset before clearing */ pch_log_state(); #endif printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase()); - pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PMBASE) & 0xff80; - - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - smi_en = inl(pmbase + SMI_EN); + smi_en = inl(get_pmbase() + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } printk(BIOS_DEBUG, "\n"); - dump_smi_status(reset_smi_status()); - dump_pm1_status(reset_pm1_status()); - dump_gpe0_status(reset_gpe0_status()); - dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); - /* Disable GPE0 PME_B0 */ - gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en &= ~PME_B0_EN; - outl(gpe0_en, pmbase + GPE0_EN); + /* Dump and clear status registers */ + clear_smi_status(); + clear_pm1_status(); + clear_tco_status(); + clear_gpe_status(); - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); + /* Configure events */ + enable_pm1(PWRBTN_EN | GBL_EN); + disable_gpe(PME_B0_EN); /* Enable SMI generation: * - on TCO events @@ -273,23 +67,7 @@ void southbridge_smm_init(void) * No SMIs: * - on microcontroller writes (io 0x62/0x66) */ - - smi_en = 0; /* reset SMI enables */ - -#if 0 - smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; -#endif - smi_en |= TCO_EN; - smi_en |= APMC_EN; - smi_en |= SLP_SMI_EN; -#if 0 - smi_en |= BIOS_EN; -#endif - - /* The following need to be on for SMIs to happen */ - smi_en |= EOS | GBL_SMI_EN; - - outl(smi_en, pmbase + SMI_EN); + enable_smi(TCO_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void southbridge_trigger_smi(void) @@ -315,13 +93,13 @@ void southbridge_trigger_smi(void) void southbridge_clear_smi_status(void) { /* Clear SMI status */ - reset_smi_status(); + clear_smi_status(); /* Clear PM1 status */ - reset_pm1_status(); + clear_pm1_status(); /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); + enable_smi(EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 48dca2c..49f7df8 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -33,14 +34,6 @@ #include "nvs.h" -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; -u16 smm_get_pmbase(void) -{ - return pmbase; -} static u8 smm_initialized = 0; @@ -53,157 +46,6 @@ global_nvs_t *smm_get_gnvs(void) return gnvs; } -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_SPEW, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); - printk(BIOS_SPEW, "\n"); - int reg16 = inw(pmbase + PM1_EN); - printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i<= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); - if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -226,11 +68,7 @@ int southbridge_io_trap_handler(int smif) */ void southbridge_smi_set_eos(void) { - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); + enable_smi(EOS); } static void busmaster_disable_on_bus(int bus) @@ -274,6 +112,7 @@ static void southbridge_smi_sleep(void) u32 reg32; u8 slp_typ; u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u16 pmbase = get_pmbase(); // save and recover RTC port values u8 tmp70, tmp72; @@ -284,9 +123,7 @@ static void southbridge_smi_sleep(void) outb(tmp72, 0x72); /* First, disable further SMIs */ - reg8 = inb(pmbase + SMI_EN); - reg8 &= ~SLP_SMI_EN; - outb(reg8, pmbase + SMI_EN); + disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ reg32 = inl(pmbase + PM1_CNT); @@ -306,19 +143,26 @@ static void southbridge_smi_sleep(void) */ switch (slp_typ) { - case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; - case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; - case 5: + case SLP_TYP_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case SLP_TYP_S1: + printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); + break; + case SLP_TYP_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); /* Invalidate the cache before going to S3 */ wbinvd(); break; - case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; - case 7: + case SLP_TYP_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case SLP_TYP_S5: printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - outl(0, pmbase + GPE0_EN); + /* Disable all GPE */ + disable_all_gpe(); /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated @@ -334,14 +178,16 @@ static void southbridge_smi_sleep(void) /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); break; - default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; } /* Write back to the SLP register to cause the originally intended * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - outl(reg32 | SLP_EN, pmbase + PM1_CNT); + enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) @@ -354,8 +200,7 @@ static void southbridge_smi_sleep(void) reg32 = inl(pmbase + PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ - reg32 &= ~(SLP_EN | SLP_TYP); - outl(reg32, pmbase + PM1_CNT); + disable_pm1_control(SLP_EN | SLP_TYP); } } @@ -420,7 +265,6 @@ static void southbridge_smi_gsmi(void) static void southbridge_smi_apmc(void) { - u32 pmctrl; u8 reg8; em64t101_smm_state_save_area_t *state; @@ -443,20 +287,17 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl &= ~SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); + disable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl |= SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); + enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_GNVS_UPDATE: if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); + printk(BIOS_DEBUG, + "SMI#: SMM structures already initialized!\n"); return; } state = smi_apmc_find_state_save(reg8); @@ -479,53 +320,41 @@ static void southbridge_smi_apmc(void) static void southbridge_smi_pm1(void) { - u16 pm1_sts; - - pm1_sts = reset_pm1_status(); - dump_pm1_status(pm1_sts); + u16 pm1_sts = clear_pm1_status(); /* While OSPM is not active, poweroff immediately * on a power button event. */ if (pm1_sts & PWRBTN_STS) { // power button pressed - u32 reg32; - reg32 = (7 << 10) | (1 << 13); #if CONFIG_ELOG_GSMI elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif - outl(reg32, pmbase + PM1_CNT); + disable_pm1_control(-1UL); + enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); } } static void southbridge_smi_gpe0(void) { - u32 gpe0_sts; - - gpe0_sts = reset_gpe0_status(); - dump_gpe0_status(gpe0_sts); + clear_gpe_status(); } static void southbridge_smi_gpi(void) { - u16 reg16; - reg16 = inw(pmbase + ALT_GP_SMI_STS); - outw(reg16, pmbase + ALT_GP_SMI_STS); - - reg16 &= inw(pmbase + ALT_GP_SMI_EN); + mainboard_smi_gpi(clear_alt_smi_status()); - mainboard_smi_gpi(reg16); - - outw(reg16, pmbase + ALT_GP_SMI_STS); + /* Clear again after mainboard handler */ + clear_alt_smi_status(); } static void southbridge_smi_mc(void) { u32 reg32; - reg32 = inl(pmbase + SMI_EN); + reg32 = inl(get_pmbase() + SMI_EN); - /* Are periodic SMIs enabled? */ + /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) return; @@ -536,9 +365,7 @@ static void southbridge_smi_mc(void) static void southbridge_smi_tco(void) { - u32 tco_sts; - - tco_sts = reset_tco_status(); + u32 tco_sts = clear_tco_status(); /* Any TCO event? */ if (!tco_sts) @@ -561,13 +388,12 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, + (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); - } else if (!tco_sts) { - dump_tco_status(tco_sts); } } @@ -575,7 +401,7 @@ static void southbridge_smi_periodic(void) { u32 reg32; - reg32 = inl(pmbase + SMI_EN); + reg32 = inl(get_pmbase() + SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) @@ -624,11 +450,14 @@ static void southbridge_smi_monitor(void) // Fall through to debug } - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", + trap_cycle & 0xfffc); + for (i=0; i < 4; i++) + if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); + printk(BIOS_DEBUG, " read/write: %s\n", + (trap_cycle & (1 << 24)) ? "read" : "write"); if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ @@ -683,16 +512,13 @@ static smi_handler_t southbridge_smi[32] = { void southbridge_smi_handler(void) { - int i, dump = 0; + int i; u32 smi_sts; - /* Update global variable pmbase */ - pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ - smi_sts = reset_smi_status(); + smi_sts = clear_smi_status(); /* Call SMI sub handler for each of the status bits */ for (i = 0; i < 31; i++) { @@ -700,15 +526,10 @@ void southbridge_smi_handler(void) if (southbridge_smi[i]) { southbridge_smi[i](); } else { - printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " - "handler available.\n", i); - dump = 1; + printk(BIOS_DEBUG, + "SMI_STS[%d] occured, but no " + "handler available.\n", i); } } } - - if(dump) { - dump_smi_status(smi_sts); - } - }

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New patch to review for coreboot: bdd0fdb lynxpoint: Fix GPIO and PM base reservations
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2815 -gerrit commit bdd0fdbd77629b93bd939c55566692148d8ad363 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 8 16:34:33 2013 -0800 lynxpoint: Fix GPIO and PM base reservations The kernel ACPI was not happy with the Add inside a ResourceTemplate (or perhaps within the IO declaration) Instead make a buffer of IO reservations and turn _CRS into a method that updates the buffer depending on the chipset type. This adds an \ISLP() method that checks the chipset LPC device ID to see if it is -LP or -H. It also increases the PM base reservation to 256 bytes and moves both GPIO and PM base to above 0x1000 on -LP chipsets. Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 102 +++++++++++++++++++-------- src/southbridge/intel/lynxpoint/acpi/pch.asl | 12 +++- src/southbridge/intel/lynxpoint/lpc.c | 4 +- src/southbridge/intel/lynxpoint/pch.h | 5 +- 4 files changed, 90 insertions(+), 33 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 03d61eb..f9bf578 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -28,6 +28,8 @@ Device (LPCB) OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) { + Offset (0x3), + DIDH, 8, // Device ID High Byte Offset (0x40), PMBS, 16, // PMBASE Offset (0x60), // Interrupt Routing Registers @@ -181,36 +183,80 @@ Device (LPCB) { Name (_HID, EISAID("PNP0C02")) Name (_UID, 2) - Name (_CRS, ResourceTemplate() + + Name (RBUF, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI - -#if CONFIG_INTEL_LYNXPOINT_LP - // LynxPoint LP GPIO is 1KB - IO (Decode16, DEFAULT_GPIOBASE, - DEFAULT_GPIOBASE, 0x1, 0xff) - IO (Decode16, Add(DEFAULT_GPIOBASE, 0x100), - Add(DEFAULT_GPIOBASE, 0x100), 0x1, 0xff) - IO (Decode16, Add(DEFAULT_GPIOBASE, 0x200), - Add(DEFAULT_GPIOBASE, 0x200), 0x1, 0xff) - IO (Decode16, Add(DEFAULT_GPIOBASE, 0x300), - Add(DEFAULT_GPIOBASE, 0x300), 0x1, 0xff) -#else - // LynxPoint GPIO is 128 bytes - IO (Decode16, DEFAULT_GPIOBASE, - DEFAULT_GPIOBASE, 0x1, DEFAULT_GPIOSIZE) -#endif + IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO + IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, + 0x1, 0xff) + + // GPIO region may be 128 bytes or 4096 bytes + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, + 0x1, 0x00, GPR1) + IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR2) + IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR3) + IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR4) }) + + Method (_CRS, 0, NotSerialized) + { + CreateByteField (^RBUF, ^GPR1._LEN, R1LN) + CreateByteField (^RBUF, ^GPR2._LEN, R2LN) + CreateByteField (^RBUF, ^GPR3._LEN, R3LN) + CreateByteField (^RBUF, ^GPR4._LEN, R4LN) + + CreateWordField (^RBUF, ^GPR1._MIN, R1MN) + CreateWordField (^RBUF, ^GPR2._MIN, R2MN) + CreateWordField (^RBUF, ^GPR3._MIN, R3MN) + CreateWordField (^RBUF, ^GPR4._MIN, R4MN) + + CreateWordField (^RBUF, ^GPR1._MAX, R1MX) + CreateWordField (^RBUF, ^GPR2._MAX, R2MX) + CreateWordField (^RBUF, ^GPR3._MAX, R3MX) + CreateWordField (^RBUF, ^GPR4._MAX, R4MX) + + // Update GPIO region for LynxPoint-LP + If (\ISLP ()) { + // LynxPoint-LP + Store (R1MN, Local0) + + // Update GPIO bank 1 + Store (Local0, R1MN) + Store (Local0, R1MX) + Store (0xff, R1LN) + + // Update GPIO bank 2 + Add (Local0, 0x100, Local0) + Store (Local0, R2MN) + Store (Local0, R2MX) + Store (0xff, R2LN) + + // Update GPIO bank 3 + Add (Local0, 0x100, Local0) + Store (Local0, R3MN) + Store (Local0, R3MN) + Store (0xff, R3LN) + + // Update GPIO bank 4 + Add (Local0, 0x100, Local0) + Store (Local0, R4MN) + Store (Local0, R4MN) + Store (0xff, R4LN) + } Else { + // LynxPoint-H + // Update GPIO region length + Store (DEFAULT_GPIOSIZE, R1LN) + } + Return (RBUF) + } } Device (RTC) // Real Time Clock diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 8632ad8..ce8f0e0 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -23,6 +23,16 @@ Scope(\) { + // Return TRUE if chipset is LynxPoint-LP + Method (ISLP, 0, NotSerialized) + { + If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) { + Return (1) + } else { + Return (0) + } + } + // IO-Trap at 0x800. This is the ACPI->SMI communication interface. OperationRegion(IO_T, SystemIO, 0x800, 0x10) @@ -33,7 +43,7 @@ Scope(\) } // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) - OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) + OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0xff) Field(PMIO, ByteAcc, NoLock, Preserve) { Offset(0x20), // GPE0_STS diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 89cf9e7..89d7350 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -630,11 +630,11 @@ static void pch_lpc_add_io_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE, DEFAULT_GPIOSIZE, + pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE); /* PMBASE */ - pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 128, PMBASE); + pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); /* LPC Generic IO Decode range. */ pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index f2953d2..ee2efd5 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -65,12 +65,13 @@ */ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -#define DEFAULT_PMBASE 0x0500 #if CONFIG_INTEL_LYNXPOINT_LP -#define DEFAULT_GPIOBASE 0x1000 +#define DEFAULT_PMBASE 0x1000 +#define DEFAULT_GPIOBASE 0x1400 #define DEFAULT_GPIOSIZE 0x400 #else +#define DEFAULT_PMBASE 0x500 #define DEFAULT_GPIOBASE 0x480 #define DEFAULT_GPIOSIZE 0x80 #endif

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New patch to review for coreboot: b2f9334 lynxpoint: remove DEBUG_PERIODIC_SMIS
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2814 -gerrit commit b2f93343c4f77349e33033f54ea6ee6022ded9e9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 8 16:06:06 2013 -0800 lynxpoint: remove DEBUG_PERIODIC_SMIS This was put in for debugging and experimentation on i945 and has been copied around since. Drop it from lynxpoint. Change-Id: I0b53f4e1362cd3ce703625ef2b4988139c48b989 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 6 ------ src/southbridge/intel/lynxpoint/pch.h | 1 - src/southbridge/intel/lynxpoint/smi.c | 6 ------ 3 files changed, 13 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index eaf926c..89cf9e7 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -255,12 +255,6 @@ static void pch_power_options(device_t dev) reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); // SMI# rate 1 minute reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - reg16 |= (3 << 0); // Periodic SMI every 8s -#endif pci_write_config16(dev, GEN_PMCON_1, reg16); // Set the board's GPI routing. diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 0f20a83..f2953d2 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -79,7 +79,6 @@ #define DEFAULT_RCBA 0xfed1c000 #ifndef __ACPI__ -#define DEBUG_PERIODIC_SMIS 0 #if defined (__SMM__) && !defined(__ASSEMBLER__) void intel_pch_finalize_smm(void); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 80dea2c..a3354b8 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -281,12 +281,6 @@ void southbridge_smm_init(void) #endif smi_en |= TCO_EN; smi_en |= APMC_EN; -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - smi_en |= PERIODIC_EN; -#endif smi_en |= SLP_SMI_EN; #if 0 smi_en |= BIOS_EN;

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New patch to review for coreboot: 391b390 lynxpoint: Add power management helper functions
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2813 -gerrit commit 391b39079fb1830047f2da710c1e54a63095c25e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 8 16:01:44 2013 -0800 lynxpoint: Add power management helper functions There are subtle yet significant differences in some of the registers in the power management region between LynxPoint-H and LynxPoint-LP. In order to reduce code that is accessing these registers and would need special cases this adds a number of helper functions that can be used in both ramstage and SMM. This commit just adds the new functions, subsequent commits will start to use them. Change-Id: I411da75da519f5b3198a408078cbf3114e426992 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 3 +- src/southbridge/intel/lynxpoint/pch.h | 40 ++ src/southbridge/intel/lynxpoint/pmutil.c | 561 +++++++++++++++++++++++++++ 3 files changed, 603 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 3710135..04fa2f8 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -44,8 +44,9 @@ ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index db9bb77..0f20a83 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -132,6 +132,32 @@ int pch_silicon_type(void); int pch_is_lp(void); u16 get_pmbase(void); u16 get_gpiobase(void); + +/* Power Management register handling in pmutil.c */ +/* PM1_CNT */ +void enable_pm1_control(u32 mask); +void disable_pm1_control(u32 mask); +/* PM1 */ +u16 clear_pm1_status(void); +void enable_pm1(u32 mask); +u32 clear_smi_status(void); +/* SMI */ +void enable_smi(u32 mask); +void disable_smi(u32 mask); +/* ALT_GP_SMI */ +u32 clear_alt_smi_status(void); +void enable_alt_smi(u32 mask); +/* TCO */ +u32 clear_tco_status(void); +void enable_tco_sci(void); +/* GPE0 */ +u32 clear_gpe_status(void); +void clear_gpe_enable(void); +void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4); +void disable_all_gpe(void); +void enable_gpe(u32 mask); +void disable_gpe(u32 mask); + #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> #include <arch/acpi.h> @@ -590,10 +616,12 @@ unsigned get_gpios(const int *gpio_num_array); #define TCOSCI_STS (1 << 6) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) +#define GPE0_STS_2 0x24 #define GPE0_EN 0x28 #define PME_B0_EN (1 << 13) #define PME_EN (1 << 11) #define TCOSCI_EN (1 << 6) +#define GPE0_EN_2 0x2c #define SMI_EN 0x30 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic @@ -618,6 +646,18 @@ unsigned get_gpios(const int *gpio_num_array); #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +#define ALT_GP_SMI_EN2 0x5c +#define ALT_GP_SMI_STS2 0x5e + +/* Lynxpoint LP */ +#define LP_GPE0_STS_1 0x80 /* GPIO 0-31 */ +#define LP_GPE0_STS_2 0x84 /* GPIO 32-63 */ +#define LP_GPE0_STS_3 0x88 /* GPIO 64-94 */ +#define LP_GPE0_STS_4 0x8c /* Standard GPE */ +#define LP_GPE0_EN_1 0x90 +#define LP_GPE0_EN_2 0x94 +#define LP_GPE0_EN_3 0x98 +#define LP_GPE0_EN_4 0x9c /* * SPI Opcode Menu setup for SPIBAR lockdown diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c new file mode 100644 index 0000000..64fc585 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -0,0 +1,561 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * Helper functions for dealing with power management registers + * and the differences between LynxPoint-H and LynxPoint-LP. + */ + +#include <arch/io.h> +#ifdef __SMM__ +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#else /* !__SMM__ */ +#include <device/device.h> +#include <device/pci.h> +#endif + +#include <console/console.h> +#include "pch.h" + +#if CONFIG_INTEL_LYNXPOINT_LP +#include "lp_gpio.h" +#endif + +/* Print status bits with descriptive names */ +static void print_status_bits(u32 status, const char *bit_names[]) +{ + int i; + + if (!status) + return; + + for (i=31; i>=0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +/* Print status bits as GPIO numbers */ +static void print_gpio_status(u32 status, int start) +{ + int i; + + if (!status) + return; + + for (i=31; i>=0; i--) { + if (status & (1 << i)) + printk(BIOS_DEBUG, "GPIO%d ", start + i); + } +} + + +/* + * PM1_CNT + */ + +/* Enable events in PM1 control register */ +void enable_pm1_control(u32 mask) +{ + u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); + pm1_cnt |= mask; + outl(pm1_cnt, get_pmbase() + PM1_CNT); +} + +/* Disable events in PM1 control register */ +void disable_pm1_control(u32 mask) +{ + u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); + pm1_cnt &= ~mask; + outl(pm1_cnt, get_pmbase() + PM1_CNT); +} + + +/* + * PM1 + */ + +/* Clear and return PM1 status register */ +static u16 reset_pm1_status(void) +{ + u16 pm1_sts = inw(get_pmbase() + PM1_STS); + outw(pm1_sts, get_pmbase() + PM1_STS); + return pm1_sts; +} + +/* Print PM1 status bits */ +static u16 print_pm1_status(u16 pm1_sts) +{ + const char *pm1_sts_bits[] = { + [0] = "TMROF", + [4] = "BM", + [5] = "GBL", + [8] = "PWRBTN", + [10] = "RTC", + [11] = "PRBTNOR", + [14] = "PCIEXPWAK", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_SPEW, "PM1_STS: "); + print_status_bits(pm1_sts, pm1_sts_bits); + printk(BIOS_SPEW, "\n"); + + return pm1_sts; +} + +/* Print, clear, and return PM1 status */ +u16 clear_pm1_status(void) +{ + return print_pm1_status(reset_pm1_status()); +} + +/* Enable PM1 event */ +void enable_pm1(u32 mask) +{ + u32 pm1_en = inl(get_pmbase() + PM1_EN); + pm1_en |= mask; + outl(pm1_en, get_pmbase() + PM1_EN); +} + + +/* + * SMI + */ + +/* Clear and return SMI status register */ +static u32 reset_smi_status(void) +{ + u32 smi_sts = inl(get_pmbase() + SMI_STS); + outl(smi_sts, get_pmbase() + SMI_STS); + return smi_sts; +} + +/* Print SMI status bits */ +static u32 print_smi_status(u32 smi_sts) +{ + const char *smi_sts_bits[] = { + [2] = "BIOS", + [3] = "LEGACY_USB", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [8] = "PM1", + [9] = "GPE0", + [10] = "GPI", + [11] = "MCSMI", + [12] = "DEVMON", + [13] = "TCO", + [14] = "PERIODIC", + [15] = "SERIRQ_SMI", + [16] = "SMBUS_SMI", + [17] = "LEGACY_USB2", + [18] = "INTEL_USB2", + [20] = "PCI_EXP_SMI", + [21] = "MONITOR", + [26] = "SPI", + [27] = "GPIO_UNLOCK" + }; + + if (!smi_sts) + return 0; + + printk(BIOS_DEBUG, "SMI_STS: "); + print_status_bits(smi_sts, smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return smi_sts; +} + +/* Print, clear, and return SMI status */ +u32 clear_smi_status(void) +{ + return print_smi_status(reset_smi_status()); +} + +/* Enable SMI event */ +void enable_smi(u32 mask) +{ + u32 smi_en = inl(get_pmbase() + SMI_EN); + smi_en |= mask; + outl(smi_en, get_pmbase() + SMI_EN); +} + +/* Disable SMI event */ +void disable_smi(u32 mask) +{ + u32 smi_en = inl(get_pmbase() + SMI_EN); + smi_en &= ~mask; + outl(smi_en, get_pmbase() + SMI_EN); +} + + +/* + * ALT_GP_SMI + */ + +/* Clear GPIO SMI status and return events that are enabled and active */ +static u32 reset_alt_smi_status(void) +{ + u32 alt_sts, alt_en; + + if (pch_is_lp()) { + /* LynxPoint-LP moves this to GPIO region as dword */ + alt_sts = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_STS); + outl(alt_sts, get_gpiobase() + GPIO_ALT_GPI_SMI_STS); + + alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); + } else { + u16 pmbase = get_pmbase(); + + /* LynxPoint-H adds a second enable/status word */ + alt_sts = inw(pmbase + ALT_GP_SMI_STS2); + outw(alt_sts & 0xffff, pmbase + ALT_GP_SMI_STS2); + + alt_sts <<= 16; + alt_sts |= inw(pmbase + ALT_GP_SMI_STS); + outw(alt_sts & 0xffff, pmbase + ALT_GP_SMI_STS); + + alt_en = inw(pmbase + ALT_GP_SMI_EN2); + alt_en <<= 16; + alt_en |= inw(pmbase + ALT_GP_SMI_EN); + } + + /* Only report enabled events */ + return alt_sts & alt_en; +} + +/* Print GPIO SMI status bits */ +static u32 print_alt_smi_status(u32 alt_sts) +{ + if (!alt_sts) + return 0; + + printk(BIOS_DEBUG, "ALT_STS: "); + + if (pch_is_lp()) { + /* First 16 events are GPIO 32-47 */ + print_gpio_status(alt_sts & 0xffff, 32); + } else { + const char *alt_sts_bits_high[] = { + [0] = "GPIO17", + [1] = "GPIO19", + [2] = "GPIO21", + [3] = "GPIO22", + [4] = "GPIO43", + [5] = "GPIO56", + [6] = "GPIO57", + [7] = "GPIO60", + }; + + /* First 16 events are GPIO 0-15 */ + print_gpio_status(alt_sts & 0xffff, 0); + print_status_bits(alt_sts >> 16, alt_sts_bits_high); + } + + printk(BIOS_DEBUG, "\n"); + + return alt_sts; +} + +/* Print, clear, and return GPIO SMI status */ +u32 clear_alt_smi_status(void) +{ + return print_alt_smi_status(reset_alt_smi_status()); +} + +/* Enable GPIO SMI events */ +void enable_alt_smi(u32 mask) +{ + if (pch_is_lp()) { + u32 alt_en; + + alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); + alt_en |= mask; + outl(alt_en, get_gpiobase() + GPIO_ALT_GPI_SMI_EN); + } else { + u16 pmbase = get_pmbase(); + u16 alt_en; + + /* Lower enable register */ + alt_en = inw(pmbase + ALT_GP_SMI_EN); + alt_en |= mask & 0xffff; + outw(alt_en, pmbase + ALT_GP_SMI_EN); + + /* Upper enable register */ + alt_en = inw(pmbase + ALT_GP_SMI_EN2); + alt_en |= (mask >> 16) & 0xffff; + outw(alt_en, pmbase + ALT_GP_SMI_EN2); + } +} + + +/* + * TCO + */ + +/* Clear TCO status and return events that are enabled and active */ +static u32 reset_tco_status(void) +{ + u32 tcobase = get_pmbase() + 0x60; + u32 tco_sts = inl(tcobase + 0x04); + u32 tco_en = inl(get_pmbase() + 0x68); + + /* Don't clear BOOT_STS before SECOND_TO_STS */ + outl(tco_sts & ~(1 << 18), tcobase + 0x04); + + /* Clear BOOT_STS */ + if (tco_sts & (1 << 18)) + outl(tco_sts & (1 << 18), tcobase + 0x04); + + return tco_sts & tco_en; +} + +/* Print TCO status bits */ +static u32 print_tco_status(u32 tco_sts) +{ + const char *tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [18] = "BOOT", + [20] = "SMLINK_SLV" + }; + + if (!tco_sts) + return 0; + + printk(BIOS_DEBUG, "TCO_STS: "); + print_status_bits(tco_sts, tco_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return tco_sts; +} + +/* Print, clear, and return TCO status */ +u32 clear_tco_status(void) +{ + return print_tco_status(reset_tco_status()); +} + +/* Enable TCO SCI */ +void enable_tco_sci(void) +{ + u16 gpe0_sts = pch_is_lp() ? LP_GPE0_STS_4 : GPE0_STS; + + /* Clear pending events */ + outl(get_pmbase() + gpe0_sts, TCOSCI_STS); + + /* Enable TCO SCI events */ + enable_gpe(TCOSCI_EN); +} + + +/* + * GPE0 + */ + +/* Clear a GPE0 status and return events that are enabled and active */ +static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) +{ + u32 gpe0_sts = inl(get_pmbase() + sts_reg); + u32 gpe0_en = inl(get_pmbase() + en_reg); + + outl(gpe0_sts, get_pmbase() + sts_reg); + + /* Only report enabled events */ + return gpe0_sts & gpe0_en; +} + +/* Print GPE0 status bits */ +static u32 print_gpe_status(u32 gpe0_sts, const char *bit_names[]) +{ + if (!gpe0_sts) + return 0; + + printk(BIOS_DEBUG, "GPE0_STS: "); + print_status_bits(gpe0_sts, bit_names); + printk(BIOS_DEBUG, "\n"); + + return gpe0_sts; +} + +/* Print GPE0 GPIO status bits */ +static u32 print_gpe_gpio(u32 gpe0_sts, int start) +{ + if (!gpe0_sts) + return 0; + + printk(BIOS_DEBUG, "GPE0_STS: "); + print_gpio_status(gpe0_sts, start); + printk(BIOS_DEBUG, "\n"); + + return gpe0_sts; +} + +/* Print, clear, and return LynxPoint-H GPE0 status */ +static u32 clear_lpt_gpe_status(void) +{ + const char *gpe0_sts_bits_low[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [8] = "RI", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "PME", + [13] = "PME_B0", + [16] = "GPIO0", + [17] = "GPIO1", + [18] = "GPIO2", + [19] = "GPIO3", + [20] = "GPIO4", + [21] = "GPIO5", + [22] = "GPIO6", + [23] = "GPIO7", + [24] = "GPIO8", + [25] = "GPIO9", + [26] = "GPIO10", + [27] = "GPIO11", + [28] = "GPIO12", + [29] = "GPIO13", + [30] = "GPIO14", + [31] = "GPIO15", + }; + const char *gpe0_sts_bits_high[] = { + [3] = "GPIO27", + [6] = "WADT", + [24] = "GPIO17", + [25] = "GPIO19", + [26] = "GPIO21", + [27] = "GPIO22", + [28] = "GPIO43", + [29] = "GPIO56", + [30] = "GPIO57", + [31] = "GPIO60", + }; + + /* High bits */ + print_gpe_status(reset_gpe_status(GPE0_STS_2, GPE0_EN_2), + gpe0_sts_bits_high); + + /* Standard GPE and GPIO 0-31 */ + return print_gpe_status(reset_gpe_status(GPE0_STS, GPE0_EN), + gpe0_sts_bits_low); +} + +/* Print, clear, and return LynxPoint-LP GPE0 status */ +static u32 clear_lpt_lp_gpe_status(void) +{ + const char *gpe0_sts_4_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "PME", + [12] = "ME", + [13] = "PME_B0", + [16] = "GPIO27", + [18] = "WADT" + }; + + /* GPIO 0-31 */ + print_gpe_gpio(reset_gpe_status(LP_GPE0_STS_1, LP_GPE0_EN_1), 0); + + /* GPIO 32-63 */ + print_gpe_gpio(reset_gpe_status(LP_GPE0_STS_2, LP_GPE0_EN_2), 32); + + /* GPIO 64-94 */ + print_gpe_gpio(reset_gpe_status(LP_GPE0_STS_3, LP_GPE0_EN_3), 64); + + /* Standard GPE */ + return print_gpe_status(reset_gpe_status(LP_GPE0_STS_4, LP_GPE0_EN_4), + gpe0_sts_4_bits); +} + +/* Clear all GPE status and return "standard" GPE event status */ +u32 clear_gpe_status(void) +{ + if (pch_is_lp()) + return clear_lpt_lp_gpe_status(); + else + return clear_lpt_gpe_status(); +} + +/* Enable all requested GPE */ +void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) +{ + u16 pmbase = get_pmbase(); + + if (pch_is_lp()) { + outl(set1, pmbase + LP_GPE0_EN_1); + outl(set2, pmbase + LP_GPE0_EN_2); + outl(set3, pmbase + LP_GPE0_EN_3); + outl(set4, pmbase + LP_GPE0_EN_4); + } else { + outl(set1, pmbase + GPE0_EN); + outl(set2, pmbase + GPE0_EN_2); + } +} + +/* Disable all GPE */ +void disable_all_gpe(void) +{ + enable_all_gpe(0, 0, 0, 0); +} + +/* Enable a standard GPE */ +void enable_gpe(u32 mask) +{ + u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; + u32 gpe0_en = inl(get_pmbase() + gpe0_reg); + gpe0_en |= mask; + outl(gpe0_en, get_pmbase() + gpe0_reg); +} + +/* Disable a standard GPE */ +void disable_gpe(u32 mask) +{ + u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; + u32 gpe0_en = inl(get_pmbase() + gpe0_reg); + gpe0_en &= ~mask; + outl(gpe0_en, get_pmbase() + gpe0_reg); +}

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New patch to review for coreboot: 3af78a8 lynxpoint: Add helper functions for reading PM and GPIO base
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2812 -gerrit commit 3af78a8e1c90f2b6f3ae346b1f12215c29da0fcc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Mar 7 14:08:04 2013 -0800 lynxpoint: Add helper functions for reading PM and GPIO base These base addresses are used in several places and it is helpful to have one location that is reading it. Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/haswell/acpi.c | 4 +++- src/cpu/intel/haswell/haswell_init.c | 2 +- src/southbridge/intel/lynxpoint/pch.c | 20 ++++++++++++++++++++ src/southbridge/intel/lynxpoint/pch.h | 3 ++- 4 files changed, 26 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index c0df9f6..a4d9cd9 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -33,6 +33,8 @@ #include "haswell.h" #include "chip.h" +#include <southbridge/intel/lynxpoint/pch.h> + static int get_cores_per_package(void) { struct cpuinfo_x86 c; @@ -322,7 +324,7 @@ static int generate_P_state_entries(int core, int cores_per_package) void generate_cpu_entries(void) { int len_pr; - int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; + int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); int numcpus = totalcores/cores_per_package; diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index c7f89ee..0bb11a8 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -267,7 +267,7 @@ static void configure_c_states(void) msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); msr.lo &= ~0x7ffff; - msr.lo |= (PMB0_BASE + 4); // LVL_2 base address + msr.lo |= (get_pmbase() + 4); // LVL_2 base address msr.lo |= (2 << 16); // CST Range: C7 is max C-state wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 6f03716..b4f64e1 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -65,6 +65,26 @@ int pch_is_lp(void) return pch_silicon_type() == PCH_TYPE_LPT_LP; } +u16 get_pmbase(void) +{ + static u16 pmbase; + + if (!pmbase) + pmbase = pci_read_config16(pch_get_lpc_device(), + PMBASE) & 0xfffc; + return pmbase; +} + +u16 get_gpiobase(void) +{ + static u16 gpiobase; + + if (!gpiobase) + gpiobase = pci_read_config16(pch_get_lpc_device(), + GPIOBASE) & 0xfffc; + return gpiobase; +} + #ifndef __SMM__ /* Set bit in Function Disble register to hide this device */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 38202b5..db9bb77 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -130,7 +130,8 @@ void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_type(void); int pch_is_lp(void); - +u16 get_pmbase(void); +u16 get_gpiobase(void); #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> #include <arch/acpi.h>

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New patch to review for coreboot: 9776a16 lynxpoint: Add function for checking for LP chipset
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2811 -gerrit commit 9776a16d3c5edde2c25201bd384e25c61203065c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Mar 7 14:06:43 2013 -0800 lynxpoint: Add function for checking for LP chipset Add a helper function pch_is_lp() that will return 1 if the current chipset is of the new "low power" variant used with Haswell ULT. Additionally these functions are added to SMM so it can be used there. Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/pch.c | 40 ++++++++++++++++++++-------- src/southbridge/intel/lynxpoint/pch.h | 13 +++++---- 3 files changed, 38 insertions(+), 17 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index fd5b4df..3710135 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -45,7 +45,7 @@ ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 41c596c..6f03716 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,36 +21,52 @@ #include <console/console.h> #include <delay.h> +#ifdef __SMM__ +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#else /* !__SMM__ */ #include <device/device.h> #include <device/pci.h> +#endif #include "pch.h" -static int pch_revision_id = -1; -static int pch_type = -1; +static device_t pch_get_lpc_device(void) +{ +#ifdef __SMM__ + return PCI_DEV(0, 0x1f, 0); +#else + return dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +#endif +} int pch_silicon_revision(void) { + static int pch_revision_id = -1; + if (pch_revision_id < 0) - pch_revision_id = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PCI_REVISION_ID); + pch_revision_id = pci_read_config8(pch_get_lpc_device(), + PCI_REVISION_ID); return pch_revision_id; } int pch_silicon_type(void) { + static int pch_type = -1; + if (pch_type < 0) - pch_type = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PCI_DEVICE_ID + 1); + pch_type = pci_read_config8(pch_get_lpc_device(), + PCI_DEVICE_ID + 1); return pch_type; } -int pch_silicon_supported(int type, int rev) +int pch_is_lp(void) { - return 1; + return pch_silicon_type() == PCH_TYPE_LPT_LP; } +#ifndef __SMM__ + /* Set bit in Function Disble register to hide this device */ static void pch_hide_devfn(unsigned devfn) { @@ -444,3 +460,5 @@ struct chip_operations southbridge_intel_lynxpoint_ops = { CHIP_NAME("Intel Series 8 (Lynx Point) Southbridge") .enable_dev = pch_enable, }; + +#endif /* __SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 563730e..38202b5 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -40,9 +40,9 @@ * Bus 0:Device 28:Function 5 PCI Express Port 6 * Bus 0:Device 28:Function 6 PCI Express Port 7 * Bus 0:Device 28:Function 7 PCI Express Port 8 - * Bus 0:Device 27:Function 0 Intel® High Definition Audio Controller + * Bus 0:Device 27:Function 0 Intel High Definition Audio Controller * Bus 0:Device 25:Function 0 Gigabit Ethernet Controller - * Bus 0:Device 22:Function 0 Intel® Management Engine Interface #1 + * Bus 0:Device 22:Function 0 Intel Management Engine Interface #1 * Bus 0:Device 22:Function 1 Intel Management Engine Interface #2 * Bus 0:Device 22:Function 2 IDE-R * Bus 0:Device 22:Function 3 KT @@ -50,6 +50,8 @@ */ /* PCH types */ +#define PCH_TYPE_LPT 0x8c +#define PCH_TYPE_LPT_LP 0x9c /* PCH stepping values for LPC device */ @@ -125,13 +127,14 @@ struct rcba_config_instruction #if !defined(__ASSEMBLER__) && !defined(__ROMCC__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); +int pch_silicon_revision(void); +int pch_silicon_type(void); +int pch_is_lp(void); + #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> #include <arch/acpi.h> #include "chip.h" -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); void pch_enable(device_t dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG

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New patch to review for coreboot: 6eb3a56 lynxpoint: Enable EC IO ports 0x62/0x66
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2810 -gerrit commit 6eb3a56b9ab502c446647bb8bbe96214755dfbef Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Mar 7 14:00:43 2013 -0800 lynxpoint: Enable EC IO ports 0x62/0x66 In order to be able to talk to an EC via standard path. Change-Id: I3fe76882dec9a0596cbc1c844afa2ddb03ed771c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/early_pch.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index e7b62b4..3709aed 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -90,8 +90,9 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); - /* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; + /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | + COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); }

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coreboot March 2013