coreboot February 2013

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Patch merged into coreboot/master: 315dec4 bootblock: Reduce register load
by gerrit＠coreboot.org 06 Feb '13

06 Feb '13

the following patch was just integrated into master: commit 315dec48ea6ae4f06dc3a0751dfa2ddf9ff55fba Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Feb 6 11:37:08 2013 +0100 bootblock: Reduce register load The common part of the bootblock resets the nvram data if it's found to be invalid. Since that code is compiled with romcc in i386 mode, there's a shortage on registers. Try to reduce the strain by doing things smarter: cmos_write_inner is the same as cmos_write, just that it doesn't check if the RTC is disabled. Since we just disabled it before, we can assume that it is so. Change-Id: Ic85eb2a5df949d1c1aff654bc1b40d6f2ff71756 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2296 Tested-by: build bot (Jenkins) Reviewed-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> See http://review.coreboot.org/2296 for details. -gerrit

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New patch to review for coreboot: 2e4ab4f console: Revise console initialization.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2299 -gerrit commit 2e4ab4f237e12eb5cddc3bc6074da5f0001a27db Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 17:51:19 2013 +0800 console: Revise console initialization. Provides an unified way to configure and start console. In Kconfig, use these variables to control console output: - EARLY_CONSOLE: Outputs in pre-ram stage (bootblock and romstage). - CONSOLE_SERIAL: Enable serial output console, from one of following drivers: - CONSOLE_SERIAL8250 (standard 8250 chipset for most x86 devices) - CONSOLE_SERIAL8250MEM (8250 with memory-mapped I/O) - CONSOLE_SERIAL_UART (device-specific UART driver for most ARM devices) In bootblock/romstage/ramstage, to output message to console: #include <console/console.h> ... init_console(); printk(level, format, ...); Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/Kconfig | 4 ++ src/arch/armv7/Makefile.inc | 9 ++-- src/arch/armv7/bootblock_simple.c | 2 + src/arch/armv7/include/common.h | 13 ------ src/arch/armv7/lib/Makefile.inc | 8 ++-- src/arch/armv7/lib/early_console.c | 81 +++++++++++++++++++++++++++++++++ src/arch/armv7/lib/romstage_console.c | 73 ----------------------------- src/console/Kconfig | 39 ++++++++-------- src/console/Makefile.inc | 8 ++-- src/console/console.c | 10 ++-- src/cpu/Kconfig | 2 +- src/cpu/samsung/Kconfig | 5 +- src/cpu/samsung/exynos5-common/uart.h | 2 - src/cpu/samsung/exynos5250/Makefile.inc | 13 ++---- src/cpu/samsung/exynos5250/uart.c | 4 +- src/include/console/console.h | 21 +++++++-- src/include/uart.h | 9 ++-- src/mainboard/google/snow/Kconfig | 5 +- src/mainboard/google/snow/bootblock.c | 12 ++--- 19 files changed, 163 insertions(+), 157 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 92bdf11..32a63d8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -277,6 +277,10 @@ config HAVE_UART_MEMORY_MAPPED bool default n +config HAVE_UART_SPECIAL + bool + default n + config HAVE_ACPI_RESUME bool default n diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 7d02e7c..0471b94 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -223,17 +223,18 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC) $(bootblock-c-ccopts) $(INCLUDES) -MM \ + -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ + $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index fe2662e..0132b87 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -23,6 +23,7 @@ #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> +#include <console/console.h> #include "stages.c" @@ -46,6 +47,7 @@ void main(void) bootblock_mainboard_init(); } + console_init(); printk(BIOS_INFO, "hello from bootblock\n"); printk(BIOS_INFO, "bootblock main(): loading romstage\n"); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index d95a74d..d8698db 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -422,19 +422,6 @@ int strcmp_compar(const void *, const void *); /* lib/time.c */ void udelay (unsigned long); -#if 0 -/* lib/vsprintf.c */ -ulong simple_strtoul(const char *cp,char **endp,unsigned int base); -int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); -unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); -long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2), noreturn)); -int sprintf(char * buf, const char *fmt, ...) - __attribute__ ((format (__printf__, 2, 3))); -int vsprintf(char *buf, const char *fmt, va_list args); -#endif - /* lib/strmhz.c */ char * strmhz(char *buf, unsigned long hz); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 343e9f8..b8dab64 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,14 +1,14 @@ bootblock-y += syslib.c -bootblock-y += romstage_console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c +# bootblock-y += early_console.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += div64.S -romstage-y += romstage_console.c romstage-y += syslib.c - -#ramstage-y += printk_init.c +# romstage-y += early_console.c +romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c ramstage-y += div64.S diff --git a/src/arch/armv7/lib/early_console.c b/src/arch/armv7/lib/early_console.c new file mode 100644 index 0000000..68e81c6 --- /dev/null +++ b/src/arch/armv7/lib/early_console.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +/* FIXME: need to make console driver more generic */ +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL8250MEM + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif +} + +static void _console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) { + return 0; + } + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + _console_tx_flush(); + + return i; +} diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c deleted file mode 100644 index 42a9664..0000000 --- a/src/arch/armv7/lib/romstage_console.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/vtxprintf.h> -// TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_SERIAL_CONSOLE -#include <uart.h> -#endif -#if CONFIG_USBDEBUG -#include <usbdebug.h> -#endif - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_SERIAL_CONSOLE - uart_tx_byte(byte); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_CBMEM - cbmemc_tx_byte(byte); -#endif -} - -static void _console_tx_flush(void) -{ -#if CONFIG_SERIAL_CONSOLE - uart_tx_flush(); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_flush(0); -#endif -} - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - _console_tx_flush(); - - return i; -} diff --git a/src/console/Kconfig b/src/console/Kconfig index b1f41de..e57d568 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,20 +1,21 @@ menu "Console" -config SERIAL_CONSOLE - bool "Serial port console output" - default y - help - Send coreboot debug output to a serial port -config EARLY_SERIAL_CONSOLE - bool - depends on SERIAL_CONSOLE +config EARLY_CONSOLE + bool "Enable early (pre-RAM) console output." default n help - Use serial console during early (pre-RAM) boot stages + Use console during early (pre-RAM) boot stages + +config CONSOLE_SERIAL + bool "Serial port console output" + default y + help + Send coreboot debug output to a serial port (should be one or more of + CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) config CONSOLE_SERIAL8250 bool "Serial port console output (I/O mapped, 8250-compatible)" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL depends on HAVE_UART_IO_MAPPED default y help @@ -22,21 +23,21 @@ config CONSOLE_SERIAL8250 config CONSOLE_SERIAL8250MEM bool "Serial port console output (memory mapped, 8250-compatible)" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL depends on HAVE_UART_MEMORY_MAPPED help Send coreboot debug output to a memory mapped serial port console. -config CONSOLE_SERIAL_NONSTANDARD_MEM - bool "Serial port console output (memory-mapped, device-specific)" - depends on SERIAL_CONSOLE - depends on HAVE_UART_MEMORY_MAPPED +config CONSOLE_SERIAL_UART + bool "Serial port console output (device-specific UART)" + depends on CONSOLE_SERIAL + depends on HAVE_UART_SPECIAL + default y help - Send coreboot debug output to a memory mapped serial port console - on a device-specific UART. + Send coreboot debug output to a device-specific serial port console. choice - prompt "Serial port" + prompt "Serial port for 8250" default CONSOLE_SERIAL_COM1 depends on CONSOLE_SERIAL8250 @@ -72,7 +73,7 @@ config TTYS0_BASE choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_115200 bool "115200" diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 42d3282..9ce3474 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,13 +9,13 @@ smm-y += printk.c smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c -romstage-y += vtxprintf.c -romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +romstage-y += console.c romstage-y += post.c romstage-y += die.c -bootblock-y += vtxprintf.c -bootblock-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +bootblock-y += console.c bootblock-y += post.c bootblock-y += die.c diff --git a/src/console/console.c b/src/console/console.c index 4c47d7f..fc77df7 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,15 +99,15 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined -#include <uart.h> - void console_init(void) { +#if CONFIG_EARLY_CONSOLE + #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL uart_init(); #endif #if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM @@ -127,5 +127,7 @@ void console_init(void) COREBOOT_BUILD " starting...\n"; print_info(console_test); + +#endif /* CONFIG_EARLY_CONSOLE */ } -#endif +#endif /* __PRE_RAM__ */ diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index ddc46cf..c2c3816 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,7 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select EARLY_SERIAL_CONSOLE + select EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index abfc049..c905b2a 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -5,7 +5,10 @@ config CPU_SAMSUNG_EXYNOS config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS - select EARLY_SERIAL_CONSOLE + select HAVE_UART_SPECIAL + # TODO remove EARLY_CONSOLE when we can run ramstage without early UART + # init. + select EARLY_CONSOLE bool default n diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h index 52da62d..350e224 100644 --- a/src/cpu/samsung/exynos5-common/uart.h +++ b/src/cpu/samsung/exynos5-common/uart.h @@ -52,6 +52,4 @@ static inline int s5p_uart_divslot(void) return 0; } -void uart_init(void); - #endif diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e2033ff..7e11536 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -11,7 +11,7 @@ bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += power.c bootblock-y += soc.c -bootblock-y += uart.c +bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c romstage-y += clock_init.c @@ -19,23 +19,18 @@ romstage-y += exynos_cache.c romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c -romstage-y += uart.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c +romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -#ramstage-y += clock.c -#ramstage-y += clock_init.c -#ramstage-y += power.c -#ramstage-y += uart.c -#ramstage-y += pinmux.c -##ramstage-y += tzpc_init.c +#ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c -ramstage-y += uart.c +ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3126d7a..dacdc10 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,6 +28,8 @@ #include <console/console.h> /* for __console definition */ #include <cpu/samsung/exynos5-common/exynos5-common.h> +#include <cpu/samsung/exynos5-common/uart.h> +#include <cpu/samsung/exynos5250/uart.h> #include <cpu/samsung/exynos5250/clk.h> #define RX_FIFO_COUNT_MASK 0xff @@ -188,7 +190,7 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } -#if !defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) +#if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, diff --git a/src/include/console/console.h b/src/include/console/console.h index 375e5a4..6b057f0 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,8 +24,8 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> +#if CONFIG_CONSOLE_SERIAL +#include <uart.h> #endif #if CONFIG_USBDEBUG #include <usbdebug.h> @@ -74,6 +74,15 @@ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +#if defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE + +static inline void printk(int LEVEL, const char *fmt, ...); +static inline void printk(int LEVEL, const char *fmt, ...) { + /* Do nothing. */ +} + +#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ + #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS /* We saw some strange effects in the past like coreboot crashing while * disabling cache as ram for a maximum console log level of 6 and above while @@ -88,6 +97,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, * avoid this, do a * #define WE_CLEANED_UP_ALL_SIDE_EFFECTS */ + #ifdef WE_CLEANED_UP_ALL_SIDE_EFFECTS #define printk(LEVEL, fmt, args...) \ @@ -97,7 +107,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, } \ } while(0) -#else +#else /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */ #define printk(LEVEL, fmt, args...) \ do { \ @@ -107,7 +117,10 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, do_printk(BIOS_NEVER, fmt, ##args); \ } \ } while(0) -#endif + +#endif /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */ + +#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) diff --git a/src/include/uart.h b/src/include/uart.h index 2a72575..ca5191e 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -26,18 +26,15 @@ #ifndef UART_H #define UART_H -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif -#if CONFIG_CPU_SAMSUNG_EXYNOS5 -#include <cpu/samsung/exynos5-common/uart.h> -#endif - -#ifndef __ROMCC__ +#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); +void uart_init(void); #endif #endif /* UART_H */ diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index a0c76d6..bee987d 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS5 select HAVE_UART_MEMORY_MAPPED - select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging # select EC_GOOGLE_CHROMEEC select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 @@ -71,7 +70,7 @@ config NR_DRAM_BANKS choice prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_NONSTANDARD_MEM + depends on CONSOLE_SERIAL_UART config CONSOLE_SERIAL_UART0 bool "UART0" @@ -97,7 +96,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_NONSTANDARD_MEM + depends on CONSOLE_SERIAL_UART default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 64b12c6..be5a99f 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,12 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_SERIAL_CONSOLE #include <types.h> #include <arch/io.h> -#include <cbfs.h> -#include <uart.h> -#include <console/console.h> #include <device/i2c.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -30,9 +26,9 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <src/cpu/samsung/exynos5250/power.h> #include <drivers/maxim/max77686/max77686.h> +#include <console/console.h> #define I2C0_BASE 0x12c60000 -#endif void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) @@ -46,10 +42,8 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - -#if CONFIG_EARLY_SERIAL_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - uart_init(); + + console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); -#endif }

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New patch to review for coreboot: 4d41ed8 armv7: Clean up: replace hang() by hlt().
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2298 -gerrit commit 4d41ed83d18dfd8593a5e637ef3a1d2b6970be8c Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 18:03:40 2013 +0800 armv7: Clean up: replace hang() by hlt(). hang() is the legacy function from U-boot and should be replaced by hlt() in coreboot. Change-Id: I0f390b1b6f9ff71487ea36cf16c462724b66d8ca Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/include/common.h | 2 -- src/arch/armv7/include/hang.h | 20 -------------------- src/arch/armv7/lib/Makefile.inc | 2 -- src/arch/armv7/lib/hang_spl.c | 16 ---------------- src/cpu/samsung/exynos5-common/spl_boot.c | 2 +- 5 files changed, 1 insertion(+), 41 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index 1b69e84..d95a74d 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -129,8 +129,6 @@ ulong timer_get_us(void); * Function Prototypes */ -void hang (void) __attribute__ ((noreturn)); - int init_timer(void); /* FIXME(dhendrix): used to be timer_init() */ int cpu_init(void); diff --git a/src/arch/armv7/include/hang.h b/src/arch/armv7/include/hang.h deleted file mode 100644 index f57fc28..0000000 --- a/src/arch/armv7/include/hang.h +++ /dev/null @@ -1,20 +0,0 @@ - /* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -void hang(void); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 4fd15a6..343e9f8 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -5,7 +5,6 @@ romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += div64.S -romstage-y += hang_spl.c romstage-y += romstage_console.c romstage-y += syslib.c @@ -13,7 +12,6 @@ romstage-y += syslib.c ramstage-y += div0.c ramstage-y += div64.S -ramstage-y += hang_spl.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S diff --git a/src/arch/armv7/lib/hang_spl.c b/src/arch/armv7/lib/hang_spl.c deleted file mode 100644 index 630a57a..0000000 --- a/src/arch/armv7/lib/hang_spl.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - */ - -#include <hang.h> - -void hang(void) -{ - for (;;); -} diff --git a/src/cpu/samsung/exynos5-common/spl_boot.c b/src/cpu/samsung/exynos5-common/spl_boot.c index ddf6937..101afeb 100644 --- a/src/cpu/samsung/exynos5-common/spl_boot.c +++ b/src/cpu/samsung/exynos5-common/spl_boot.c @@ -410,7 +410,7 @@ void panic(const char *fmt, ...) putc('\n'); va_end(args); #if defined(CONFIG_PANIC_HANG) - hang(); + hlt(); #else udelay(100000); /* allow messages to go out */ do_reset(NULL, 0, 0, NULL);

1 0

New patch to review for coreboot: 58e1bbc armv7: Clean up: femove "SPL_BUILD" configuation.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2297 -gerrit commit 58e1bbc8e1cfc26d0880d9c9f5b6666bfce8fbc3 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 17:48:20 2013 +0800 armv7: Clean up: femove "SPL_BUILD" configuation. "SPL" in U-Boot is almost identical to bootblock in coreboot, so we don't need it anymore. Change-Id: Id16877075d0b870839a10160073ad70777a2af0a Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Kconfig | 4 ---- src/arch/armv7/lib/eabi_compat.c | 5 ++--- src/cpu/samsung/exynos5250/Kconfig | 4 ---- src/cpu/samsung/exynos5250/clk.h | 3 --- src/cpu/samsung/exynos5250/clock_init.c | 2 -- src/cpu/samsung/s5p-common/cpu_info.c | 2 +- src/cpu/samsung/s5p-common/s5p_gpio.c | 2 -- src/cpu/samsung/s5p-common/timer.c | 3 +-- 8 files changed, 4 insertions(+), 21 deletions(-) diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 65de2d5..488ca97 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -1,9 +1,5 @@ menu "Architecture (armv7)" -config SPL_BUILD - bool "Build second-phase bootloader (SPL)" - default y - config EABI_COMPAT bool "Toolchain is EABI compatible" default n diff --git a/src/arch/armv7/lib/eabi_compat.c b/src/arch/armv7/lib/eabi_compat.c index 5f59892..2772de6 100644 --- a/src/arch/armv7/lib/eabi_compat.c +++ b/src/arch/armv7/lib/eabi_compat.c @@ -10,14 +10,13 @@ */ #include <common.h> +#include <console/console.h> /* FIXME(dhendrix): prototypes added for assembler */ int raise (int signum); int raise (int signum) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - printf("raise: Signal # %d caught\n", signum); -#endif + printk(BIOS_CRIT, "raise: Signal # %d caught\n", signum); return 0; } diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 6a09d88..0b07b90 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -88,10 +88,6 @@ config SYS_SDRAM_BASE hex "SDRAM base address" default 0x40000000 -config SPL_BUILD - bool - default n - config SYS_TEXT_BASE hex "Executable code section" default 0x43e00000 diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index 2de949a..dbddce0 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -564,8 +564,6 @@ const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf); * At present we are using 14148 of 14336 bytes. If we change this function * to be exported in SPL, we go over the edge. */ -/* TODO(dhendrix): do we still need this ifndef? */ -//#ifndef CONFIG_SPL_BUILD /** * Get the required memory type and speed (Main U-Boot version). * @@ -581,6 +579,5 @@ const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf); int clock_get_mem_selection(enum ddr_mode *mem_type, unsigned *frequency_mhz, unsigned *arm_freq, enum mem_manuf *mem_manuf); -//#endif /* CONFIG_SPL_BUILD */ #endif diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 4f21022..27e96ae 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,7 +452,6 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -#ifdef CONFIG_SPL_BUILD /* * This is a custom implementation for the udelay(), as we do not the timer * initialise during the SPL boot. We are assuming the cpu takes 3 instruction @@ -466,4 +465,3 @@ void udelay(unsigned usec) count = usec * (get_pll_clk(APLL) / (3 * 10000000)); sdelay(count); } -#endif diff --git a/src/cpu/samsung/s5p-common/cpu_info.c b/src/cpu/samsung/s5p-common/cpu_info.c index 6b4742e..1c4c49f 100644 --- a/src/cpu/samsung/s5p-common/cpu_info.c +++ b/src/cpu/samsung/s5p-common/cpu_info.c @@ -92,7 +92,7 @@ int print_cpuinfo(void) } #endif -#ifndef CONFIG_SPL_BUILD +#if 0 void board_show_dram(ulong size) { enum ddr_mode mem_type; diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index 0023beb..e91b9df 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -95,9 +95,7 @@ static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio) } } -#ifndef CONFIG_SPL_BUILD assert(gpio < GPIO_MAX_PORT); /* ...which it will not be */ -#endif return NULL; } //#endif diff --git a/src/cpu/samsung/s5p-common/timer.c b/src/cpu/samsung/s5p-common/timer.c index 373c374..c6ed830 100644 --- a/src/cpu/samsung/s5p-common/timer.c +++ b/src/cpu/samsung/s5p-common/timer.c @@ -67,7 +67,7 @@ int init_timer(void) pwm_init(4, MUX_DIV_4, 0); pwm_config(4, 100000, 100000); pwm_enable(4); -#ifndef CONFIG_SPL_BUILD + /* Use this as the current monotonic time in us */ //gd->timer_reset_value = 0; timer_reset_value = 0; @@ -75,7 +75,6 @@ int init_timer(void) /* Use this as the last timer value we saw */ //gd->lastinc = timer_get_us_down(); lastinc = timer_get_us_down(); -#endif } return 0;

1 0

Patch set updated for coreboot: 48838bc snow: remove dead code from bootblock
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2291 -gerrit commit 48838bcf2c82004415deb97b273311e9cdee9cc1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Feb 5 15:24:54 2013 -0800 snow: remove dead code from bootblock This attempts to clean out some dead code which was copy + pasted into Snow's bootblock.c file, along with some unnecessary headers. Change-Id: If9f157a52395a047c249a2a6385e0e8ddf310e59 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 107 +++------------------------------- 1 file changed, 9 insertions(+), 98 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 90a2de1..fc0b208 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,90 +17,20 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdlib.h> #include <types.h> -#include <assert.h> -#include <arch/armv7/include/common.h> #include <arch/io.h> -#include "cpu/samsung/exynos5250/clk.h" -#include "cpu/samsung/exynos5250/cpu.h" -#include "cpu/samsung/exynos5250/dmc.h" -#include "cpu/samsung/exynos5250/gpio.h" -#include "cpu/samsung/exynos5250/periph.h" -#include "cpu/samsung/exynos5250/setup.h" -#include "cpu/samsung/exynos5250/clock_init.h" -#include "cpu/samsung/s5p-common/gpio.h" -#include "cpu/samsung/s5p-common/s3c24x0_i2c.h" -#include "cpu/samsung/exynos5-common/spi.h" - -#include <device/i2c.h> -#include <drivers/maxim/max77686/max77686.h> +#include <cbfs.h> #include <uart.h> - #include <console/console.h> -#include <cbfs.h> - -#define EXYNOS5_CLOCK_BASE 0x10010000 - -#define CONFIG_SYS_CLK_FREQ 24000000 - -void puts(const char *s); -void puts(const char *s) -{ - int n = 0; - - while (*s) { - if (*s == '\n') { - uart_tx_byte(0xd); /* CR */ - } - - uart_tx_byte(*s++); - n++; - } -} - -static void do_serial(void) -{ - //exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - gpio_set_pull(GPIO_A14, EXYNOS_GPIO_PULL_NONE); - gpio_cfg_pin(GPIO_A15, EXYNOS_GPIO_FUNC(0x2)); - - uart_init(); -} +#include <device/i2c.h> +#include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/dmc.h> +#include <cpu/samsung/exynos5250/periph.h> +#include <cpu/samsung/exynos5250/clock_init.h> +#include <drivers/maxim/max77686/max77686.h> #define I2C0_BASE 0x12c60000 -void do_barriers(void); -void do_barriers(void) -{ - /* - * The reason we don't write out the instructions dsb/isb/sev: - * While ARM Cortex-A8 supports ARM v7 instruction set (-march=armv7a), - * we compile with -march=armv5 to allow more compilers to work. - * For U-Boot code this has no performance impact. - */ - __asm__ __volatile__( -#if defined(__thumb__) - ".hword 0xF3BF, 0x8F4F\n" /* dsb; darn -march=armv5 */ - ".hword 0xF3BF, 0x8F6F\n" /* isb; darn -march=armv5 */ - ".hword 0xBF40\n" /* sev; darn -march=armv5 */ -#else - ".word 0xF57FF04F\n" /* dsb; darn -march=armv5 */ - ".word 0xF57FF06F\n" /* isb; darn -march=armv5 */ - ".word 0xE320F004\n" /* sev; darn -march=armv5 */ -#endif - ); -} - -/* is this right? meh, it seems to work well enough... */ -void my_udelay(unsigned int n); -void my_udelay(unsigned int n) -{ - n *= 1000; - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (n):"0"(n)); -} - /* * Max77686 parameters values * see max77686.h for parameters details @@ -359,13 +289,6 @@ static void power_init(void) #define is_digit isdigit #define isxdigit(c) (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'f') || ((c) >= 'A' && (c) <= 'F')) -void __div0 (void); -void __div0 (void) -{ - puts("divide by zero detected"); - while(1) ; -} - static int skip_atoi(const char **s) { int i=0; @@ -649,20 +572,8 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - do_serial(); + exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + uart_init(); printk(BIOS_INFO, "%s: UART initialized\n", __func__); - -#if 0 - /* FIXME: dump SRAM content for sanity checking */ - uint32_t u; - for (u = CONFIG_SPI_IMAGE_HACK; u < CONFIG_SPI_IMAGE_HACK + 128; u++) { - if (u % 16 == 0) - printk(BIOS_INFO, "\n0x%08x: ", u); - else - printk(BIOS_INFO, " "); - printk(BIOS_INFO, "%02x", *(uint8_t *)(u)); - } - printk(BIOS_INFO, "\n"); -#endif printk(BIOS_INFO, "%s: finished\n", __func__); }

1 0

Patch set updated for coreboot: 2b811a5 armv7: Clean up arm/snow bootblock build process.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2282 -gerrit commit 2b811a54639ed37178e62385dac0c39da55f35c6 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Feb 4 14:38:03 2013 +0800 armv7: Clean up arm/snow bootblock build process. Remove duplicated / testing code and share more driver for bootblock, romstage and ramstage. The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is also executed before RAM is initialized. Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- Makefile.inc | 6 +- src/arch/armv7/bootblock_exit.c | 28 -- src/arch/armv7/bootblock_simple.c | 10 +- src/arch/armv7/include/arch/bootblock_exit.h | 26 -- src/arch/armv7/include/arch/stages.h | 2 +- src/arch/armv7/lib/Makefile.inc | 2 +- src/arch/armv7/lib/romstage_console.c | 12 +- src/arch/armv7/stages.c | 4 +- src/console/Makefile.inc | 5 + src/cpu/samsung/exynos5-common/clk.h | 2 +- src/cpu/samsung/exynos5250/Makefile.inc | 1 + src/cpu/samsung/exynos5250/clock_init.h | 1 + src/cpu/samsung/exynos5250/power.c | 3 +- src/cpu/samsung/exynos5250/uart.c | 3 + src/cpu/samsung/s5p-common/s3c24x0_i2c.c | 14 +- src/drivers/maxim/max77686/Makefile.inc | 1 + src/mainboard/google/snow/Makefile.inc | 1 + src/mainboard/google/snow/bootblock.c | 536 +-------------------------- src/mainboard/google/snow/romstage.c | 59 +-- 19 files changed, 47 insertions(+), 669 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 0b473e4..069bdfe 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -111,8 +111,8 @@ $(error Your current configuration requires binary-only components, but you did endif endif -bootblock-c-ccopts:=-D__BOOT_BLOCK__ -bootblock-S-ccopts:=-D__BOOT_BLOCK__ +bootblock-c-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ +bootblock-S-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ smm-c-ccopts:=-D__SMM__ smm-S-ccopts:=-D__SMM__ @@ -292,7 +292,7 @@ $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $ $(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -D__BOOT_BLOCK__ $(CFLAGS) -c -o $@ $< + $(CC) -MMD $(bootblock-c-ccopts) $(CFLAGS) -c -o $@ $< ####################################################################### # Clean up rules diff --git a/src/arch/armv7/bootblock_exit.c b/src/arch/armv7/bootblock_exit.c deleted file mode 100644 index 8b97d6b..0000000 --- a/src/arch/armv7/bootblock_exit.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/bootblock_exit.h> - -void bootblock_exit(unsigned long addr) -{ - __attribute__((noreturn)) void (*doit)(void) = (void *)addr; - doit(); -} diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index e808edc..fe2662e 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -38,19 +38,19 @@ static int boot_cpu(void) void main(void) { - const char *target1 = "fallback/romstage"; - unsigned long romstage_entry; + const char *stage_name = "fallback/romstage"; + void *entry; if (boot_cpu()) { bootblock_cpu_init(); bootblock_mainboard_init(); } + printk(BIOS_INFO, "hello from bootblock\n"); printk(BIOS_INFO, "bootblock main(): loading romstage\n"); - romstage_entry = (unsigned long)cbfs_load_stage( - CBFS_DEFAULT_MEDIA, target1); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); printk(BIOS_INFO, "bootblock main(): jumping to romstage\n"); - if (romstage_entry) stage_exit(romstage_entry); + if (entry) stage_exit(entry); hlt(); } diff --git a/src/arch/armv7/include/arch/bootblock_exit.h b/src/arch/armv7/include/arch/bootblock_exit.h deleted file mode 100644 index 0a039e1..0000000 --- a/src/arch/armv7/include/arch/bootblock_exit.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/** - * This is a shim that is to be compiled for the instruction set matching - * that of the entry point for the next boot stage (romstage). - */ -void bootblock_exit(unsigned long addr); diff --git a/src/arch/armv7/include/arch/stages.h b/src/arch/armv7/include/arch/stages.h index 215aaa8..671c02b 100644 --- a/src/arch/armv7/include/arch/stages.h +++ b/src/arch/armv7/include/arch/stages.h @@ -23,6 +23,6 @@ extern void main(void); void stage_entry(void) __attribute__((section(".text.stage_entry.armv7"))); -void stage_exit(unsigned long); +void stage_exit(void *); #endif diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index e0445ce..4fd15a6 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += syslib.c +bootblock-y += romstage_console.c romstage-y += cache_v7.c romstage-y += cache-cp15.c @@ -9,7 +10,6 @@ romstage-y += romstage_console.c romstage-y += syslib.c #ramstage-y += printk_init.c -#romstage-y += walkcbfs.S ramstage-y += div0.c ramstage-y += div64.S diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c index ead26f3..42a9664 100644 --- a/src/arch/armv7/lib/romstage_console.c +++ b/src/arch/armv7/lib/romstage_console.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <console/vtxprintf.h> +// TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) #if CONFIG_SERIAL_CONSOLE #include <uart.h> #endif @@ -43,18 +44,15 @@ void console_tx_byte(unsigned char byte) #endif } -/* FIXME(dhendrix): add this back in */ -#if 0 -static void console_tx_flush(void) +static void _console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); +#if CONFIG_SERIAL_CONSOLE + uart_tx_flush(); #endif #if CONFIG_USBDEBUG usbdebug_tx_flush(0); #endif } -#endif int do_printk(int msg_level, const char *fmt, ...) { @@ -69,7 +67,7 @@ int do_printk(int msg_level, const char *fmt, ...) i = vtxprintf(console_tx_byte, fmt, args); va_end(args); -// console_tx_flush(); + _console_tx_flush(); return i; } diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c index fd4374f..e8a47e5 100644 --- a/src/arch/armv7/stages.c +++ b/src/arch/armv7/stages.c @@ -38,8 +38,8 @@ void stage_entry(void) main(); } -void stage_exit(unsigned long addr) +void stage_exit(void *addr) { - __attribute__((noreturn)) void (*doit)(void) = (void *)addr; + __attribute__((noreturn)) void (*doit)(void) = addr; doit(); } diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 3c4777f..42d3282 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -14,6 +14,11 @@ romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c romstage-y += post.c romstage-y += die.c +bootblock-y += vtxprintf.c +bootblock-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +bootblock-y += post.c +bootblock-y += die.c + ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug_console.c diff --git a/src/cpu/samsung/exynos5-common/clk.h b/src/cpu/samsung/exynos5-common/clk.h index 0178f88..eb3b253 100644 --- a/src/cpu/samsung/exynos5-common/clk.h +++ b/src/cpu/samsung/exynos5-common/clk.h @@ -52,7 +52,7 @@ struct clk_bit_info { s8 prediv_bit; }; -/* FIXME(dhendrix) conflicts with stp-common/clk.h */ +/* FIXME(dhendrix) conflicts with s5p-common/clk.h */ #if 0 unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 1c6d716..e2033ff 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += clock_init.c bootblock-y += clock.c bootblock-y += pinmux.c +bootblock-y += power.c bootblock-y += soc.c bootblock-y += uart.c diff --git a/src/cpu/samsung/exynos5250/clock_init.h b/src/cpu/samsung/exynos5250/clock_init.h index 3757e7d..bb7f7e9 100644 --- a/src/cpu/samsung/exynos5250/clock_init.h +++ b/src/cpu/samsung/exynos5250/clock_init.h @@ -24,6 +24,7 @@ #ifndef __EXYNOS_CLOCK_INIT_H #define __EXYNOS_CLOCK_INIT_H +#include "dmc.h" /* These are the ratio's for configuring ARM clock */ struct arm_clk_ratios { diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 7c61655..2e0b253 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -24,6 +24,7 @@ #include <common.h> #include <arch/io.h> +#include <arch/hlt.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -62,7 +63,7 @@ void power_shutdown(void) clrbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); - hang(); + hlt(); } void power_enable_dp_phy(void) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index f3ee081..3126d7a 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -211,4 +211,7 @@ void uart_tx_byte(unsigned char data) { exynos5_uart_tx_byte(data); } + +void uart_tx_flush(void) { +} #endif diff --git a/src/cpu/samsung/s5p-common/s3c24x0_i2c.c b/src/cpu/samsung/s5p-common/s3c24x0_i2c.c index 2940b09..135becb 100644 --- a/src/cpu/samsung/s5p-common/s3c24x0_i2c.c +++ b/src/cpu/samsung/s5p-common/s3c24x0_i2c.c @@ -221,22 +221,12 @@ void board_i2c_init(const void *blob) /* * MULTI BUS I2C support */ -/* - * FIXME(dhendrix): not sure why this had to be guarded, but the code - * should probably go into an exynos5-specific .c file if it really is - * not generic. - */ -//#ifdef CONFIG_EXYNOS5 -static void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus) +void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus); +void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus) { exynos_pinmux_config(i2c->id, 0); - i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); } -//#else -//#error "should not be here" -//static void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus) {} -//#endif #ifdef CONFIG_I2C_MULTI_BUS int i2c_set_bus_num(unsigned int bus) diff --git a/src/drivers/maxim/max77686/Makefile.inc b/src/drivers/maxim/max77686/Makefile.inc index a5d7b90..097b291 100644 --- a/src/drivers/maxim/max77686/Makefile.inc +++ b/src/drivers/maxim/max77686/Makefile.inc @@ -17,5 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +bootblock-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c romstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c ramstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 130c354..0d1cb0c 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += romstage.c # parameters. Grep around for spl_get_machine_params for examples. romstage-y += smdk5250_spl.c ramstage-y += smdk5250_spl.c +bootblock-y += smdk5250_spl.c #ramstage-y += mainboard.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index fc0b208..64b12c6 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if CONFIG_EARLY_SERIAL_CONSOLE #include <types.h> #include <arch/io.h> #include <cbfs.h> @@ -27,553 +28,28 @@ #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/clock_init.h> +#include <src/cpu/samsung/exynos5250/power.h> #include <drivers/maxim/max77686/max77686.h> #define I2C0_BASE 0x12c60000 - -/* - * Max77686 parameters values - * see max77686.h for parameters details - */ -struct max77686_para max77686_param[] = {/*{vol_addr, vol_bitpos, - vol_bitmask, reg_enaddr, reg_enbitpos, reg_enbitmask, reg_enbiton, - reg_enbitoff, vol_min, vol_div}*/ - {/* PMIC_BUCK1 */ 0x11, 0x0, 0x3F, 0x10, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {/* PMIC_BUCK2 */ 0x14, 0x0, 0xFF, 0x12, 0x4, 0x3, 0x1, 0x0, 600, 12500}, - {/* PMIC_BUCK3 */ 0x1E, 0x0, 0xFF, 0x1C, 0x4, 0x3, 0x1, 0x0, 600, 12500}, - {/* PMIC_BUCK4 */ 0x28, 0x0, 0xFF, 0x26, 0x4, 0x3, 0x1, 0x0, 600, 12500}, - {/* PMIC_BUCK5 */ 0x31, 0x0, 0x3F, 0x30, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {/* PMIC_BUCK6 */ 0x33, 0x0, 0x3F, 0x32, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {/* PMIC_BUCK7 */ 0x35, 0x0, 0x3F, 0x34, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {/* PMIC_BUCK8 */ 0x37, 0x0, 0x3F, 0x36, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {/* PMIC_BUCK9 */ 0x39, 0x0, 0x3F, 0x38, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {/* PMIC_LDO1 */ 0x40, 0x0, 0x3F, 0x40, 0x6, 0x3, 0x3, 0x0, 800, 25000}, - {/* PMIC_LDO2 */ 0x41, 0x0, 0x3F, 0x41, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {/* PMIC_LDO3 */ 0x42, 0x0, 0x3F, 0x42, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO4 */ 0x43, 0x0, 0x3F, 0x43, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO5 */ 0x44, 0x0, 0x3F, 0x44, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO6 */ 0x45, 0x0, 0x3F, 0x45, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {/* PMIC_LDO7 */ 0x46, 0x0, 0x3F, 0x46, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {/* PMIC_LDO8 */ 0x47, 0x0, 0x3F, 0x47, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {/* PMIC_LDO9 */ 0x48, 0x0, 0x3F, 0x48, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO10 */ 0x49, 0x0, 0x3F, 0x49, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {/* PMIC_LDO11 */ 0x4A, 0x0, 0x3F, 0x4A, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {/* PMIC_LDO12 */ 0x4B, 0x0, 0x3F, 0x4B, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {/* PMIC_LDO13 */ 0x4C, 0x0, 0x3F, 0x4C, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO14 */ 0x4D, 0x0, 0x3F, 0x4D, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {/* PMIC_LDO15 */ 0x4E, 0x0, 0x3F, 0x4E, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {/* PMIC_LDO16 */ 0x4F, 0x0, 0x3F, 0x4F, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {/* PMIC_LDO17 */ 0x50, 0x0, 0x3F, 0x50, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO18 */ 0x51, 0x0, 0x3F, 0x51, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO19 */ 0x52, 0x0, 0x3F, 0x52, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO20 */ 0x53, 0x0, 0x3F, 0x53, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO21 */ 0x54, 0x0, 0x3F, 0x54, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO22 */ 0x55, 0x0, 0x3F, 0x55, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO23 */ 0x56, 0x0, 0x3F, 0x56, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO24 */ 0x57, 0x0, 0x3F, 0x57, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO25 */ 0x58, 0x0, 0x3F, 0x58, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_LDO26 */ 0x59, 0x0, 0x3F, 0x59, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {/* PMIC_EN32KHZ_CP */ 0x0, 0x0, 0x0, 0x7F, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0}, -}; - -/* - * Write a value to a register - * - * @param chip_addr i2c addr for max77686 - * @param reg reg number to write - * @param val value to be written - * - */ -static inline int max77686_i2c_write(unsigned char chip_addr, - unsigned int reg, unsigned char val) -{ - return i2c_write(chip_addr, reg, 1, &val, 1); -} - -/* - * Read a value from a register - * - * @param chip_addr i2c addr for max77686 - * @param reg reg number to write - * @param val value to be written - * - */ -static inline int max77686_i2c_read(unsigned char chip_addr, - unsigned int reg, unsigned char *val) -{ - return i2c_read(chip_addr, reg, 1, val, 1); -} - -/* Chip register numbers (not exported from this module) */ -enum { - REG_BBAT = 0x7e, - - /* Bits for BBAT */ - BBAT_BBCHOSTEN_MASK = 1 << 0, - BBAT_BBCVS_SHIFT = 3, - BBAT_BBCVS_MASK = 3 << BBAT_BBCVS_SHIFT, -}; - -int max77686_disable_backup_batt(void) -{ - unsigned char val; - int ret; - - //i2c_set_bus_num(0); - ret = max77686_i2c_read(MAX77686_I2C_ADDR, REG_BBAT, &val); - if (ret) { -// debug("max77686 i2c read failed\n"); - return ret; - } - - /* If we already have the correct values, exit */ - if ((val & (BBAT_BBCVS_MASK | BBAT_BBCHOSTEN_MASK)) == - BBAT_BBCVS_MASK) - return 0; - - /* First disable charging */ - val &= ~BBAT_BBCHOSTEN_MASK; - ret = max77686_i2c_write(MAX77686_I2C_ADDR, REG_BBAT, val); - if (ret) { - //debug("max77686 i2c write failed\n"); - return -1; - } - - /* Finally select 3.5V to minimize power consumption */ - val |= BBAT_BBCVS_MASK; - ret = max77686_i2c_write(MAX77686_I2C_ADDR, REG_BBAT, val); - if (ret) { - //debug("max77686 i2c write failed\n"); - return -1; - } - - return 0; -} - -static int max77686_enablereg(enum max77686_regnum reg, int enable) -{ - struct max77686_para *pmic; - unsigned char read_data; - int ret; - - pmic = &max77686_param[reg]; - - ret = max77686_i2c_read(MAX77686_I2C_ADDR, pmic->reg_enaddr, - &read_data); - if (ret != 0) { - //debug("max77686 i2c read failed.\n"); - return -1; - } - - if (enable == REG_DISABLE) { - clrbits_8(&read_data, - pmic->reg_enbitmask << pmic->reg_enbitpos); - } else { - clrsetbits_8(&read_data, - pmic->reg_enbitmask << pmic->reg_enbitpos, - pmic->reg_enbiton << pmic->reg_enbitpos); - } - - ret = max77686_i2c_write(MAX77686_I2C_ADDR, - pmic->reg_enaddr, read_data); - if (ret != 0) { - //debug("max77686 i2c write failed.\n"); - return -1; - } - - return 0; -} - -static int max77686_do_volsetting(enum max77686_regnum reg, unsigned int volt, - int enable, int volt_units) -{ - struct max77686_para *pmic; - unsigned char read_data; - int vol_level = 0; - int ret; - - pmic = &max77686_param[reg]; - - if (pmic->vol_addr == 0) { - //debug("not a voltage register.\n"); - return -1; - } - - ret = max77686_i2c_read(MAX77686_I2C_ADDR, pmic->vol_addr, &read_data); - if (ret != 0) { - //debug("max77686 i2c read failed.\n"); - return -1; - } - - if (volt_units == MAX77686_UV) - vol_level = volt - (u32)pmic->vol_min * 1000; - else - vol_level = (volt - (u32)pmic->vol_min) * 1000; - - if (vol_level < 0) { - //debug("Not a valid voltage level to set\n"); - return -1; - } - vol_level /= (u32)pmic->vol_div; - - clrsetbits_8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos, - vol_level << pmic->vol_bitpos); - - ret = max77686_i2c_write(MAX77686_I2C_ADDR, pmic->vol_addr, read_data); - if (ret != 0) { - //debug("max77686 i2c write failed.\n"); - return -1; - } - - ret = max77686_enablereg(reg, enable); - if (ret != 0) { - //debug("Failed to enable buck/ldo.\n"); - return -1; - } - return 0; -} - -int max77686_volsetting(enum max77686_regnum reg, unsigned int volt, - int enable, int volt_units) -{ -// int old_bus = i2c_get_bus_num(); - int ret; - -// i2c_set_bus_num(0); - ret = max77686_do_volsetting(reg, volt, enable, volt_units); -// i2c_set_bus_num(old_bus); - return ret; -} - -/* power_init() stuff */ -static void power_init(void) -{ - max77686_disable_backup_batt(); - -#if 0 - /* FIXME: for debugging... */ - volatile unsigned long *addr = (unsigned long *)0x1004330c; - *addr |= 0x100; - while (1); #endif - max77686_volsetting(PMIC_BUCK2, CONFIG_VDD_ARM_MV, - REG_ENABLE, MAX77686_MV); - max77686_volsetting(PMIC_BUCK3, CONFIG_VDD_INT_UV, - REG_ENABLE, MAX77686_UV); - max77686_volsetting(PMIC_BUCK1, CONFIG_VDD_MIF_MV, - REG_ENABLE, MAX77686_MV); - max77686_volsetting(PMIC_BUCK4, CONFIG_VDD_G3D_MV, - REG_ENABLE, MAX77686_MV); - max77686_volsetting(PMIC_LDO2, CONFIG_VDD_LDO2_MV, - REG_ENABLE, MAX77686_MV); - max77686_volsetting(PMIC_LDO3, CONFIG_VDD_LDO3_MV, - REG_ENABLE, MAX77686_MV); - max77686_volsetting(PMIC_LDO5, CONFIG_VDD_LDO5_MV, - REG_ENABLE, MAX77686_MV); - max77686_volsetting(PMIC_LDO10, CONFIG_VDD_LDO10_MV, - REG_ENABLE, MAX77686_MV); -} - -#include <console/vtxprintf.h> -#include <string.h> -#define ZEROPAD 1 /* pad with zero */ -#define SIGN 2 /* unsigned/signed long */ -#define PLUS 4 /* show plus */ -#define SPACE 8 /* space if plus */ -#define LEFT 16 /* left justified */ -#define SPECIAL 32 /* 0x */ -#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ -/* haha, don't need ctype.c */ -#define isdigit(c) ((c) >= '0' && (c) <= '9') -#define is_digit isdigit -#define isxdigit(c) (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'f') || ((c) >= 'A' && (c) <= 'F')) - -static int skip_atoi(const char **s) -{ - int i=0; - - while (is_digit(**s)) - i = i*10 + *((*s)++) - '0'; - return i; -} - -#include <div64.h> -static int number(void (*tx_byte)(unsigned char byte), - unsigned long long num, int base, int size, int precision, int type) -{ - char c,sign,tmp[66]; - const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; - int i; - int count = 0; - - if (type & LARGE) - digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; - if (type & LEFT) - type &= ~ZEROPAD; - if (base < 2 || base > 36) - return 0; - c = (type & ZEROPAD) ? '0' : ' '; - sign = 0; - if (type & SIGN) { - if ((signed long long)num < 0) { - sign = '-'; - num = -num; - size--; - } else if (type & PLUS) { - sign = '+'; - size--; - } else if (type & SPACE) { - sign = ' '; - size--; - } - } - if (type & SPECIAL) { - if (base == 16) - size -= 2; - else if (base == 8) - size--; - } - i = 0; - if (num == 0) { - tmp[i++]='0'; - } else while (num != 0) { - /* FIXME: do_div was broken */ -// tmp[i++] = digits[do_div(num,base)]; - tmp[i++] = digits[num & 0xf]; - num = num >> 4; - } - if (i > precision) - precision = i; - size -= precision; - if (!(type&(ZEROPAD+LEFT))) - while(size-->0) - tx_byte(' '), count++; - if (sign) - tx_byte(sign), count++; - if (type & SPECIAL) { - if (base==8) - tx_byte('0'), count++; - else if (base==16) { - tx_byte('0'), count++; - tx_byte(digits[33]), count++; - } - } - if (!(type & LEFT)) - while (size-- > 0) - tx_byte(c), count++; - while (i < precision--) - tx_byte('0'), count++; - while (i-- > 0) - tx_byte(tmp[i]), count++; - while (size-- > 0) - tx_byte(' '), count++; - return count; -} - -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args) -{ - int len; - unsigned long long num; - int i, base; - const char *s; - - int flags; /* flags to number() */ - - int field_width; /* width of output field */ - int precision; /* min. # of digits for integers; max - number of chars for from string */ - int qualifier; /* 'h', 'l', or 'L' for integer fields */ - - int count; - - for (count=0; *fmt ; ++fmt) { - if (*fmt != '%') { - tx_byte(*fmt), count++; - continue; - } - - /* process flags */ - flags = 0; -repeat: - ++fmt; /* this also skips first '%' */ - switch (*fmt) { - case '-': flags |= LEFT; goto repeat; - case '+': flags |= PLUS; goto repeat; - case ' ': flags |= SPACE; goto repeat; - case '#': flags |= SPECIAL; goto repeat; - case '0': flags |= ZEROPAD; goto repeat; - } - - /* get field width */ - field_width = -1; - if (is_digit(*fmt)) - field_width = skip_atoi(&fmt); - else if (*fmt == '*') { - ++fmt; - /* it's the next argument */ - field_width = va_arg(args, int); - if (field_width < 0) { - field_width = -field_width; - flags |= LEFT; - } - } - - /* get the precision */ - precision = -1; - if (*fmt == '.') { - ++fmt; - if (is_digit(*fmt)) - precision = skip_atoi(&fmt); - else if (*fmt == '*') { - ++fmt; - /* it's the next argument */ - precision = va_arg(args, int); - } - if (precision < 0) - precision = 0; - } - - /* get the conversion qualifier */ - qualifier = -1; - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z') { - qualifier = *fmt; - ++fmt; - if (*fmt == 'l') { - qualifier = 'L'; - ++fmt; - } - } - - /* default base */ - base = 10; - - switch (*fmt) { - case 'c': - if (!(flags & LEFT)) - while (--field_width > 0) - tx_byte(' '), count++; - tx_byte((unsigned char) va_arg(args, int)), count++; - while (--field_width > 0) - tx_byte(' '), count++; - continue; - - case 's': - s = va_arg(args, char *); - if (!s) - s = "<NULL>"; - - len = strnlen(s, precision); - - if (!(flags & LEFT)) - while (len < field_width--) - tx_byte(' '), count++; - for (i = 0; i < len; ++i) - tx_byte(*s++), count++; - while (len < field_width--) - tx_byte(' '), count++; - continue; - - case 'p': - if (field_width == -1) { - field_width = 2*sizeof(void *); - flags |= ZEROPAD; - } - count += number(tx_byte, - (unsigned long) va_arg(args, void *), 16, - field_width, precision, flags); - continue; - - case 'n': - if (qualifier == 'L') { - long long *ip = va_arg(args, long long *); - *ip = count; - } else if (qualifier == 'l') { - long * ip = va_arg(args, long *); - *ip = count; - } else { - int * ip = va_arg(args, int *); - *ip = count; - } - continue; - - case '%': - tx_byte('%'), count++; - continue; - - /* integer number formats - set up the flags and "break" */ - case 'o': - base = 8; - break; - - case 'X': - flags |= LARGE; - case 'x': - base = 16; - break; - - case 'd': - case 'i': - flags |= SIGN; - case 'u': - break; - - default: - tx_byte('%'), count++; - if (*fmt) - tx_byte(*fmt), count++; - else - --fmt; - continue; - } - if (qualifier == 'L') { - num = va_arg(args, unsigned long long); - } else if (qualifier == 'l') { - num = va_arg(args, unsigned long); - } else if (qualifier == 'z') { - num = va_arg(args, size_t); - } else if (qualifier == 'h') { - num = (unsigned short) va_arg(args, int); - if (flags & SIGN) - num = (short) num; - } else if (flags & SIGN) { - num = va_arg(args, int); - } else { - num = va_arg(args, unsigned int); - } - count += number(tx_byte, num, base, field_width, precision, flags); - } - return count; -} - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - va_start(args, fmt); - i = vtxprintf(uart_tx_byte, fmt, args); - va_end(args); - - return i; -} - void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { struct mem_timings *mem; struct arm_clk_ratios *arm_ratios; - /* FIXME: we should not need UART in bootblock, this is only - done for testing purposes */ i2c_set_early_reg(I2C0_BASE); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); power_init(); mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); + +#if CONFIG_EARLY_SERIAL_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); uart_init(); - printk(BIOS_INFO, "%s: UART initialized\n", __func__); - printk(BIOS_INFO, "%s: finished\n", __func__); + printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); +#endif } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 03fd1be..700fe0d 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -34,15 +34,12 @@ void main(void) { - struct cbfs_media cbfs; -// i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -// power_init(); -// clock_init(); -// exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - console_init(); - printk(BIOS_INFO, "hello from romstage\n"); struct mem_timings *mem; int ret; + void *entry; + + console_init(); + printk(BIOS_INFO, "hello from romstage\n"); mem = get_mem_timings(); if (!mem) { @@ -63,51 +60,9 @@ void main(void) } printk(BIOS_INFO, "ddr3_init done\n"); - /* wow, did it work? */ - int i; - u32 *c = (void *)CONFIG_RAMBASE; - -// mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); -// printk(BIOS_INFO, "mmu_setup done\n"); - for(i = 0; i < 16384; i++) - c[i] = i+32768; - for(i = 0; i < 16384; i++) - if (c[i] != i+32768) - printk(BIOS_SPEW, "BADc[%02x]: %02x,", i, c[i]); - for(i = 0; i < 1048576; i++) - c[i] = 0; - - ret = init_default_cbfs_media(&cbfs); - if (ret){ - printk(BIOS_ERR, "init_default_cbfs_media returned %d: HALT\n", - ret); - while (1); - } - - struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(&cbfs, "fallback/coreboot_ram", - CBFS_TYPE_STAGE); - printk(BIOS_ERR, "Stage: %p\n", stage); - printk(BIOS_ERR, "loading stage %s @ 0x%x (0x%x bytes),entry @ 0x%p\n", - "ram stage", - (uint32_t) stage->load, stage->memlen, - (void *)(u32)stage->entry); - -#if 0 - /* for reference and testing ... we should be able to remove soon */ -// c = (void *)(u32)(stage->load + stage->len); - c = (void *)(u32)(stage->load); - printk(BIOS_ERR, "memzero 0x%x words starting at %p\n", - (stage->memlen /*- stage->len*/)/4, c); - for(i = 0; i < (stage->memlen /*- stage->len*/)/4; i++){ - printk(BIOS_INFO, "%p, ", &c[i]); - c[i] = 0; - } -#endif - void *entry = cbfs_load_stage(&cbfs, "fallback/coreboot_ram"); - printk(BIOS_INFO, "entry is %p\n", entry); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); - printk(BIOS_INFO, "sayonara, romstage!\n"); - stage_exit((unsigned long)entry); + stage_exit(entry); }

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New patch to review for coreboot: 69d861a bootblock: Reduce register load
by Patrick Georgi 06 Feb '13

06 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2296 -gerrit commit 69d861a6fbb689193cfcbafef8597fc655315df3 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Feb 6 11:37:08 2013 +0100 bootblock: Reduce register load The common part of the bootblock resets the nvram data if it's found to be invalid. Since that code is compiled with romcc in i386 mode, there's a shortage on registers. Try to reduce the strain by doing things smarter: cmos_write_inner is the same as cmos_write, just that it doesn't check if the RTC is disabled. Since we just disabled it before, we can assume that it is so. Change-Id: Ic85eb2a5df949d1c1aff654bc1b40d6f2ff71756 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/include/bootblock_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index c24b5b0..11fb230 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -39,7 +39,7 @@ static void sanitize_cmos(void) int i; cmos_disable_rtc(); for (i = 14; i < 128; i++) { - cmos_write(cmos_default[i], i); + cmos_write_inner(cmos_default[i], i); } cmos_enable_rtc(); }

1 0

Patch set updated for coreboot: d45ad50 crossgcc: Save the script itself when cross build is over.
by Zheng Bao 06 Feb '13

06 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2247 -gerrit commit d45ad503db3f03b16b3ab56fc44aed410396db9b Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Wed Feb 6 18:04:40 2013 +0800 crossgcc: Save the script itself when cross build is over. In case that the new toolchains don't work well, we can trace back and reproduce the old tools by checking the xgcc folder. It is useful when my team members need to get my old toolchains on their own host machines. Change-Id: I54e4bc6afcfbbf622165af6eae27bbb6efc2e8cc Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/crossgcc/buildgcc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c69e7cd..eaff24d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -595,6 +595,9 @@ test -r $IASL_DIR/generate/unix/.failed && printf "${RED}failed${NC}\n" || \ test -r $IASL_DIR/generate/unix/.failed && exit 1 fi +rm -f $DESTDIR$TARGETDIR/$0.commit.* +cp $0 $DESTDIR$TARGETDIR/"$0.commit.`git describe`" + if [ $SAVETEMPS -eq 0 ]; then printf "Cleaning up... " rm -rf ${GMP_DIR} build-gmp

1 0

Patch merged into coreboot/master: c5ff648 armv7: Prevent CBFS data overlapping bootblock.
by gerrit＠coreboot.org 06 Feb '13

06 Feb '13

the following patch was just integrated into master: commit c5ff6487e65294aac4dccbf6b2a56ac518f982e2 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 12:41:49 2013 +0800 armv7: Prevent CBFS data overlapping bootblock. For arm/snow, current bootblock is larger than previously assigned CBFS offset and will fail to boot. To prevent this happening again in future, cbfstool now checks if CBFS will overlap bootblock. A sample error message: E: Bootblock (0x0+0x71d4) overlap CBFS data (0x5000) E: Failed to create build/coreboot.pre1.tmp. arm/snow offset is also enlarged and moved to Kconfig variable. Change-Id: I4556aef27ff716556040312ae8ccb78078abc82d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2295 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Feb 6 06:05:43 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Wed Feb 6 10:53:18 2013, giving +2 See http://review.coreboot.org/2295 for details. -gerrit

1 0

Patch merged into coreboot/master: 966e2db cbfs: Revise debug messages.
by gerrit＠coreboot.org 06 Feb '13

06 Feb '13

the following patch was just integrated into master: commit 966e2dbb6537e9368514dfb3dfba24a8345c49bf Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 12:25:27 2013 +0800 cbfs: Revise debug messages. Some variables are using incorrect data type in debug messages. Also corrects a typo (extra 'x'). Change-Id: Ia3014ea018f8c1e4733c54a7d9ee196d0437cfbb Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2294 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Feb 6 05:53:08 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Wed Feb 6 10:52:12 2013, giving +2 See http://review.coreboot.org/2294 for details. -gerrit

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coreboot February 2013