coreboot February 2013

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[PATCH] Kconfig: string option doesn't work properly inside choice section
by Jens Rottmann 06 Feb '13

06 Feb '13

Kconfig: string option doesn't work properly inside choice section At least not in menuconfig. Move it after the endchoice. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- Hi everyone (in case any still remember me, last time was > 2 years ago), I prepared / am preparing support for 2 of our new boards (both AMD Fusion platform, mostly differ in form factor), which I'd like to upstream into the official repository. Then I'll likely disappear again for years, sorry. :-( My boards are based on AMD Persimmon and Inagua. When trying to compare the two I noticed lots of differences, most of which are whitespace. It looks like one is a copy of the other, but afterwards someone did a cleanup of Inagua only? As both are AMD reference designs, I think I have no choice but first try to get them closer to each other before (re)basing my code on it. But first of all this little bugfix here. Best regards and thanks, Jens Rottmann --- coreboot-f04e68e/src/cpu/Kconfig +++ coreboot/src/cpu/Kconfig @@ -105,13 +105,6 @@ If unsure, select "Generate from tree" -config CPU_MICROCODE_FILE - string "Path and filename of CPU microcode" - depends on CPU_MICROCODE_CBFS_EXTERNAL - default "cpu_microcode.bin" - help - The path and filename of the file containing the CPU microcode. - config CPU_MICROCODE_CBFS_NONE bool "Do not include microcode updates" help @@ -155,3 +148,10 @@ selecting this option. endchoice + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. _

2 1

Patch set updated for coreboot: 48e4e3c AMD Fam14 - Fix warnings
by Martin Roth 06 Feb '13

06 Feb '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2293 -gerrit commit 48e4e3c4b99299ca681f5ced6efb2a04c7830368 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Feb 5 21:06:21 2013 -0700 AMD Fam14 - Fix warnings Added casts and a couple of #ifdefs to fix the warnings in the vendorcode/amd/agesa/f14 codebase. This will allow us to re-enable 'all warnings being treated as errors' in boards such as Persimmon that are using this code. That change will follow. These are the warnings that are fixed by this patch: src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToTempRamAtPost': src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:219:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToMainRamAtPost': src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:372:30: warning: comparison between pointer and integer [enabled by default] src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:381:33: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c: In function 'ApUtilSetupIdtForHlt': src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:863:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:872:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c: In function 'LoadMicrocode': src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c:211:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapManagerInit': src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:167:52: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:183:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress': src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:669:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:676:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:683:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:684:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:687:23: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:691:21: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:696:3: warning: return makes pointer from integer without a cast [enabled by default] In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0, from src/northbridge/amd/agesa/family14/northbridge.c:36: src/vendorcode/amd/agesa/f14/AGESA.h:1132:0: warning: "TOP_MEM" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0, from src/northbridge/amd/agesa/family14/northbridge.c:36: src/vendorcode/amd/agesa/f14/AGESA.h:1133:0: warning: "TOP_MEM2" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition Verified on persimmon. Change-Id: I1671b191c72dfc1d63ada41126ae3418bc8f86ae Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/vendorcode/amd/agesa/f14/AGESA.h | 4 ++++ .../amd/agesa/f14/Legacy/Proc/hobTransfer.c | 6 +++--- .../amd/agesa/f14/Proc/CPU/cpuApicUtilities.c | 4 ++-- .../amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c | 19 ++++++++++--------- 5 files changed, 20 insertions(+), 15 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 511be69..5eaa638 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -1129,8 +1129,12 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 +#ifndef TOP_MEM #define TOP_MEM 0xC001001A +#endif +#ifndef TOP_MEM2 #define TOP_MEM2 0xC001001D +#endif #define HWCR 0xC0010015 #define NB_CFG 0xC001001F diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c index d3987fb..bb23204 100644 --- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c @@ -216,7 +216,7 @@ CopyHeapToTempRamAtPost ( HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - BaseAddressInTempMem = (UINT8 *) (UserOptions.CfgHeapDramAddress); + BaseAddressInTempMem = (UINT8 *) (intptr_t) (UserOptions.CfgHeapDramAddress); HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); @@ -369,7 +369,7 @@ CopyHeapToMainRamAtPost ( HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; } // if address of heap in temp memory is above 1M, then we must used one variable MTRR. - if (StdHeader->HeapBasePtr >= 0x100000) { + if (StdHeader->HeapBasePtr >= (void *) 0x100000) { // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); @@ -378,7 +378,7 @@ CopyHeapToMainRamAtPost ( HeapRamVariableMtrr--) { LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == ((UINT64)(StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) && + if ((VariableMtrrBase == ((UINT64) (intptr_t) (StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) && (VariableMtrrMask == (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { break; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c index 40c395d..0b9b9c6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c @@ -860,7 +860,7 @@ ApUtilSetupIdtForHlt ( DescSize = 8; } - HandlerOffset = (UINT64)&NmiHandler; + HandlerOffset = (UINT64) (intptr_t) &NmiHandler; NmiIdtDescPtr->OffsetLo = (UINT16) (HandlerOffset & 0xFFFF); NmiIdtDescPtr->OffsetHi = (UINT16) ((HandlerOffset >> 16) & 0xFFFF); GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader); @@ -869,7 +869,7 @@ ApUtilSetupIdtForHlt ( NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32); NmiIdtDescPtr->Rsvd64 = 0; IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1); - IdtInfo.Base = (UINT64) NmiIdtDescPtr - (DescSize * 2); + IdtInfo.Base = (UINT64) (intptr_t) NmiIdtDescPtr - (DescSize * 2); SetIdtr (&IdtInfo , StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c index 4116a6e..bc15447 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c @@ -208,7 +208,7 @@ LoadMicrocode ( PATCH_LOADER PatchLoaderMsr; // Load microcode patch into CPU - PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr; + PatchLoaderMsr.RawData = (UINT64) (intptr_t) MicrocodePatchPtr; PatchLoaderMsr.BitFields.SBZ = 0; LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c index 57e1838..f6b409f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c @@ -164,7 +164,8 @@ HeapManagerInit ( LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) { LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); - if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { + if (((UINT64) (intptr_t) MsrData & CacheInfoPtr->HeapBaseMask) == + ((UINT64) (intptr_t) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) { // This is not a bug, there are multiple premem basic entry points, // and each will call heap init to make sure create struct will succeed. @@ -180,7 +181,7 @@ HeapManagerInit ( } // Set variable MTRR base and mask - MsrData = ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); + MsrData = ((UINT64) (intptr_t)HeapBufferPtr & CacheInfoPtr->HeapBaseMask); MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK; MsrData |= 0x06; @@ -666,34 +667,34 @@ VOID // Firstly, we try to see if heap is in cache BaseAddress = HeapGetCurrentBase (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; + HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) && (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) && (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) { // Secondly, we try to see if heap is in temp memory BaseAddress = UserOptions.CfgHeapDramAddress; - HeapManager = (HEAP_MANAGER *) BaseAddress; + HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { // Thirdly, we try to see if heap in main memory // by locating with external buffer manager (IBV) AgesaBuffer.StdHeader = *StdHeader; AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) { - BaseAddress = (UINT64) AgesaBuffer.BufferPointer; - HeapManager = (HEAP_MANAGER *) BaseAddress; + BaseAddress = (UINT64) (intptr_t) AgesaBuffer.BufferPointer; + HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { // No valid heap signature ever found, return a NULL pointer - BaseAddress = NULL; + BaseAddress = (UINT64) (intptr_t) NULL; } } else { // No heap buffer is allocated by external manager (IBV), return a NULL pointer - BaseAddress = NULL; + BaseAddress = (UINT64) (intptr_t) NULL; } } } - return BaseAddress; + return (void *) (intptr_t) BaseAddress; } /*---------------------------------------------------------------------------------------

1 0

Patch set updated for coreboot: 880f027 armv7: Clean up: remove deprecated SPL.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2297 -gerrit commit 880f02787909154d735f8a838576d00ac12348df Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 17:48:20 2013 +0800 armv7: Clean up: remove deprecated SPL. "SPL" from U-Boot is deprecated by bootblock in coreboot/arm, so we don't need it anymore. Change-Id: Id16877075d0b870839a10160073ad70777a2af0a Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Kconfig | 4 - src/arch/armv7/lib/eabi_compat.c | 5 +- src/cpu/samsung/exynos5-common/spl.h | 94 ------- src/cpu/samsung/exynos5-common/spl_boot.c | 447 ------------------------------ src/cpu/samsung/exynos5250/Kconfig | 4 - src/cpu/samsung/exynos5250/clk.h | 3 - src/cpu/samsung/exynos5250/clock_init.c | 2 - src/cpu/samsung/exynos5250/dmc_common.c | 2 +- src/cpu/samsung/exynos5250/power.c | 1 - src/cpu/samsung/s5p-common/cpu_info.c | 2 +- src/cpu/samsung/s5p-common/s5p_gpio.c | 2 - src/cpu/samsung/s5p-common/timer.c | 3 +- src/mainboard/google/snow/Makefile.inc | 9 - src/mainboard/google/snow/smdk5250_spl.c | 89 ------ 14 files changed, 5 insertions(+), 662 deletions(-) diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 65de2d5..488ca97 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -1,9 +1,5 @@ menu "Architecture (armv7)" -config SPL_BUILD - bool "Build second-phase bootloader (SPL)" - default y - config EABI_COMPAT bool "Toolchain is EABI compatible" default n diff --git a/src/arch/armv7/lib/eabi_compat.c b/src/arch/armv7/lib/eabi_compat.c index 5f59892..2772de6 100644 --- a/src/arch/armv7/lib/eabi_compat.c +++ b/src/arch/armv7/lib/eabi_compat.c @@ -10,14 +10,13 @@ */ #include <common.h> +#include <console/console.h> /* FIXME(dhendrix): prototypes added for assembler */ int raise (int signum); int raise (int signum) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - printf("raise: Signal # %d caught\n", signum); -#endif + printk(BIOS_CRIT, "raise: Signal # %d caught\n", signum); return 0; } diff --git a/src/cpu/samsung/exynos5-common/spl.h b/src/cpu/samsung/exynos5-common/spl.h deleted file mode 100644 index afa9a8e..0000000 --- a/src/cpu/samsung/exynos5-common/spl.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_EXYNOS_SPL_H__ -#define __ASM_ARCH_EXYNOS_SPL_H__ - -#include <cpu/samsung/exynos5-common/cpu.h> -/* FIXME(dhendrix): non-common header included by a common header... */ -#include <cpu/samsung/exynos5250/dmc.h> - -/* Parameters of early board initialization in SPL */ -struct spl_machine_param { - /* Add fields as and when required */ - u32 signature; - u32 version; /* Version number */ - u32 size; /* Size of block */ - /** - * Parameters we expect, in order, terminated with \0. Each parameter - * is a single character representing one 32-bit word in this - * structure. - * - * Valid characters in this string are: - * - * Code Name - * v mem_iv_size - * m mem_type - * u uboot_size - * b boot_source - * f frequency_mhz (memory frequency in MHz) - * a ARM clock frequency in MHz - * s serial base address - * i i2c base address for early access (meant for PMIC) - * r board rev GPIO numbers used to read board revision - * (lower halfword=bit 0, upper=bit 1) - * M Memory Manufacturer name - * w Bad Wake GPIO number - * \0 termination - */ - char params[12]; /* Length must be word-aligned */ - u32 mem_iv_size; /* Memory channel interleaving size */ - enum ddr_mode mem_type; /* Type of on-board memory */ - /* - * U-boot size - The iROM mmc copy function used by the SPL takes a - * block count paramter to describe the u-boot size unlike the spi - * boot copy function which just uses the u-boot size directly. Align - * the u-boot size to block size (512 bytes) when populating the SPL - * table only for mmc boot. - */ - u32 uboot_size; - enum boot_mode boot_source; /* Boot device */ - unsigned frequency_mhz; /* Frequency of memory in MHz */ - unsigned arm_freq_mhz; /* ARM Frequency in MHz */ - u32 serial_base; /* Serial base address */ - u32 i2c_base; /* i2c base address */ - u32 board_rev_gpios; /* Board revision GPIOs */ - enum mem_manuf mem_manuf; /* Memory Manufacturer */ - u32 bad_wake_gpio; /* If high at wake time disallow wake */ -} __attribute__((__packed__)); - -/** - * Validate signature and return a pointer to the parameter table. If the - * signature is invalid, call panic() and never return. - * - * @return pointer to the parameter table if signature matched or never return. - */ -struct spl_machine_param *spl_get_machine_params(void); - -/* - * Initialize the timer and serial driver in SPL u-boot. - * Besides the serial driver, it also setup the minimal set of its dependency, - * like gd struct, pinmux, and serial. - */ -void spl_early_init(void); - -#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */ diff --git a/src/cpu/samsung/exynos5-common/spl_boot.c b/src/cpu/samsung/exynos5-common/spl_boot.c deleted file mode 100644 index ddf6937..0000000 --- a/src/cpu/samsung/exynos5-common/spl_boot.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* FIXME(dhendrix): pulled in a lot of extra crap such as partition and string - libs*/ -#include <assert.h> -#include <common.h> -#include <stdlib.h> -#include <string.h> - -#include <console/console.h> -#include <console/loglevel.h> -//#include <asm/arch/board.h> - -#include <config.h> -#include <spi.h> -#if 0 -#include <asm/arch/clock.h> -#include <asm/arch-exynos/spi.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/power.h> -#endif -#include <arch/hlt.h> -#include <cpu/samsung/exynos5250/clk.h> -#include <cpu/samsung/exynos5250/cpu.h> -#include <cpu/samsung/exynos5250/periph.h> -#include <cpu/samsung/exynos5250/pinmux.h> -#include <cpu/samsung/exynos5250/power.h> -#include <cpu/samsung/exynos5250/spi.h> - -#include <cpu/samsung/exynos5-common/cpu.h> -#include <cpu/samsung/exynos5-common/exynos5-common.h> - -//#include <asm/system.h> -#include <system.h> - -#include <arch/io.h> - -#define OM_STAT (0x1f << 1) - -/** - * Copy data from SD or MMC device to RAM. - * - * @param offset Block offset of the data - * @param nblock Number of blocks - * @param dst Destination address - * @return 1 = True or 0 = False - */ -typedef u32 (*mmc_copy_func_t)(u32 offset, u32 nblock, u32 dst); - -/** - * Copy data from SPI flash to RAM. - * - * @param offset Block offset of the data - * @param nblock Number of blocks - * @param dst Destination address - * @return 1 = True or 0 = False - */ -typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); - - -/** - * Copy data through USB. - * - * @return 1 = True or 0 = False - */ -typedef u32 (*usb_copy_func_t)(void); - -/* - * Set/clear program flow prediction and return the previous state. - */ -static int config_branch_prediction(int set_cr_z) -{ - unsigned int cr; - - /* System Control Register: 11th bit Z Branch prediction enable */ - cr = get_cr(); - set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); - - return cr & CR_Z; -} - -#if 0 -static void spi_rx_tx(struct exynos_spi *regs, int todo, - void *dinp, void const *doutp, int i) -{ - uint *rxp = (uint *)(dinp + (i * (32 * 1024))); - int rx_lvl, tx_lvl; - uint out_bytes, in_bytes; - - out_bytes = in_bytes = todo; - setbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); - writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt); - - while (in_bytes) { - uint32_t spi_sts; - int temp; - - spi_sts = readl(&regs->spi_sts); - rx_lvl = ((spi_sts >> 15) & 0x7f); - tx_lvl = ((spi_sts >> 6) & 0x7f); - while (tx_lvl < 32 && out_bytes) { - temp = 0xffffffff; - writel(temp, &regs->tx_data); - out_bytes -= 4; - tx_lvl += 4; - } - while (rx_lvl >= 4 && in_bytes) { - temp = readl(&regs->rx_data); - if (rxp) - *rxp++ = temp; - in_bytes -= 4; - rx_lvl -= 4; - } - } -} -#endif - -/* FIXME(dhendrix): feels like exynos_spi_copy should go somewhere else... */ -#if 0 -/** - * Copy uboot from spi flash to RAM - * - * @parma uboot_size size of u-boot to copy - */ -static void exynos_spi_copy(unsigned int uboot_size) -{ - int upto, todo; - int i; -// struct exynos_spi *regs = (struct exynos_spi *)samsung_get_base_spi1(); - struct exynos_spi *regs = (struct exynos_spi *)0x12d30000; - - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ - /* set the spi1 GPIO */ - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); - - /* set pktcnt and enable it */ - writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt); - /* set FB_CLK_SEL */ - writel(SPI_FB_DELAY_180, &regs->fb_clk); - /* set CH_WIDTH and BUS_WIDTH as word */ - setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | - SPI_MODE_BUS_WIDTH_WORD); - clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ - - /* clear rx and tx channel if set priveously */ - clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - - setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN | - SPI_RX_BYTE_SWAP | - SPI_RX_HWORD_SWAP); - - /* do a soft reset */ - setbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); - - /* now set rx and tx channel ON */ - setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); - clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ - - /* Send read instruction (0x3h) followed by a 24 bit addr */ - writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data); - - /* waiting for TX done */ - while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)); - - for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { - todo = MIN(uboot_size - upto, (1 << 15)); - spi_rx_tx(regs, todo, (void *)(CONFIG_SYS_TEXT_BASE), - (void *)(SPI_FLASH_UBOOT_POS), i); - } - - setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ - - /* - * Let put controller mode to BYTE as - * SPI driver does not support WORD mode yet - */ - clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | - SPI_MODE_BUS_WIDTH_WORD); - writel(0, &regs->swap_cfg); - - /* - * Flush spi tx, rx fifos and reset the SPI controller - * and clear rx/tx channel - */ - clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); -} -#endif - -/* Copy U-Boot image to RAM */ -static void copy_uboot_to_ram(void) -{ - unsigned int sec_boot_check; - unsigned int uboot_size = CONFIG_COREBOOT_ROMSIZE_KB_4096; - int is_cr_z_set; - enum boot_mode boot_mode = BOOT_MODE_OM; - mmc_copy_func_t mmc_copy; - - usb_copy_func_t usb_copy; - -#if 0 - uboot_size = exynos_get_uboot_size(); - boot_mode = exynos_get_boot_device(); -#endif - - if (boot_mode == BOOT_MODE_OM) { - /* Read iRAM location to check for secondary USB boot mode */ - sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); - if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) - boot_mode = BOOT_MODE_USB; - } - debug("U-Boot size %u\n", uboot_size); - - if (boot_mode == BOOT_MODE_OM) - boot_mode = readl(EXYNOS_POWER_BASE) & OM_STAT; - - switch (boot_mode) { -#if defined(CONFIG_EXYNOS_SPI_BOOT) - case BOOT_MODE_SERIAL: - /* let us our own function to copy u-boot from SF */ - exynos_spi_copy(uboot_size); - break; -#endif - case BOOT_MODE_MMC: - mmc_copy = *(mmc_copy_func_t *)EXYNOS_COPY_MMC_FNPTR_ADDR; - assert(!(uboot_size & 511)); - mmc_copy(BL2_START_OFFSET, uboot_size / 512, - CONFIG_SYS_TEXT_BASE); - break; - case BOOT_MODE_USB: - /* - * iROM needs program flow prediction to be disabled - * before copy from USB device to RAM - */ - is_cr_z_set = config_branch_prediction(0); - usb_copy = *(usb_copy_func_t *) - EXYNOS_COPY_USB_FNPTR_ADDR; - usb_copy(); - config_branch_prediction(is_cr_z_set); - break; - default: - printk(BIOS_ERR, "Invalid boot mode selection\n"); - hlt(); - break; - } - debug("U-Boot copied\n"); -} - -#if 0 -/** - * Set up the U-Boot global_data pointer - * - * This sets the address of the global data, and sets up basic values. - * - * @param gdp Value to give to gd - */ -static void setup_global_data(gd_t *gdp) -{ - gd = gdp; - memzero((void *)gd, sizeof(gd_t)); - gd->flags |= GD_FLG_RELOC; - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; -} -#endif - -#if 0 -/* Tell the loaded U-Boot that it was loaded from SPL */ -static void exynos5_set_spl_marker(void) -{ - uint32_t *marker = (uint32_t *)CONFIG_SPL_MARKER; - - *marker = EXYNOS5_SPL_MARKER; -} -#endif - -/* Board-specific call to see if wakeup is allowed. */ -static int __def_board_wakeup_permitted(void) -{ - return 1; -} -int board_wakeup_permitted(void) - __attribute__((weak, alias("__def_board_wakeup_permitted"))); - -void board_init_f(void) -{ - /* - * The gd struct is only needed for serial initialization. Since this - * function is called in SPL u-boot. We store the gd struct in the - * stack instead of the default memory region which may not be - * initialized. - */ -// __attribute__((aligned(8))) gd_t local_gd; -// __attribute__((noreturn)) void (*uboot)(void); - -// exynos5_set_spl_marker(); -// setup_global_data(&local_gd); - - /* - * Init subsystems, and resume if required. For a normal boot this - * will set up the UART and display a message. - */ - if (lowlevel_init_subsystems()) { - if (!board_wakeup_permitted()) - power_reset(); - power_exit_wakeup(); - } - -// printk(BIOS_INFO, "\n\nU-Boot SPL, board rev %u\n", board_get_revision()); - - copy_uboot_to_ram(); - /* Jump to U-Boot image */ -// uboot = (void *)CONFIG_SYS_TEXT_BASE; -// uboot(); - /* Never returns Here */ -// printk(BIOS_ERR, "%s: u-boot jump failed", __func__); - printk(BIOS_INFO, "%s: we should not be here...", __func__); - hlt(); -} - -//void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} - -#if 0 -/* - * The following functions are required when linking console library to SPL. - * - * Enabling UART in SPL u-boot requires console library. But some - * functions we needed in the console library depends on a bunch - * of library in libgeneric, like lib/ctype.o, lib/div64.o, lib/string.o, - * and lib/vsprintf.o. Adding them makes the SPL u-boot too large and not - * fit into the expected size. - * - * So we mock these functions in SPL, i.e. vsprintf(), panic(), etc., - * in order to cut its dependency. - */ -int vsprintf(char *buf, const char *fmt, va_list args) -{ - char *str = buf, *s; - ulong u; - - /* - * We won't implement all full functions of vsprintf(). - * We only implement %s and %u, and ignore others and directly use - * the original format string as its result. - */ - - while (*fmt) { - if (*fmt != '%') { - *str++ = *fmt++; - continue; - } - fmt++; - switch (*fmt) { - case '%': - *str++ = *fmt++; - break; - case 's': - fmt++; - s = va_arg(args, char *); - while (*s) - *str++ = *s++; - break; - case 'u': - fmt++; - u = va_arg(args, ulong); - s = simple_itoa(u); - while (*s) - *str++ = *s++; - break; - default: - /* Print the original string for unsupported formats */ - *str++ = '%'; - *str++ = *fmt++; - } - } - *str = '\0'; - return str - buf; -} -#endif - -#if 0 -void panic(const char *fmt, ...) -{ - va_list args; - va_start(args, fmt); - vprintf(fmt, args); - putc('\n'); - va_end(args); -#if defined(CONFIG_PANIC_HANG) - hang(); -#else - udelay(100000); /* allow messages to go out */ - do_reset(NULL, 0, 0, NULL); -#endif - while (1) - ; -} -#endif - -#if 0 -void __assert_fail(const char *assertion, const char *file, unsigned line, - const char *function) -{ - /* This will not return */ - panic("%s:%u: %s: Assertion `%s' failed.", file, line, function, - assertion); -} -#endif - -#if 0 -char *simple_itoa(ulong i) -{ - /* 21 digits plus null terminator, good for 64-bit or smaller ints */ - static char local[22] __attribute__((section(".data"))); - char *p = &local[21]; - - *p-- = '\0'; - do { - *p-- = '0' + i % 10; - i /= 10; - } while (i > 0); - return p + 1; -} -#endif diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 6a09d88..0b07b90 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -88,10 +88,6 @@ config SYS_SDRAM_BASE hex "SDRAM base address" default 0x40000000 -config SPL_BUILD - bool - default n - config SYS_TEXT_BASE hex "Executable code section" default 0x43e00000 diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index 2de949a..dbddce0 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -564,8 +564,6 @@ const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf); * At present we are using 14148 of 14336 bytes. If we change this function * to be exported in SPL, we go over the edge. */ -/* TODO(dhendrix): do we still need this ifndef? */ -//#ifndef CONFIG_SPL_BUILD /** * Get the required memory type and speed (Main U-Boot version). * @@ -581,6 +579,5 @@ const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf); int clock_get_mem_selection(enum ddr_mode *mem_type, unsigned *frequency_mhz, unsigned *arm_freq, enum mem_manuf *mem_manuf); -//#endif /* CONFIG_SPL_BUILD */ #endif diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 4f21022..27e96ae 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,7 +452,6 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -#ifdef CONFIG_SPL_BUILD /* * This is a custom implementation for the udelay(), as we do not the timer * initialise during the SPL boot. We are assuming the cpu takes 3 instruction @@ -466,4 +465,3 @@ void udelay(unsigned usec) count = usec * (get_pll_clk(APLL) / (3 * 10000000)); sdelay(count); } -#endif diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c index f91cbb3..8c4b583 100644 --- a/src/cpu/samsung/exynos5250/dmc_common.c +++ b/src/cpu/samsung/exynos5250/dmc_common.c @@ -22,13 +22,13 @@ * MA 02111-1307 USA */ +#include <arch/io.h> #include <assert.h> #include <common.h> #include <console/console.h> #include <cpu/samsung/exynos5250/setup.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/clock_init.h> -#include <cpu/samsung/exynos5-common/spl.h> #include <system.h> #include "clock_init.h" diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 2e0b253..25931e4 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -29,7 +29,6 @@ #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> #include <cpu/samsung/exynos5250/sysreg.h> -#include <cpu/samsung/exynos5-common/spl.h> #include <drivers/maxim/max77686/max77686.h> #include "device/i2c.h" diff --git a/src/cpu/samsung/s5p-common/cpu_info.c b/src/cpu/samsung/s5p-common/cpu_info.c index 6b4742e..1c4c49f 100644 --- a/src/cpu/samsung/s5p-common/cpu_info.c +++ b/src/cpu/samsung/s5p-common/cpu_info.c @@ -92,7 +92,7 @@ int print_cpuinfo(void) } #endif -#ifndef CONFIG_SPL_BUILD +#if 0 void board_show_dram(ulong size) { enum ddr_mode mem_type; diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index 0023beb..e91b9df 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -95,9 +95,7 @@ static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio) } } -#ifndef CONFIG_SPL_BUILD assert(gpio < GPIO_MAX_PORT); /* ...which it will not be */ -#endif return NULL; } //#endif diff --git a/src/cpu/samsung/s5p-common/timer.c b/src/cpu/samsung/s5p-common/timer.c index 373c374..c6ed830 100644 --- a/src/cpu/samsung/s5p-common/timer.c +++ b/src/cpu/samsung/s5p-common/timer.c @@ -67,7 +67,7 @@ int init_timer(void) pwm_init(4, MUX_DIV_4, 0); pwm_config(4, 100000, 100000); pwm_enable(4); -#ifndef CONFIG_SPL_BUILD + /* Use this as the current monotonic time in us */ //gd->timer_reset_value = 0; timer_reset_value = 0; @@ -75,7 +75,6 @@ int init_timer(void) /* Use this as the last timer value we saw */ //gd->lastinc = timer_get_us_down(); lastinc = timer_get_us_down(); -#endif } return 0; diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 0d1cb0c..04bf543 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -26,15 +26,6 @@ romstage-y += memory.c romstage-y += romstage.c # ramstage-y += ec.c - -# FIXME: smdk5250_spl and mainboard.c are a mess. In the long -# run we'll want to replace low-level code that calls mainboard code -# with mainboard code that calls low-level code with appropriate -# parameters. Grep around for spl_get_machine_params for examples. -romstage-y += smdk5250_spl.c -ramstage-y += smdk5250_spl.c -bootblock-y += smdk5250_spl.c -#ramstage-y += mainboard.c ramstage-y += ramstage.c # romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c deleted file mode 100644 index 33f27b1..0000000 --- a/src/mainboard/google/snow/smdk5250_spl.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <arch/gpio.h> -#include <cpu/samsung/exynos5-common/spl.h> -#include <cpu/samsung/exynos5250/gpio.h> - -#define SIGNATURE 0xdeadbeef - -/* Parameters of early board initialization in SPL */ -static struct spl_machine_param machine_param = { - .signature = SIGNATURE, - .version = 1, - .params = "vmubfasirMw", - .size = sizeof(machine_param), - - .mem_iv_size = 0x1f, - .mem_type = DDR_MODE_DDR3, - - /* - * Set uboot_size to 0x100000 bytes. - * - * This is an overly conservative value chosen to accommodate all - * possible U-Boot image. You are advised to set this value to a - * smaller realistic size via scripts that modifies the .machine_param - * section of output U-Boot image. - */ - .uboot_size = 0x100000, - - .boot_source = BOOT_MODE_OM, - .frequency_mhz = 800, - .arm_freq_mhz = 1700, - .serial_base = 0x12c30000, - .i2c_base = 0x12c60000, - .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), - .mem_manuf = MEM_MANUF_SAMSUNG, - .bad_wake_gpio = GPIO_Y10, -}; - -struct spl_machine_param *spl_get_machine_params(void) -{ - if (machine_param.signature != SIGNATURE) { - /* TODO: Call panic() here */ - while (1) - ; - } - - return &machine_param; -} - -#if 0 -int board_get_revision(void) -{ - struct spl_machine_param *params = spl_get_machine_params(); - unsigned gpio[CONFIG_BOARD_REV_GPIO_COUNT]; - - gpio[0] = params->board_rev_gpios & 0xffff; - gpio[1] = params->board_rev_gpios >> 16; - return gpio_decode_number(gpio, CONFIG_BOARD_REV_GPIO_COUNT); -} -#endif - -int board_wakeup_permitted(void) -{ - struct spl_machine_param *param = spl_get_machine_params(); - const int gpio = param->bad_wake_gpio; - int is_bad_wake; - - /* We're a bad wakeup if the gpio was defined and was high */ - is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); - - return !is_bad_wake; -}

1 0

Patch set updated for coreboot: b9e2757 console: Revise serial console configuration names.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2299 -gerrit commit b9e2757823828ba02e3fe367d194aba0c14aed78 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 21:24:12 2013 +0800 console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This CL will change configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers were named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/Kconfig | 4 ++++ src/arch/armv7/lib/romstage_console.c | 6 +++--- src/console/Kconfig | 39 ++++++++++++++++++----------------- src/console/Makefile.inc | 4 ++-- src/console/console.c | 2 +- src/cpu/Kconfig | 2 +- src/cpu/samsung/Kconfig | 5 ++++- src/include/console/console.h | 4 ++-- src/mainboard/google/snow/Kconfig | 5 ++--- src/mainboard/google/snow/bootblock.c | 4 ++-- 10 files changed, 41 insertions(+), 34 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 92bdf11..32a63d8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -277,6 +277,10 @@ config HAVE_UART_MEMORY_MAPPED bool default n +config HAVE_UART_SPECIAL + bool + default n + config HAVE_ACPI_RESUME bool default n diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c index 42a9664..b0ac34e 100644 --- a/src/arch/armv7/lib/romstage_console.c +++ b/src/arch/armv7/lib/romstage_console.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <console/vtxprintf.h> // TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL #include <uart.h> #endif #if CONFIG_USBDEBUG @@ -33,7 +33,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL_UART uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG @@ -46,7 +46,7 @@ void console_tx_byte(unsigned char byte) static void _console_tx_flush(void) { -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL_UART uart_tx_flush(); #endif #if CONFIG_USBDEBUG diff --git a/src/console/Kconfig b/src/console/Kconfig index b1f41de..e57d568 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,20 +1,21 @@ menu "Console" -config SERIAL_CONSOLE - bool "Serial port console output" - default y - help - Send coreboot debug output to a serial port -config EARLY_SERIAL_CONSOLE - bool - depends on SERIAL_CONSOLE +config EARLY_CONSOLE + bool "Enable early (pre-RAM) console output." default n help - Use serial console during early (pre-RAM) boot stages + Use console during early (pre-RAM) boot stages + +config CONSOLE_SERIAL + bool "Serial port console output" + default y + help + Send coreboot debug output to a serial port (should be one or more of + CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) config CONSOLE_SERIAL8250 bool "Serial port console output (I/O mapped, 8250-compatible)" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL depends on HAVE_UART_IO_MAPPED default y help @@ -22,21 +23,21 @@ config CONSOLE_SERIAL8250 config CONSOLE_SERIAL8250MEM bool "Serial port console output (memory mapped, 8250-compatible)" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL depends on HAVE_UART_MEMORY_MAPPED help Send coreboot debug output to a memory mapped serial port console. -config CONSOLE_SERIAL_NONSTANDARD_MEM - bool "Serial port console output (memory-mapped, device-specific)" - depends on SERIAL_CONSOLE - depends on HAVE_UART_MEMORY_MAPPED +config CONSOLE_SERIAL_UART + bool "Serial port console output (device-specific UART)" + depends on CONSOLE_SERIAL + depends on HAVE_UART_SPECIAL + default y help - Send coreboot debug output to a memory mapped serial port console - on a device-specific UART. + Send coreboot debug output to a device-specific serial port console. choice - prompt "Serial port" + prompt "Serial port for 8250" default CONSOLE_SERIAL_COM1 depends on CONSOLE_SERIAL8250 @@ -72,7 +73,7 @@ config TTYS0_BASE choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_115200 bool "115200" diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 42d3282..938dee3 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -10,12 +10,12 @@ smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-y += vtxprintf.c -romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += console.c romstage-y += post.c romstage-y += die.c bootblock-y += vtxprintf.c -bootblock-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += console.c bootblock-y += post.c bootblock-y += die.c diff --git a/src/console/console.c b/src/console/console.c index 4c47d7f..d4b4b88 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -107,7 +107,7 @@ void console_init(void) enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL uart_init(); #endif #if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index ddc46cf..c2c3816 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,7 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select EARLY_SERIAL_CONSOLE + select EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index abfc049..c905b2a 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -5,7 +5,10 @@ config CPU_SAMSUNG_EXYNOS config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS - select EARLY_SERIAL_CONSOLE + select HAVE_UART_SPECIAL + # TODO remove EARLY_CONSOLE when we can run ramstage without early UART + # init. + select EARLY_CONSOLE bool default n diff --git a/src/include/console/console.h b/src/include/console/console.h index 375e5a4..edd49e0 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,8 +24,8 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> +#if CONFIG_CONSOLE_SERIAL +#include <uart.h> #endif #if CONFIG_USBDEBUG #include <usbdebug.h> diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index a0c76d6..bee987d 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS5 select HAVE_UART_MEMORY_MAPPED - select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging # select EC_GOOGLE_CHROMEEC select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 @@ -71,7 +70,7 @@ config NR_DRAM_BANKS choice prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_NONSTANDARD_MEM + depends on CONSOLE_SERIAL_UART config CONSOLE_SERIAL_UART0 bool "UART0" @@ -97,7 +96,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_NONSTANDARD_MEM + depends on CONSOLE_SERIAL_UART default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 64b12c6..ff5e4a0 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_SERIAL_CONSOLE +#if CONFIG_EARLY_CONSOLE #include <types.h> #include <arch/io.h> #include <cbfs.h> @@ -47,7 +47,7 @@ void bootblock_mainboard_init(void) arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); -#if CONFIG_EARLY_SERIAL_CONSOLE +#if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); uart_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__);

1 0

Patch set updated for coreboot: 9990d48 armv7: Clean up: replace hang() by hlt().
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2298 -gerrit commit 9990d48439c7f9843f7aa5e72024a672ddac594a Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 18:03:40 2013 +0800 armv7: Clean up: replace hang() by hlt(). hang() is the legacy function from U-boot and should be replaced by hlt() in coreboot. Change-Id: I0f390b1b6f9ff71487ea36cf16c462724b66d8ca Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/include/common.h | 2 -- src/arch/armv7/include/hang.h | 20 -------------------- src/arch/armv7/lib/Makefile.inc | 2 -- src/arch/armv7/lib/hang_spl.c | 16 ---------------- 4 files changed, 40 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index 1b69e84..d95a74d 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -129,8 +129,6 @@ ulong timer_get_us(void); * Function Prototypes */ -void hang (void) __attribute__ ((noreturn)); - int init_timer(void); /* FIXME(dhendrix): used to be timer_init() */ int cpu_init(void); diff --git a/src/arch/armv7/include/hang.h b/src/arch/armv7/include/hang.h deleted file mode 100644 index f57fc28..0000000 --- a/src/arch/armv7/include/hang.h +++ /dev/null @@ -1,20 +0,0 @@ - /* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -void hang(void); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 4fd15a6..343e9f8 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -5,7 +5,6 @@ romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += div64.S -romstage-y += hang_spl.c romstage-y += romstage_console.c romstage-y += syslib.c @@ -13,7 +12,6 @@ romstage-y += syslib.c ramstage-y += div0.c ramstage-y += div64.S -ramstage-y += hang_spl.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S diff --git a/src/arch/armv7/lib/hang_spl.c b/src/arch/armv7/lib/hang_spl.c deleted file mode 100644 index 630a57a..0000000 --- a/src/arch/armv7/lib/hang_spl.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - */ - -#include <hang.h> - -void hang(void) -{ - for (;;); -}

1 0

Patch set updated for coreboot: d535b01 armv7: Unify console in all stages.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2301 -gerrit commit d535b01e0dbcede5ffec920fb716e75a5cac4d4a Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 22:01:18 2013 +0800 armv7: Unify console in all stages. Uses same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> console_init() ... printk(level, format, ...) Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 9 ++-- src/arch/armv7/bootblock_simple.c | 2 + src/arch/armv7/include/common.h | 13 ------ src/arch/armv7/lib/Makefile.inc | 6 +-- src/arch/armv7/lib/early_console.c | 81 +++++++++++++++++++++++++++++++++ src/arch/armv7/lib/romstage_console.c | 73 ----------------------------- src/cpu/samsung/exynos5-common/uart.h | 2 - src/cpu/samsung/exynos5250/Makefile.inc | 13 ++---- src/cpu/samsung/exynos5250/uart.c | 4 +- src/include/uart.h | 5 +- src/mainboard/google/snow/bootblock.c | 12 ++--- 11 files changed, 101 insertions(+), 119 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 7d02e7c..0471b94 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -223,17 +223,18 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC) $(bootblock-c-ccopts) $(INCLUDES) -MM \ + -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ + $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index fe2662e..0132b87 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -23,6 +23,7 @@ #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> +#include <console/console.h> #include "stages.c" @@ -46,6 +47,7 @@ void main(void) bootblock_mainboard_init(); } + console_init(); printk(BIOS_INFO, "hello from bootblock\n"); printk(BIOS_INFO, "bootblock main(): loading romstage\n"); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index d95a74d..d8698db 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -422,19 +422,6 @@ int strcmp_compar(const void *, const void *); /* lib/time.c */ void udelay (unsigned long); -#if 0 -/* lib/vsprintf.c */ -ulong simple_strtoul(const char *cp,char **endp,unsigned int base); -int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); -unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); -long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2), noreturn)); -int sprintf(char * buf, const char *fmt, ...) - __attribute__ ((format (__printf__, 2, 3))); -int vsprintf(char *buf, const char *fmt, va_list args); -#endif - /* lib/strmhz.c */ char * strmhz(char *buf, unsigned long hz); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 343e9f8..048e071 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,14 +1,12 @@ bootblock-y += syslib.c -bootblock-y += romstage_console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += div64.S -romstage-y += romstage_console.c romstage-y += syslib.c - -#ramstage-y += printk_init.c +romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c ramstage-y += div64.S diff --git a/src/arch/armv7/lib/early_console.c b/src/arch/armv7/lib/early_console.c new file mode 100644 index 0000000..68e81c6 --- /dev/null +++ b/src/arch/armv7/lib/early_console.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +/* FIXME: need to make console driver more generic */ +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL8250MEM + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif +} + +static void _console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) { + return 0; + } + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + _console_tx_flush(); + + return i; +} diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c deleted file mode 100644 index b0ac34e..0000000 --- a/src/arch/armv7/lib/romstage_console.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/vtxprintf.h> -// TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_CONSOLE_SERIAL -#include <uart.h> -#endif -#if CONFIG_USBDEBUG -#include <usbdebug.h> -#endif - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_byte(byte); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_CBMEM - cbmemc_tx_byte(byte); -#endif -} - -static void _console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_flush(); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_flush(0); -#endif -} - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - _console_tx_flush(); - - return i; -} diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h index 52da62d..350e224 100644 --- a/src/cpu/samsung/exynos5-common/uart.h +++ b/src/cpu/samsung/exynos5-common/uart.h @@ -52,6 +52,4 @@ static inline int s5p_uart_divslot(void) return 0; } -void uart_init(void); - #endif diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e2033ff..7e11536 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -11,7 +11,7 @@ bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += power.c bootblock-y += soc.c -bootblock-y += uart.c +bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c romstage-y += clock_init.c @@ -19,23 +19,18 @@ romstage-y += exynos_cache.c romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c -romstage-y += uart.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c +romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -#ramstage-y += clock.c -#ramstage-y += clock_init.c -#ramstage-y += power.c -#ramstage-y += uart.c -#ramstage-y += pinmux.c -##ramstage-y += tzpc_init.c +#ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c -ramstage-y += uart.c +ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3126d7a..dacdc10 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,6 +28,8 @@ #include <console/console.h> /* for __console definition */ #include <cpu/samsung/exynos5-common/exynos5-common.h> +#include <cpu/samsung/exynos5-common/uart.h> +#include <cpu/samsung/exynos5250/uart.h> #include <cpu/samsung/exynos5250/clk.h> #define RX_FIFO_COUNT_MASK 0xff @@ -188,7 +190,7 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } -#if !defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) +#if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, diff --git a/src/include/uart.h b/src/include/uart.h index e424496..ca5191e 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -30,14 +30,11 @@ #include <uart8250.h> #endif -#if CONFIG_CPU_SAMSUNG_EXYNOS5 -#include <cpu/samsung/exynos5-common/uart.h> -#endif - #if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); +void uart_init(void); #endif #endif /* UART_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index ff5e4a0..be5a99f 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,12 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_CONSOLE #include <types.h> #include <arch/io.h> -#include <cbfs.h> -#include <uart.h> -#include <console/console.h> #include <device/i2c.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -30,9 +26,9 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <src/cpu/samsung/exynos5250/power.h> #include <drivers/maxim/max77686/max77686.h> +#include <console/console.h> #define I2C0_BASE 0x12c60000 -#endif void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) @@ -46,10 +42,8 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - -#if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - uart_init(); + + console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); -#endif }

1 0

Patch set updated for coreboot: 03f8985 console: Support EARLY_CONSOLE correctly.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2300 -gerrit commit 03f89858a3dce5fb5723c7e6d471e7bf9463737f Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 21:51:15 2013 +0800 console: Support EARLY_CONSOLE correctly. Refines console source file dependency (especially for EARLY_CONSOLE), and interprets printk/console_init according to EARLY_CONSOLE setting (no-ops if EARLY_CONSOLE is not defined). Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/console/Makefile.inc | 8 ++++---- src/console/console.c | 8 +++++--- src/include/console/console.h | 16 ++++++++++++++-- src/include/uart.h | 4 ++-- 4 files changed, 25 insertions(+), 11 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 938dee3..9ce3474 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,13 +9,13 @@ smm-y += printk.c smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c -romstage-y += vtxprintf.c -romstage-$(CONFIG_EARLY_CONSOLE) += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +romstage-y += console.c romstage-y += post.c romstage-y += die.c -bootblock-y += vtxprintf.c -bootblock-$(CONFIG_EARLY_CONSOLE) += console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +bootblock-y += console.c bootblock-y += post.c bootblock-y += die.c diff --git a/src/console/console.c b/src/console/console.c index d4b4b88..fc77df7 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,10 +99,10 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined -#include <uart.h> - void console_init(void) { +#if CONFIG_EARLY_CONSOLE + #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); @@ -127,5 +127,7 @@ void console_init(void) COREBOOT_BUILD " starting...\n"; print_info(console_test); + +#endif /* CONFIG_EARLY_CONSOLE */ } -#endif +#endif /* __PRE_RAM__ */ diff --git a/src/include/console/console.h b/src/include/console/console.h index edd49e0..497a517 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -74,6 +74,15 @@ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +#if defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE + +static inline void printk(int LEVEL, const char *fmt, ...); +static inline void printk(int LEVEL, const char *fmt, ...) { + /* Do nothing. */ +} + +#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ + #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS /* We saw some strange effects in the past like coreboot crashing while * disabling cache as ram for a maximum console log level of 6 and above while @@ -97,7 +106,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, } \ } while(0) -#else +#else /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */ #define printk(LEVEL, fmt, args...) \ do { \ @@ -107,7 +116,10 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, do_printk(BIOS_NEVER, fmt, ##args); \ } \ } while(0) -#endif + +#endif /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */ + +#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) diff --git a/src/include/uart.h b/src/include/uart.h index 2a72575..e424496 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -26,7 +26,7 @@ #ifndef UART_H #define UART_H -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -34,7 +34,7 @@ #include <cpu/samsung/exynos5-common/uart.h> #endif -#ifndef __ROMCC__ +#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void);

1 0

New patch to review for coreboot: 8d6715d armv7: Unify console in all stages.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2301 -gerrit commit 8d6715da5195a395f018e4fbbf9647d4e3410776 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 22:01:18 2013 +0800 armv7: Unify console in all stages. Uses same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> console_init() ... printk(level, format, ...) Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 9 ++-- src/arch/armv7/bootblock_simple.c | 2 + src/arch/armv7/include/common.h | 13 ------ src/arch/armv7/lib/Makefile.inc | 6 +-- src/arch/armv7/lib/early_console.c | 81 +++++++++++++++++++++++++++++++++ src/arch/armv7/lib/romstage_console.c | 73 ----------------------------- src/cpu/samsung/exynos5-common/uart.h | 2 - src/cpu/samsung/exynos5250/Makefile.inc | 13 ++---- src/cpu/samsung/exynos5250/uart.c | 4 +- src/include/uart.h | 5 +- src/mainboard/google/snow/bootblock.c | 12 ++--- 11 files changed, 101 insertions(+), 119 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 7d02e7c..0471b94 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -223,17 +223,18 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC) $(bootblock-c-ccopts) $(INCLUDES) -MM \ + -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ + $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index fe2662e..0132b87 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -23,6 +23,7 @@ #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> +#include <console/console.h> #include "stages.c" @@ -46,6 +47,7 @@ void main(void) bootblock_mainboard_init(); } + console_init(); printk(BIOS_INFO, "hello from bootblock\n"); printk(BIOS_INFO, "bootblock main(): loading romstage\n"); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index d95a74d..d8698db 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -422,19 +422,6 @@ int strcmp_compar(const void *, const void *); /* lib/time.c */ void udelay (unsigned long); -#if 0 -/* lib/vsprintf.c */ -ulong simple_strtoul(const char *cp,char **endp,unsigned int base); -int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); -unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); -long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2), noreturn)); -int sprintf(char * buf, const char *fmt, ...) - __attribute__ ((format (__printf__, 2, 3))); -int vsprintf(char *buf, const char *fmt, va_list args); -#endif - /* lib/strmhz.c */ char * strmhz(char *buf, unsigned long hz); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 343e9f8..048e071 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,14 +1,12 @@ bootblock-y += syslib.c -bootblock-y += romstage_console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += div64.S -romstage-y += romstage_console.c romstage-y += syslib.c - -#ramstage-y += printk_init.c +romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c ramstage-y += div64.S diff --git a/src/arch/armv7/lib/early_console.c b/src/arch/armv7/lib/early_console.c new file mode 100644 index 0000000..68e81c6 --- /dev/null +++ b/src/arch/armv7/lib/early_console.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +/* FIXME: need to make console driver more generic */ +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL8250MEM + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif +} + +static void _console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) { + return 0; + } + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + _console_tx_flush(); + + return i; +} diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c deleted file mode 100644 index b0ac34e..0000000 --- a/src/arch/armv7/lib/romstage_console.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/vtxprintf.h> -// TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_CONSOLE_SERIAL -#include <uart.h> -#endif -#if CONFIG_USBDEBUG -#include <usbdebug.h> -#endif - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_byte(byte); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_CBMEM - cbmemc_tx_byte(byte); -#endif -} - -static void _console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_flush(); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_flush(0); -#endif -} - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - _console_tx_flush(); - - return i; -} diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h index 52da62d..350e224 100644 --- a/src/cpu/samsung/exynos5-common/uart.h +++ b/src/cpu/samsung/exynos5-common/uart.h @@ -52,6 +52,4 @@ static inline int s5p_uart_divslot(void) return 0; } -void uart_init(void); - #endif diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e2033ff..7e11536 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -11,7 +11,7 @@ bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += power.c bootblock-y += soc.c -bootblock-y += uart.c +bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c romstage-y += clock_init.c @@ -19,23 +19,18 @@ romstage-y += exynos_cache.c romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c -romstage-y += uart.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c +romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -#ramstage-y += clock.c -#ramstage-y += clock_init.c -#ramstage-y += power.c -#ramstage-y += uart.c -#ramstage-y += pinmux.c -##ramstage-y += tzpc_init.c +#ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c -ramstage-y += uart.c +ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3126d7a..dacdc10 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,6 +28,8 @@ #include <console/console.h> /* for __console definition */ #include <cpu/samsung/exynos5-common/exynos5-common.h> +#include <cpu/samsung/exynos5-common/uart.h> +#include <cpu/samsung/exynos5250/uart.h> #include <cpu/samsung/exynos5250/clk.h> #define RX_FIFO_COUNT_MASK 0xff @@ -188,7 +190,7 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } -#if !defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) +#if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, diff --git a/src/include/uart.h b/src/include/uart.h index e424496..ca5191e 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -30,14 +30,11 @@ #include <uart8250.h> #endif -#if CONFIG_CPU_SAMSUNG_EXYNOS5 -#include <cpu/samsung/exynos5-common/uart.h> -#endif - #if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); +void uart_init(void); #endif #endif /* UART_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index ff5e4a0..be5a99f 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,12 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_CONSOLE #include <types.h> #include <arch/io.h> -#include <cbfs.h> -#include <uart.h> -#include <console/console.h> #include <device/i2c.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -30,9 +26,9 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <src/cpu/samsung/exynos5250/power.h> #include <drivers/maxim/max77686/max77686.h> +#include <console/console.h> #define I2C0_BASE 0x12c60000 -#endif void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) @@ -46,10 +42,8 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - -#if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - uart_init(); + + console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); -#endif }

1 0

New patch to review for coreboot: 6a81b32 console: Support EARLY_CONSOLE correctly.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2300 -gerrit commit 6a81b32519a778849a597da79c347dc017da61ea Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 21:51:15 2013 +0800 console: Support EARLY_CONSOLE correctly. Refines console source file dependency (especially for EARLY_CONSOLE), and interprets printk/console_init according to EARLY_CONSOLE setting (no-ops if EARLY_CONSOLE is not defined). Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/console/Makefile.inc | 8 ++++---- src/console/console.c | 8 +++++--- src/include/console/console.h | 16 ++++++++++++++-- src/include/uart.h | 4 ++-- 4 files changed, 25 insertions(+), 11 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 938dee3..9ce3474 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,13 +9,13 @@ smm-y += printk.c smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c -romstage-y += vtxprintf.c -romstage-$(CONFIG_EARLY_CONSOLE) += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +romstage-y += console.c romstage-y += post.c romstage-y += die.c -bootblock-y += vtxprintf.c -bootblock-$(CONFIG_EARLY_CONSOLE) += console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +bootblock-y += console.c bootblock-y += post.c bootblock-y += die.c diff --git a/src/console/console.c b/src/console/console.c index d4b4b88..fc77df7 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,10 +99,10 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined -#include <uart.h> - void console_init(void) { +#if CONFIG_EARLY_CONSOLE + #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); @@ -127,5 +127,7 @@ void console_init(void) COREBOOT_BUILD " starting...\n"; print_info(console_test); + +#endif /* CONFIG_EARLY_CONSOLE */ } -#endif +#endif /* __PRE_RAM__ */ diff --git a/src/include/console/console.h b/src/include/console/console.h index edd49e0..497a517 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -74,6 +74,15 @@ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +#if defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE + +static inline void printk(int LEVEL, const char *fmt, ...); +static inline void printk(int LEVEL, const char *fmt, ...) { + /* Do nothing. */ +} + +#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ + #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS /* We saw some strange effects in the past like coreboot crashing while * disabling cache as ram for a maximum console log level of 6 and above while @@ -97,7 +106,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, } \ } while(0) -#else +#else /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */ #define printk(LEVEL, fmt, args...) \ do { \ @@ -107,7 +116,10 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, do_printk(BIOS_NEVER, fmt, ##args); \ } \ } while(0) -#endif + +#endif /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */ + +#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) diff --git a/src/include/uart.h b/src/include/uart.h index 2a72575..e424496 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -26,7 +26,7 @@ #ifndef UART_H #define UART_H -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -34,7 +34,7 @@ #include <cpu/samsung/exynos5-common/uart.h> #endif -#ifndef __ROMCC__ +#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void);

1 0

Patch set updated for coreboot: f3cfc24 console: Revise serial console configuration names.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2299 -gerrit commit f3cfc24865f91d1a5fe581ef2336a0037a02244b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 21:24:12 2013 +0800 console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This CL will change configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers were named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/Kconfig | 4 ++++ src/arch/armv7/lib/romstage_console.c | 6 +++--- src/console/Kconfig | 39 ++++++++++++++++++----------------- src/console/Makefile.inc | 4 ++-- src/console/console.c | 2 +- src/cpu/Kconfig | 2 +- src/cpu/samsung/Kconfig | 5 ++++- src/include/console/console.h | 4 ++-- src/mainboard/google/snow/Kconfig | 5 ++--- src/mainboard/google/snow/bootblock.c | 4 ++-- 10 files changed, 41 insertions(+), 34 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 92bdf11..32a63d8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -277,6 +277,10 @@ config HAVE_UART_MEMORY_MAPPED bool default n +config HAVE_UART_SPECIAL + bool + default n + config HAVE_ACPI_RESUME bool default n diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c index 42a9664..b0ac34e 100644 --- a/src/arch/armv7/lib/romstage_console.c +++ b/src/arch/armv7/lib/romstage_console.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <console/vtxprintf.h> // TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL #include <uart.h> #endif #if CONFIG_USBDEBUG @@ -33,7 +33,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL_UART uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG @@ -46,7 +46,7 @@ void console_tx_byte(unsigned char byte) static void _console_tx_flush(void) { -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL_UART uart_tx_flush(); #endif #if CONFIG_USBDEBUG diff --git a/src/console/Kconfig b/src/console/Kconfig index b1f41de..e57d568 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,20 +1,21 @@ menu "Console" -config SERIAL_CONSOLE - bool "Serial port console output" - default y - help - Send coreboot debug output to a serial port -config EARLY_SERIAL_CONSOLE - bool - depends on SERIAL_CONSOLE +config EARLY_CONSOLE + bool "Enable early (pre-RAM) console output." default n help - Use serial console during early (pre-RAM) boot stages + Use console during early (pre-RAM) boot stages + +config CONSOLE_SERIAL + bool "Serial port console output" + default y + help + Send coreboot debug output to a serial port (should be one or more of + CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) config CONSOLE_SERIAL8250 bool "Serial port console output (I/O mapped, 8250-compatible)" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL depends on HAVE_UART_IO_MAPPED default y help @@ -22,21 +23,21 @@ config CONSOLE_SERIAL8250 config CONSOLE_SERIAL8250MEM bool "Serial port console output (memory mapped, 8250-compatible)" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL depends on HAVE_UART_MEMORY_MAPPED help Send coreboot debug output to a memory mapped serial port console. -config CONSOLE_SERIAL_NONSTANDARD_MEM - bool "Serial port console output (memory-mapped, device-specific)" - depends on SERIAL_CONSOLE - depends on HAVE_UART_MEMORY_MAPPED +config CONSOLE_SERIAL_UART + bool "Serial port console output (device-specific UART)" + depends on CONSOLE_SERIAL + depends on HAVE_UART_SPECIAL + default y help - Send coreboot debug output to a memory mapped serial port console - on a device-specific UART. + Send coreboot debug output to a device-specific serial port console. choice - prompt "Serial port" + prompt "Serial port for 8250" default CONSOLE_SERIAL_COM1 depends on CONSOLE_SERIAL8250 @@ -72,7 +73,7 @@ config TTYS0_BASE choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_115200 bool "115200" diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 42d3282..938dee3 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -10,12 +10,12 @@ smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-y += vtxprintf.c -romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += console.c romstage-y += post.c romstage-y += die.c bootblock-y += vtxprintf.c -bootblock-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += console.c bootblock-y += post.c bootblock-y += die.c diff --git a/src/console/console.c b/src/console/console.c index 4c47d7f..d4b4b88 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -107,7 +107,7 @@ void console_init(void) enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL uart_init(); #endif #if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index ddc46cf..c2c3816 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,7 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select EARLY_SERIAL_CONSOLE + select EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index abfc049..c905b2a 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -5,7 +5,10 @@ config CPU_SAMSUNG_EXYNOS config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS - select EARLY_SERIAL_CONSOLE + select HAVE_UART_SPECIAL + # TODO remove EARLY_CONSOLE when we can run ramstage without early UART + # init. + select EARLY_CONSOLE bool default n diff --git a/src/include/console/console.h b/src/include/console/console.h index 375e5a4..edd49e0 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,8 +24,8 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> +#if CONFIG_CONSOLE_SERIAL +#include <uart.h> #endif #if CONFIG_USBDEBUG #include <usbdebug.h> diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index a0c76d6..bee987d 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS5 select HAVE_UART_MEMORY_MAPPED - select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging # select EC_GOOGLE_CHROMEEC select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 @@ -71,7 +70,7 @@ config NR_DRAM_BANKS choice prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_NONSTANDARD_MEM + depends on CONSOLE_SERIAL_UART config CONSOLE_SERIAL_UART0 bool "UART0" @@ -97,7 +96,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_NONSTANDARD_MEM + depends on CONSOLE_SERIAL_UART default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 64b12c6..ff5e4a0 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_SERIAL_CONSOLE +#if CONFIG_EARLY_CONSOLE #include <types.h> #include <arch/io.h> #include <cbfs.h> @@ -47,7 +47,7 @@ void bootblock_mainboard_init(void) arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); -#if CONFIG_EARLY_SERIAL_CONSOLE +#if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); uart_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__);

1 0

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coreboot February 2013