coreboot February 2013

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New patch to review for coreboot: 765ff16 armv7/snow: Simplify bootblock.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2308 -gerrit commit 765ff16ba41f077df045be26868f256d7a3a0dfa Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Feb 7 13:22:29 2013 +0800 armv7/snow: Simplify bootblock. I2C, power, and max77686 are not required for bootblock to initialize. We only need SPI and clock to load romstage. Change-Id: Ic863e222871a157ba4279a673775b1e18c6eac0d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 11 ++++------- src/cpu/samsung/exynos5250/uart.c | 4 ++++ src/cpu/samsung/s5p-common/Makefile.inc | 1 - src/drivers/maxim/max77686/Makefile.inc | 1 - src/mainboard/google/snow/Makefile.inc | 4 ---- src/mainboard/google/snow/bootblock.c | 22 ---------------------- src/mainboard/google/snow/romstage.c | 15 ++++++++++++--- 7 files changed, 20 insertions(+), 38 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 7e11536..3aff95c 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,14 +3,11 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -# Clock init is done in bootblock to support UART output for -# debugging. We may add a Kconfig option to disable clock init -# in the bootblock and try moving it entirely into romstage. -bootblock-y += clock_init.c +# clock and clock_init are included for SPI to work. bootblock-y += clock.c -bootblock-y += pinmux.c -bootblock-y += power.c -bootblock-y += soc.c +bootblock-y += clock_init.c +bootblock-$(CONFIG_EARLY_CONSOLE) += pinmux.c +bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index dacdc10..a6ff139 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -121,6 +121,10 @@ static void exynos5_init_dev(void) // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); struct s5p_uart *uart = (struct s5p_uart *)base_port; + // TODO setup pinmux properly by dev_index and base_port, or move this + // to console driver. + exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index 621576d..0f4200c 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -1,5 +1,4 @@ bootblock-y += pwm.c -bootblock-y += s3c24x0_i2c.c bootblock-y += s5p_gpio.c bootblock-y += timer.c diff --git a/src/drivers/maxim/max77686/Makefile.inc b/src/drivers/maxim/max77686/Makefile.inc index 097b291..a5d7b90 100644 --- a/src/drivers/maxim/max77686/Makefile.inc +++ b/src/drivers/maxim/max77686/Makefile.inc @@ -17,6 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -bootblock-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c romstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c ramstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 04bf543..b56a1a4 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,10 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# needed for system_clock_init() -bootblock-y += mainboard.c -bootblock-y += memory.c - romstage-y += mainboard.c romstage-y += memory.c romstage-y += romstage.c diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index be5a99f..b220112 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,33 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <arch/io.h> -#include <device/i2c.h> -#include <cpu/samsung/exynos5250/clk.h> -#include <cpu/samsung/exynos5250/dmc.h> -#include <cpu/samsung/exynos5250/periph.h> -#include <cpu/samsung/exynos5250/clock_init.h> -#include <src/cpu/samsung/exynos5250/power.h> -#include <drivers/maxim/max77686/max77686.h> #include <console/console.h> -#define I2C0_BASE 0x12c60000 - void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - struct mem_timings *mem; - struct arm_clk_ratios *arm_ratios; - - i2c_set_early_reg(I2C0_BASE); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - power_init(); - mem = get_mem_timings(); - arm_ratios = get_arm_clk_ratios(); - system_clock_init(mem, arm_ratios); - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index b8e5116..20f4e81 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -24,6 +24,8 @@ #include <cbfs.h> #include <common.h> +#include <arch/hlt.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/setup.h> @@ -47,9 +49,10 @@ static int board_wakeup_permitted(void) void main(void) { - struct mem_timings *mem; int ret; void *entry; + struct mem_timings *mem; + struct arm_clk_ratios *arm_ratios; console_init(); printk(BIOS_INFO, "hello from romstage\n"); @@ -57,8 +60,14 @@ void main(void) mem = get_mem_timings(); if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); - while(1); + hlt(); } + arm_ratios = get_arm_clk_ratios(); + system_clock_init(mem, arm_ratios); + + /* Re-initialize console in case clock is changed. */ + console_init(); + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", mem->mem_manuf, mem->mem_type, @@ -69,7 +78,7 @@ void main(void) if (ret) { printk(BIOS_ERR, "Memory controller init failed, err: %x\n", ret); - while(1); + hlt(); } printk(BIOS_INFO, "ddr3_init done\n");

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New patch to review for coreboot: 325e3dd console: Always allow setting "EARLY_CONSOLE" configuration.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2307 -gerrit commit 325e3dd67c44ce3cb7ee2b3f9a00a970ee52bb4f Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Feb 7 13:41:56 2013 +0800 console: Always allow setting "EARLY_CONSOLE" configuration. Early console should always be allowed to be turned on / off (for generating production and debug versions), not enforced by "select" Kconfig rule. A new "DEFAULT_EARLY_CONSOLE" is introduced for devices to select if they prefer early console output by default. Verified Kconfig value on qemu/x86 (default y by CACHE_AS_RAM), snow/x86 (default y by EXYNOS5 config), and intel/jarrell (default n). Change-Id: Ib1cc76d4ec115a302b95e7317224f1a40d1ab035 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/console/Kconfig | 6 +++++- src/cpu/Kconfig | 2 +- src/cpu/samsung/Kconfig | 4 +--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index e57d568..7fbed4a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,8 +1,12 @@ menu "Console" +config DEFAULT_EARLY_CONSOLE + bool + default n + config EARLY_CONSOLE bool "Enable early (pre-RAM) console output." - default n + default DEFAULT_EARLY_CONSOLE help Use console during early (pre-RAM) boot stages diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index c2c3816..f60ffe7 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,7 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select EARLY_CONSOLE + select DEFAULT_EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index c905b2a..c2ee5b4 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -6,9 +6,7 @@ config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS select HAVE_UART_SPECIAL - # TODO remove EARLY_CONSOLE when we can run ramstage without early UART - # init. - select EARLY_CONSOLE + select DEFAULT_EARLY_CONSOLE bool default n

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Patch set updated for coreboot: b4f7ee7 console: Revise serial console configuration names.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2299 -gerrit commit b4f7ee79a042693a277784bd9b54dc7df59850f6 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 21:24:12 2013 +0800 console: Revise serial console configuration names. The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/Kconfig | 4 ++++ src/arch/armv7/lib/romstage_console.c | 6 +++--- src/console/Kconfig | 39 ++++++++++++++++++----------------- src/console/Makefile.inc | 4 ++-- src/console/console.c | 2 +- src/cpu/Kconfig | 2 +- src/cpu/samsung/Kconfig | 5 ++++- src/include/console/console.h | 4 ++-- src/mainboard/google/snow/Kconfig | 5 ++--- src/mainboard/google/snow/bootblock.c | 4 ++-- 10 files changed, 41 insertions(+), 34 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 92bdf11..32a63d8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -277,6 +277,10 @@ config HAVE_UART_MEMORY_MAPPED bool default n +config HAVE_UART_SPECIAL + bool + default n + config HAVE_ACPI_RESUME bool default n diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c index 42a9664..b0ac34e 100644 --- a/src/arch/armv7/lib/romstage_console.c +++ b/src/arch/armv7/lib/romstage_console.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <console/vtxprintf.h> // TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL #include <uart.h> #endif #if CONFIG_USBDEBUG @@ -33,7 +33,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL_UART uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG @@ -46,7 +46,7 @@ void console_tx_byte(unsigned char byte) static void _console_tx_flush(void) { -#if CONFIG_SERIAL_CONSOLE +#if CONFIG_CONSOLE_SERIAL_UART uart_tx_flush(); #endif #if CONFIG_USBDEBUG diff --git a/src/console/Kconfig b/src/console/Kconfig index b1f41de..e57d568 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,20 +1,21 @@ menu "Console" -config SERIAL_CONSOLE - bool "Serial port console output" - default y - help - Send coreboot debug output to a serial port -config EARLY_SERIAL_CONSOLE - bool - depends on SERIAL_CONSOLE +config EARLY_CONSOLE + bool "Enable early (pre-RAM) console output." default n help - Use serial console during early (pre-RAM) boot stages + Use console during early (pre-RAM) boot stages + +config CONSOLE_SERIAL + bool "Serial port console output" + default y + help + Send coreboot debug output to a serial port (should be one or more of + CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) config CONSOLE_SERIAL8250 bool "Serial port console output (I/O mapped, 8250-compatible)" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL depends on HAVE_UART_IO_MAPPED default y help @@ -22,21 +23,21 @@ config CONSOLE_SERIAL8250 config CONSOLE_SERIAL8250MEM bool "Serial port console output (memory mapped, 8250-compatible)" - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL depends on HAVE_UART_MEMORY_MAPPED help Send coreboot debug output to a memory mapped serial port console. -config CONSOLE_SERIAL_NONSTANDARD_MEM - bool "Serial port console output (memory-mapped, device-specific)" - depends on SERIAL_CONSOLE - depends on HAVE_UART_MEMORY_MAPPED +config CONSOLE_SERIAL_UART + bool "Serial port console output (device-specific UART)" + depends on CONSOLE_SERIAL + depends on HAVE_UART_SPECIAL + default y help - Send coreboot debug output to a memory mapped serial port console - on a device-specific UART. + Send coreboot debug output to a device-specific serial port console. choice - prompt "Serial port" + prompt "Serial port for 8250" default CONSOLE_SERIAL_COM1 depends on CONSOLE_SERIAL8250 @@ -72,7 +73,7 @@ config TTYS0_BASE choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on SERIAL_CONSOLE + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_115200 bool "115200" diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index dd826d6..8e6037a 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -10,13 +10,13 @@ smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-y += vtxprintf.c -romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += console.c romstage-y += post.c romstage-y += die.c # TODO Add vtxprintf.c only when early console is required. bootblock-y += vtxprintf.c -bootblock-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += console.c bootblock-y += die.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c diff --git a/src/console/console.c b/src/console/console.c index 4c47d7f..d4b4b88 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -107,7 +107,7 @@ void console_init(void) enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL uart_init(); #endif #if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index ddc46cf..c2c3816 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,7 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select EARLY_SERIAL_CONSOLE + select EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index abfc049..c905b2a 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -5,7 +5,10 @@ config CPU_SAMSUNG_EXYNOS config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS - select EARLY_SERIAL_CONSOLE + select HAVE_UART_SPECIAL + # TODO remove EARLY_CONSOLE when we can run ramstage without early UART + # init. + select EARLY_CONSOLE bool default n diff --git a/src/include/console/console.h b/src/include/console/console.h index 375e5a4..edd49e0 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,8 +24,8 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> +#if CONFIG_CONSOLE_SERIAL +#include <uart.h> #endif #if CONFIG_USBDEBUG #include <usbdebug.h> diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index a0c76d6..bee987d 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS5 select HAVE_UART_MEMORY_MAPPED - select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging # select EC_GOOGLE_CHROMEEC select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 @@ -71,7 +70,7 @@ config NR_DRAM_BANKS choice prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_NONSTANDARD_MEM + depends on CONSOLE_SERIAL_UART config CONSOLE_SERIAL_UART0 bool "UART0" @@ -97,7 +96,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_NONSTANDARD_MEM + depends on CONSOLE_SERIAL_UART default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 64b12c6..ff5e4a0 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_SERIAL_CONSOLE +#if CONFIG_EARLY_CONSOLE #include <types.h> #include <arch/io.h> #include <cbfs.h> @@ -47,7 +47,7 @@ void bootblock_mainboard_init(void) arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); -#if CONFIG_EARLY_SERIAL_CONSOLE +#if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); uart_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__);

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Patch set updated for coreboot: 05230f2 armv7: Unify console in all stages.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2301 -gerrit commit 05230f284dbf1ecf9671e672104947d4ac5f1256 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 22:01:18 2013 +0800 armv7: Unify console in all stages. Uses same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages. Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 9 ++-- src/arch/armv7/bootblock_simple.c | 2 + src/arch/armv7/include/common.h | 13 ------ src/arch/armv7/lib/Makefile.inc | 6 +-- src/arch/armv7/lib/early_console.c | 81 +++++++++++++++++++++++++++++++++ src/arch/armv7/lib/romstage_console.c | 73 ----------------------------- src/cpu/samsung/exynos5-common/uart.h | 2 - src/cpu/samsung/exynos5250/Makefile.inc | 13 ++---- src/cpu/samsung/exynos5250/uart.c | 4 +- src/include/uart.h | 5 +- src/mainboard/google/snow/bootblock.c | 12 ++--- src/mainboard/google/snow/ramstage.c | 4 +- 12 files changed, 102 insertions(+), 122 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 7d02e7c..0471b94 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -223,17 +223,18 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC) $(bootblock-c-ccopts) $(INCLUDES) -MM \ + -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ + $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index fe2662e..0132b87 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -23,6 +23,7 @@ #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> +#include <console/console.h> #include "stages.c" @@ -46,6 +47,7 @@ void main(void) bootblock_mainboard_init(); } + console_init(); printk(BIOS_INFO, "hello from bootblock\n"); printk(BIOS_INFO, "bootblock main(): loading romstage\n"); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index d95a74d..d8698db 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -422,19 +422,6 @@ int strcmp_compar(const void *, const void *); /* lib/time.c */ void udelay (unsigned long); -#if 0 -/* lib/vsprintf.c */ -ulong simple_strtoul(const char *cp,char **endp,unsigned int base); -int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); -unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); -long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2), noreturn)); -int sprintf(char * buf, const char *fmt, ...) - __attribute__ ((format (__printf__, 2, 3))); -int vsprintf(char *buf, const char *fmt, va_list args); -#endif - /* lib/strmhz.c */ char * strmhz(char *buf, unsigned long hz); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 343e9f8..048e071 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,14 +1,12 @@ bootblock-y += syslib.c -bootblock-y += romstage_console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += div64.S -romstage-y += romstage_console.c romstage-y += syslib.c - -#ramstage-y += printk_init.c +romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c ramstage-y += div64.S diff --git a/src/arch/armv7/lib/early_console.c b/src/arch/armv7/lib/early_console.c new file mode 100644 index 0000000..68e81c6 --- /dev/null +++ b/src/arch/armv7/lib/early_console.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +/* FIXME: need to make console driver more generic */ +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL8250MEM + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif +} + +static void _console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) { + return 0; + } + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + _console_tx_flush(); + + return i; +} diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c deleted file mode 100644 index b0ac34e..0000000 --- a/src/arch/armv7/lib/romstage_console.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/vtxprintf.h> -// TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_CONSOLE_SERIAL -#include <uart.h> -#endif -#if CONFIG_USBDEBUG -#include <usbdebug.h> -#endif - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_byte(byte); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_CBMEM - cbmemc_tx_byte(byte); -#endif -} - -static void _console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_flush(); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_flush(0); -#endif -} - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - _console_tx_flush(); - - return i; -} diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h index 52da62d..350e224 100644 --- a/src/cpu/samsung/exynos5-common/uart.h +++ b/src/cpu/samsung/exynos5-common/uart.h @@ -52,6 +52,4 @@ static inline int s5p_uart_divslot(void) return 0; } -void uart_init(void); - #endif diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e2033ff..7e11536 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -11,7 +11,7 @@ bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += power.c bootblock-y += soc.c -bootblock-y += uart.c +bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c romstage-y += clock_init.c @@ -19,23 +19,18 @@ romstage-y += exynos_cache.c romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c -romstage-y += uart.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c +romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -#ramstage-y += clock.c -#ramstage-y += clock_init.c -#ramstage-y += power.c -#ramstage-y += uart.c -#ramstage-y += pinmux.c -##ramstage-y += tzpc_init.c +#ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c -ramstage-y += uart.c +ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3126d7a..dacdc10 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,6 +28,8 @@ #include <console/console.h> /* for __console definition */ #include <cpu/samsung/exynos5-common/exynos5-common.h> +#include <cpu/samsung/exynos5-common/uart.h> +#include <cpu/samsung/exynos5250/uart.h> #include <cpu/samsung/exynos5250/clk.h> #define RX_FIFO_COUNT_MASK 0xff @@ -188,7 +190,7 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } -#if !defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) +#if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, diff --git a/src/include/uart.h b/src/include/uart.h index e424496..ca5191e 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -30,14 +30,11 @@ #include <uart8250.h> #endif -#if CONFIG_CPU_SAMSUNG_EXYNOS5 -#include <cpu/samsung/exynos5-common/uart.h> -#endif - #if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); +void uart_init(void); #endif #endif /* UART_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index ff5e4a0..be5a99f 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,12 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_CONSOLE #include <types.h> #include <arch/io.h> -#include <cbfs.h> -#include <uart.h> -#include <console/console.h> #include <device/i2c.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -30,9 +26,9 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <src/cpu/samsung/exynos5250/power.h> #include <drivers/maxim/max77686/max77686.h> +#include <console/console.h> #define I2C0_BASE 0x12c60000 -#endif void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) @@ -46,10 +42,8 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - -#if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - uart_init(); + + console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); -#endif } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 50050d3..f9d9c96 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -24,9 +24,7 @@ void main(void) // volatile unsigned long *pshold = (unsigned long *)0x1004330c; // *pshold &= ~0x100; /* shut down */ - /* FIXME: console_init() seems to cause things to die... Maybe - we need to reset our stack pointer? */ -// console_init(); + console_init(); printk(BIOS_INFO, "hello from ramstage\n"); while (1); }

1 0

Patch set updated for coreboot: 3711fdb console: Support EARLY_CONSOLE correctly.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2300 -gerrit commit 3711fdb9a7face4dd36417dcf3b6d61a65dccd56 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 21:51:15 2013 +0800 console: Support EARLY_CONSOLE correctly. Refines console source file dependency (especially for EARLY_CONSOLE), and interprets printk/console_init according to EARLY_CONSOLE setting (no-ops if EARLY_CONSOLE is not defined). Verified to boot on x86/qemu and armv7/snow. Disabling EARLY_CONSOLE correctly stops romstage messages on x86/qemu (armv7/snow needs more changes to work). Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/x86/lib/Makefile.inc | 2 +- src/console/Makefile.inc | 9 ++++----- src/console/console.c | 8 +++++--- src/include/console/console.h | 16 ++++++++++++++-- src/include/uart.h | 4 ++-- 5 files changed, 26 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index f4dc8b8..49d7e9e 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -10,7 +10,7 @@ ramstage-y += memcpy.c ramstage-y += ebda.c ramstage-y += rom_media.c -romstage-y += romstage_console.c +romstage-$(CONFIG_EARLY_CONSOLE) += romstage_console.c romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 8e6037a..9499180 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,14 +9,13 @@ smm-y += printk.c smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c -romstage-y += vtxprintf.c -romstage-$(CONFIG_EARLY_CONSOLE) += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +romstage-y += console.c romstage-y += post.c romstage-y += die.c -# TODO Add vtxprintf.c only when early console is required. -bootblock-y += vtxprintf.c -bootblock-$(CONFIG_EARLY_CONSOLE) += console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +bootblock-y += console.c bootblock-y += die.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c diff --git a/src/console/console.c b/src/console/console.c index d4b4b88..fc77df7 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,10 +99,10 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined -#include <uart.h> - void console_init(void) { +#if CONFIG_EARLY_CONSOLE + #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); @@ -127,5 +127,7 @@ void console_init(void) COREBOOT_BUILD " starting...\n"; print_info(console_test); + +#endif /* CONFIG_EARLY_CONSOLE */ } -#endif +#endif /* __PRE_RAM__ */ diff --git a/src/include/console/console.h b/src/include/console/console.h index edd49e0..497a517 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -74,6 +74,15 @@ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +#if defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE + +static inline void printk(int LEVEL, const char *fmt, ...); +static inline void printk(int LEVEL, const char *fmt, ...) { + /* Do nothing. */ +} + +#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ + #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS /* We saw some strange effects in the past like coreboot crashing while * disabling cache as ram for a maximum console log level of 6 and above while @@ -97,7 +106,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, } \ } while(0) -#else +#else /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */ #define printk(LEVEL, fmt, args...) \ do { \ @@ -107,7 +116,10 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, do_printk(BIOS_NEVER, fmt, ##args); \ } \ } while(0) -#endif + +#endif /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */ + +#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) diff --git a/src/include/uart.h b/src/include/uart.h index 2a72575..e424496 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -26,7 +26,7 @@ #ifndef UART_H #define UART_H -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -34,7 +34,7 @@ #include <cpu/samsung/exynos5-common/uart.h> #endif -#ifndef __ROMCC__ +#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void);

1 0

New patch to review for coreboot: d81798f AMD S3: Program the flash in a bigger data packet
by Zheng Bao 07 Feb '13

07 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2306 -gerrit commit d81798f11840b4b54149ae111aea5aef6b8c4dda Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Feb 7 16:21:34 2013 +0800 AMD S3: Program the flash in a bigger data packet Hudson limits the SPI programming data packet size as 15. We need to leverage that to increase the programming time. Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 54 ++++++++++++++++--------------------------- 1 file changed, 20 insertions(+), 34 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 5b4c2c3..77ac502 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -178,29 +178,21 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; msr_data = rdmsr(0x258); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; msr_data = rdmsr(0x259); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; } /* Disable access to AMD RdDram and WrDram extension bits */ @@ -211,32 +203,24 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; /* TOM */ msr_data = rdmsr(0xC001001A); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; /* TOM2 */ msr_data = rdmsr(0xC001001D); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); @@ -290,13 +274,15 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE); } + #define SPI_DATA_PACKET_SIZE 0xF nvram_pos = 0; flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); - for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + for (nvram_pos = 0; nvram_pos < DataSize - SPI_DATA_PACKET_SIZE; nvram_pos += SPI_DATA_PACKET_SIZE) { data = *(u32 *) (Data + nvram_pos); - flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos)); } + flash->write(flash, nvram_pos + pos + 4, DataSize % SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos)); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi);

1 0

AMD Parmer/Thatcher: Remaining differences in `BiosCallOuts.c`
by Paul Menzel 07 Feb '13

07 Feb '13

Dear coreboot folks, after $ git show --stat 2892023fd422794bb82658dde3e8d489af2bdd55 commit 2892023fd422794bb82658dde3e8d489af2bdd55 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jan 17 12:04:08 2013 -0700 AGESA F15tn: Move callouts into northbridge wrapper There are currently too many things in the mainboard directories that are really more suited to being in the northbridge / southbridge wrappers. This is a start at moving some of those functions down into the wrappers. Move the bios callback functions into the northbridge/amd/agesa/family15tn directory from the mainboard directories. These can still be overridden by any mainboard just by updating the pointer in the callback table to point to a customized version of the function. Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2169 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> src/mainboard/amd/parmer/BiosCallOuts.c | 464 ++------------------------------------------------------------------------- src/mainboard/amd/parmer/BiosCallOuts.h | 55 +-------- src/mainboard/amd/thatcher/BiosCallOuts.c | 464 ++------------------------------------------------------------------------- src/mainboard/amd/thatcher/BiosCallOuts.h | 55 +-------- src/northbridge/amd/agesa/family15tn/Makefile.inc | 4 + src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c | 405 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h | 53 +++++++++ the following differences remain. $ diff -u src/mainboard/amd/{parmer,thatcher}/BiosCallOuts.c --- src/mainboard/amd/parmer/BiosCallOuts.c 2013-01-23 00:25:21.150153420 +0100 +++ src/mainboard/amd/thatcher/BiosCallOuts.c 2013-01-23 00:25:21.150153420 +0100 @@ -72,9 +72,9 @@ } /** - * AMD Parmer Platform ALC272 Verb Table + * AMD Thatcher Platform ALC272 Verb Table */ -const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { +const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { {0x11, 0x411111F0}, {0x12, 0x411111F0}, {0x13, 0x411111F0}, @@ -92,9 +92,9 @@ {0xff, 0xffffffff} }; -const CODEC_TBL_LIST ParmerCodecTableList[] = +const CODEC_TBL_LIST ThatcherCodecTableList[] = { - {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, + {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; Could these objects be named the same? @@ -165,33 +165,33 @@ /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x35; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0E;//6 | BIT3; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 1; /* PWM steping rate in unit of PWM level percentage */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0; /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 105;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 60; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 105; /*critical threshold* in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; /* IMC Fan Policy PWM Settings */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */ @@ -205,10 +205,10 @@ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 1; /* PWM steping rate in unit of PWM level percentage */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; @@ -221,12 +221,12 @@ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 80; /*critical threshold* in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 100; /* AL0 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ In Parmer most of this stuff seems to be set to 0. Do the values in Thatcher’s file be used for Parmer too? @@ -296,13 +296,15 @@ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ParmerCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ /* Fan Control */ oem_fan_control(FchParams_env); - /* sata configuration */ + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; Does the Parmer board have XHCI? } printk(BIOS_DEBUG, "Done\n"); So if there are no problems with that, first a patch to unify the object names should be made, then one to use Thatcher’s values for Parmer too and then moving everything to the northbridge directory. Thanks, Paul

3 2

New patch to review for coreboot: dd68832 AMD S3: Add missing erasing flash sector for MTRR register
by Zheng Bao 07 Feb '13

07 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2304 -gerrit commit dd688325831a8a9bc89a7105ab4d8de2a045f7d0 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Feb 7 13:46:17 2013 +0800 AMD S3: Add missing erasing flash sector for MTRR register Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 7069c77..5b4c2c3 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -168,6 +168,8 @@ void OemAgesaSaveMtrr(void) flash->spi->rw = SPI_WRITE_FLAG; spi_claim_bus(flash->spi); + flash->erase(flash, S3_DATA_MTRR_POS, S3_DATA_MTRR_SIZE); + /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;

1 0

New patch to review for coreboot: 72b2edf AMD S3: Change the hardcoded data size to macros.
by Zheng Bao 07 Feb '13

07 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2303 -gerrit commit 72b2edffa06db3ad0c76444c17060ffaa4c55560 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Feb 7 13:45:09 2013 +0800 AMD S3: Change the hardcoded data size to macros. Change-Id: Ieefc4213a6dee9c399826b1daa98bbf4bc10d881 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 4 ++-- src/cpu/amd/agesa/s3_resume.h | 8 ++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 42e950f..7069c77 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -283,9 +283,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) spi_claim_bus(flash->spi); if (S3DataType == S3DataTypeNonVolatile) { - flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); + flash->erase(flash, S3_DATA_NONVOLATILE_POS, S3_DATA_NONVOLATILE_SIZE); } else { - flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000); + flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE); } nvram_pos = 0; diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 10bc826..e1c6cfc 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -20,9 +20,13 @@ #ifndef S3_RESUME_H #define S3_RESUME_H -#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + 0x7000) +/* The size needs to be 4k align, which is the sector size of most flashes. */ +#define S3_DATA_VOLATILE_SIZE 0x6000 +#define S3_DATA_MTRR_SIZE 0x1000 +#define S3_DATA_NONVOLATILE_SIZE 0x1000 #define S3_DATA_VOLATILE_POS CONFIG_S3_VOLATILE_POS -#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + 0x6000) +#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + S3_DATA_VOLATILE_SIZE) +#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE) typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type

1 0

Patch merged into coreboot/master: 5f83f6c armv7: Clean up arm/snow bootblock build process.
by gerrit＠coreboot.org 07 Feb '13

07 Feb '13

the following patch was just integrated into master: commit 5f83f6cb7a3f179482db54aaff38f23795dc1acf Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Feb 4 14:38:03 2013 +0800 armv7: Clean up arm/snow bootblock build process. Remove duplicated / testing code and share more driver for bootblock, romstage and ramstage. The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is executed before RAM is initialized. Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2282 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Feb 7 04:56:12 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Feb 7 06:10:08 2013, giving +2 See http://review.coreboot.org/2282 for details. -gerrit

1 0

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coreboot February 2013